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Mon, 6 Jun 2022 04:26:23 -0700 Envelope-to: git@xilinx.com, broonie@kernel.org, p.yadav@ti.com, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, michael@walle.cc, linux-mtd@lists.infradead.org Received: from [10.140.6.18] (port=43350 helo=xhdlakshmis40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1nyAsI-0000SR-EU; Mon, 06 Jun 2022 04:26:22 -0700 From: Amit Kumar Mahapatra To: , , , , CC: , , , , , , , Amit Kumar Mahapatra Subject: [RFC PATCH 1/2] spi: Add multiple CS support for a single SPI device Date: Mon, 6 Jun 2022 16:56:06 +0530 Message-ID: <20220606112607.20800-2-amit.kumar-mahapatra@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220606112607.20800-1-amit.kumar-mahapatra@xilinx.com> References: <20220606112607.20800-1-amit.kumar-mahapatra@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7f4e835a-f573-4bad-36d6-08da47af6422 X-MS-TrafficTypeDiagnostic: MW4PR02MB7282:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2022 11:26:25.0378 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7f4e835a-f573-4bad-36d6-08da47af6422 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0021.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR02MB7282 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org For supporting multiple CS the SPI device need to be aware of all the CS values. So the "chip_select" member in the spi_device structure is now an array that holds all the CS values. spi_device structure now has a "cs_index_mask" member. This acts as an index to the chip_select array. If nth bit of spi->cs_index_mask is set then the driver would assert spi->chip_slect[n]. When flashes are connected in stacked mode SPI-NOR will enable the required chip select by setting the appropriate bit in spi->cs_index_mask. In parallel connection both the flashes need to be asserted simultaneously, this can be achieved by enabling 0th(CS0) & 1st(CS1) bit in spi->cs_index_mask. Signed-off-by: Amit Kumar Mahapatra --- drivers/spi/spi-zynqmp-gqspi.c | 30 ++++++++++++++++++++++++++---- drivers/spi/spi.c | 10 +++++++--- include/linux/spi/spi.h | 10 +++++++++- 3 files changed, 42 insertions(+), 8 deletions(-) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index c760aac070e5..2535a8bca4da 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -136,6 +136,11 @@ #define GQSPI_MAX_NUM_CS 2 /* Maximum number of chip selects */ +#define GQSPI_SELECT_LOWER_CS BIT(0) +#define GQSPI_SELECT_UPPER_CS BIT(1) +#define GQSPI_SELECT_BOTH_CS (GQSPI_SELECT_LOWER_CS | \ + GQSPI_SELECT_UPPER_CS) + #define SPI_AUTOSUSPEND_TIMEOUT 3000 enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA}; @@ -361,16 +366,33 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high) struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master); ulong timeout; u32 genfifoentry = 0, statusreg; + u8 cs_index_mask = qspi->cs_index_mask; genfifoentry |= GQSPI_GENFIFO_MODE_SPI; if (!is_high) { - if (!qspi->chip_select) { - xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER; - xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER; - } else { + /* + * GQSPI controller only supports two chip selects, + * CS0 and CS1 + */ + if (cs_index_mask & GQSPI_SELECT_BOTH_CS) { + + xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER | + GQSPI_GENFIFO_BUS_UPPER; + xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER | + GQSPI_GENFIFO_CS_UPPER; + + } else if ((cs_index_mask & GQSPI_SELECT_UPPER_CS) && + (qspi->chip_select[GQSPI_SELECT_UPPER_CS - 1])) { + xqspi->genfifobus = GQSPI_GENFIFO_BUS_UPPER; xqspi->genfifocs = GQSPI_GENFIFO_CS_UPPER; + + } else if ((cs_index_mask & GQSPI_SELECT_LOWER_CS) && + (!qspi->chip_select[GQSPI_SELECT_LOWER_CS - 1])) { + + xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER; + xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER; } genfifoentry |= xqspi->genfifobus; genfifoentry |= xqspi->genfifocs; diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 2e6d6bbeb784..d3077874e6e8 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -2082,6 +2082,8 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, { u32 value; int rc; + u32 cs[SPI_CS_CNT_MAX]; + u8 idx; /* Mode (clock phase/polarity/etc.) */ if (of_property_read_bool(nc, "spi-cpha")) @@ -2154,13 +2156,15 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi, } /* Device address */ - rc = of_property_read_u32(nc, "reg", &value); - if (rc) { + rc = of_property_read_variable_u32_array(nc, "reg", &cs[0], + 1, SPI_CS_CNT_MAX); + if (rc < 0) { dev_err(&ctlr->dev, "%pOF has no valid 'reg' property (%d)\n", nc, rc); return rc; } - spi->chip_select = value; + for(idx = 0; idx < rc; idx++) + spi->chip_select[idx] = cs[idx]; /* Device speed */ if (!of_property_read_u32(nc, "spi-max-frequency", &value)) diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 5f8c063ddff4..e930d987f3c2 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -18,6 +18,9 @@ #include #include +/* Max no. of CS supported per spi device */ +#define SPI_CS_CNT_MAX 2 + struct dma_chan; struct software_node; struct ptp_system_timestamp; @@ -148,6 +151,7 @@ extern int spi_delay_exec(struct spi_delay *_delay, struct spi_transfer *xfer); * deasserted. If @cs_change_delay is used from @spi_transfer, then the * two delays will be added up. * @statistics: statistics for the spi_device + * @cs_index_mask: Bit mask of the active chipselect(s) in the chipselect array * * A @spi_device is used to interchange data between an SPI slave * (usually a discrete chip) and CPU memory. @@ -163,7 +167,7 @@ struct spi_device { struct spi_controller *controller; struct spi_controller *master; /* compatibility layer */ u32 max_speed_hz; - u8 chip_select; + u8 chip_select[SPI_CS_CNT_MAX]; u8 bits_per_word; bool rt; #define SPI_NO_TX BIT(31) /* no transmit wire */ @@ -194,6 +198,10 @@ struct spi_device { /* the statistics */ struct spi_statistics statistics; + /* Bit mask of the chipselect(s) that the driver + * need to use form the chipselect array. + */ + u8 cs_index_mask : 2; /* * likely need more hooks for more protocol options affecting how * the controller talks to each chip, like: From patchwork Mon Jun 6 11:26:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kumar Mahapatra X-Patchwork-Id: 581107 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97FC6C433EF for ; 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Mon, 6 Jun 2022 04:26:26 -0700 Envelope-to: git@xilinx.com, broonie@kernel.org, p.yadav@ti.com, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, michael@walle.cc, linux-mtd@lists.infradead.org Received: from [10.140.6.18] (port=43350 helo=xhdlakshmis40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1nyAsM-0000SR-2B; Mon, 06 Jun 2022 04:26:26 -0700 From: Amit Kumar Mahapatra To: , , , , CC: , , , , , , , Amit Kumar Mahapatra Subject: [RFC PATCH 2/2] mtd: spi-nor: Add support for stacked/parallel memories Date: Mon, 6 Jun 2022 16:56:07 +0530 Message-ID: <20220606112607.20800-3-amit.kumar-mahapatra@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220606112607.20800-1-amit.kumar-mahapatra@xilinx.com> References: <20220606112607.20800-1-amit.kumar-mahapatra@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ae01345c-a822-463d-a509-08da47af65fc X-MS-TrafficTypeDiagnostic: DM6PR02MB6137:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2022 11:26:28.1470 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ae01345c-a822-463d-a509-08da47af65fc X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0021.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB6137 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org While initializing the flash parameter structure, size of each flash is updated with the values coming from "stacked-memories" and "parallel-memories" DT properties. Two new nor->flags (SNOR_F_HAS_STACKED and SNOR_F_HAS_PARALLEL) are added to distinguish between the stacked and parallel configuration. In parallel configuration all the operations need to be performed on both the flashes simultaneously, So during each operation SPI-NOR needs to set 0th bit(CS0) & 1st bit(CS1) in nor->spimem->spi->cs_index_mask. The GQSPI driver will then assert CS0 & CS1. In stacked configuration the SPI-NOR, with individual flash size information, will determining the flash on which the operation need to be performed and it will set the appropriate CS bit in nor->spimem->spi->cs_index_mask. Signed-off-by: Amit Kumar Mahapatra --- drivers/mtd/spi-nor/core.c | 104 +++++++++++++++++++++++++++++++----- drivers/mtd/spi-nor/core.h | 5 ++ include/linux/mtd/spi-nor.h | 8 ++- 3 files changed, 104 insertions(+), 13 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 502967c76c5f..5d9bbb28659a 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2463,6 +2463,9 @@ static void spi_nor_init_fixup_flags(struct spi_nor *nor) */ static void spi_nor_late_init_params(struct spi_nor *nor) { + struct device_node *np = spi_nor_get_flash_node(nor); + u64 flash_size[SNOR_FLASH_CNT_MAX]; + if (nor->manufacturer && nor->manufacturer->fixups && nor->manufacturer->fixups->late_init) nor->manufacturer->fixups->late_init(nor); @@ -2479,6 +2482,27 @@ static void spi_nor_late_init_params(struct spi_nor *nor) */ if (nor->flags & SNOR_F_HAS_LOCK && !nor->params->locking_ops) spi_nor_init_default_locking_ops(nor); + + /* + * The flashes that are connected in stacked mode should be of same make. + * Except the flash size all other properties are identical for all the + * flashes connected in stacked mode. + * The flashes that are connected in parallel mode should be identical. + */ + if (!of_property_read_u64_array(np, "stacked-memories", &flash_size[0], SNOR_FLASH_CNT_MAX)) { + nor->flags |= SNOR_F_HAS_STACKED; + } else if (!of_property_read_u64_array(np, "parallel-memories", &flash_size[0], SNOR_FLASH_CNT_MAX)){ + nor->flags |= SNOR_F_HAS_PARALLEL; + } + + if (nor->flags & (SNOR_F_HAS_STACKED | SNOR_F_HAS_PARALLEL)) { + nor->params[1] = devm_kzalloc(nor->dev, sizeof(*nor->params[0]), GFP_KERNEL); + if (!nor->params[1]) + return -ENOMEM; + memcpy(nor->params[1], nor->params[0], sizeof(*nor->params[0])); + nor->params[1]->size = flash_size[1]; + } + return 0; } /** @@ -2614,8 +2638,8 @@ static int spi_nor_init_params(struct spi_nor *nor) { int ret; - nor->params = devm_kzalloc(nor->dev, sizeof(*nor->params), GFP_KERNEL); - if (!nor->params) + nor->params[0] = devm_kzalloc(nor->dev, sizeof(*nor->params[0]), GFP_KERNEL); + if (!nor->params[0]) return -ENOMEM; spi_nor_init_default_params(nor); @@ -2677,19 +2701,51 @@ static int spi_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) */ static int spi_nor_quad_enable(struct spi_nor *nor) { - if (!nor->params->quad_enable) - return 0; + u8 idx; + int err; - if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 || - spi_nor_get_protocol_width(nor->write_proto) == 4)) - return 0; + if (nor->flags & SNOR_F_HAS_PARALLEL) { + if (!nor->params[0]->quad_enable) + return 0; - return nor->params->quad_enable(nor); + if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 || + spi_nor_get_protocol_width(nor->write_proto) == 4)) + return 0; + /* + * In parallel mode both chip selects i.e., CS0 & + * CS1 need to be asserted simulatneously. + */ + nor->spimem->spi->cs_index_mask = SPI_NOR_ENABLE_BOTH_CS; + err = nor->params[0]->quad_enable(nor); + } else { + for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) { + if (nor->params[idx] != NULL) { + + if (!nor->params[idx]->quad_enable) + return 0; + + if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 || + spi_nor_get_protocol_width(nor->write_proto) == 4)) + return 0; + + /* + * Set the appropriate CS index before + * issuing the command. + */ + nor->spimem->spi->cs_index_mask = 0x01 << idx; + err = nor->params[idx]->quad_enable(nor); + if (err) + return err; + } + } + } + return err; } static int spi_nor_init(struct spi_nor *nor) { int err; + int idx; err = spi_nor_octal_dtr_enable(nor, true); if (err) { @@ -2730,7 +2786,25 @@ static int spi_nor_init(struct spi_nor *nor) */ WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET, "enabling reset hack; may not recover from unexpected reboots\n"); - nor->params->set_4byte_addr_mode(nor, true); + if (nor->flags & SNOR_F_HAS_PARALLEL) { + /* + * In parallel mode both chip selects i.e., CS0 & + * CS1 need to be asserted simulatneously. + */ + nor->spimem->spi->cs_index_mask = SPI_NOR_ENABLE_BOTH_CS; + nor->params[0]->set_4byte_addr_mode(nor, true); + } else { + for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) { + if (nor->params[idx] != NULL) { + /* + * Select the appropriate CS index before + * issuing the command. + */ + nor->spimem->spi->cs_index_mask = 0x01 << idx; + nor->params[idx]->set_4byte_addr_mode(nor, true); + } + } + } } return 0; @@ -2913,6 +2987,8 @@ static void spi_nor_set_mtd_info(struct spi_nor *nor) { struct mtd_info *mtd = &nor->mtd; struct device *dev = nor->dev; + u64 total_sz =0; + int idx; spi_nor_set_mtd_locking_ops(nor); spi_nor_set_mtd_otp_ops(nor); @@ -2926,9 +3002,13 @@ static void spi_nor_set_mtd_info(struct spi_nor *nor) mtd->flags |= MTD_NO_ERASE; else mtd->_erase = spi_nor_erase; - mtd->writesize = nor->params->writesize; - mtd->writebufsize = nor->params->page_size; - mtd->size = nor->params->size; + mtd->writesize = nor->params[0]->writesize; + mtd->writebufsize = nor->params[0]->page_size; + for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) { + if (nor->params[idx] != NULL) + total_sz += nor->params[idx]->size; + } + mtd->size = total_sz; mtd->_read = spi_nor_read; /* Might be already set by some SST flashes. */ if (!mtd->_write) diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 3f841ec36e56..4e8bf3cbe331 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -11,6 +11,9 @@ #define SPI_NOR_MAX_ID_LEN 6 +/* In parallel configuration enable both CS */ +#define SPI_NOR_ENABLE_BOTH_CS (BIT(0) | BIT(1)) + /* Standard SPI NOR flash operations. */ #define SPI_NOR_READID_OP(naddr, ndummy, buf, len) \ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 0), \ @@ -130,6 +133,8 @@ enum spi_nor_option_flags { SNOR_F_IO_MODE_EN_VOLATILE = BIT(11), SNOR_F_SOFT_RESET = BIT(12), SNOR_F_SWP_IS_VOLATILE = BIT(13), + SNOR_F_HAS_STACKED = BIT(14), + SNOR_F_HAS_PARALLEL = BIT(15), }; struct spi_nor_read_command { diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 1ede4c89805a..40800e7235ee 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -128,6 +128,12 @@ #define SR2_LB3 BIT(5) /* Security Register Lock Bit 3 */ #define SR2_QUAD_EN_BIT7 BIT(7) +/* + * Maximum number of flashes that can be connected + * in stacked/parallel configuration + */ +#define SNOR_FLASH_CNT_MAX 2 + /* Supported SPI protocols */ #define SNOR_PROTO_INST_MASK GENMASK(23, 16) #define SNOR_PROTO_INST_SHIFT 16 @@ -397,7 +403,7 @@ struct spi_nor { const struct spi_nor_controller_ops *controller_ops; - struct spi_nor_flash_parameter *params; + struct spi_nor_flash_parameter *params[SNOR_FLASH_CNT_MAX]; struct { struct spi_mem_dirmap_desc *rdesc;