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X-Received-From: 2607:f8b0:4864:20::431 Subject: [Qemu-devel] [PATCH 01/17] target/arm: Add MTE_ACTIVE to tb_flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When MTE is fully enabled, i.e. access to tags are enabled and tag checks affect the PE, then arrange to perform the check while stripping the TBI. The check is not yet implemented, just the plumbing to that point. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 13 +++++++++++ target/arm/helper-a64.h | 2 ++ target/arm/internals.h | 18 +++++++++++++++ target/arm/translate.h | 2 ++ target/arm/helper.c | 45 ++++++++++++++++++++++++++++---------- target/arm/mte_helper.c | 32 +++++++++++++++++++++++++++ target/arm/translate-a64.c | 9 +++++++- target/arm/Makefile.objs | 2 +- 8 files changed, 110 insertions(+), 13 deletions(-) create mode 100644 target/arm/mte_helper.c -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f2ff52f287..22163c9c3f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1164,6 +1164,7 @@ void pmccntr_sync(CPUARMState *env); #define PSTATE_BTYPE (3U << 10) #define PSTATE_IL (1U << 20) #define PSTATE_SS (1U << 21) +#define PSTATE_TCO (1U << 25) #define PSTATE_V (1U << 28) #define PSTATE_C (1U << 29) #define PSTATE_Z (1U << 30) @@ -1640,6 +1641,7 @@ FIELD(ID_AA64PFR0, SVE, 32, 4) FIELD(ID_AA64PFR1, BT, 0, 4) FIELD(ID_AA64PFR1, SBSS, 4, 4) +FIELD(ID_AA64PFR1, MTE, 8, 4) FIELD(ID_AA64MMFR0, PARANGE, 0, 4) FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) @@ -3003,6 +3005,7 @@ FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) FIELD(TBFLAG_A64, BTYPE, 10, 2) FIELD(TBFLAG_A64, TBID, 12, 2) +FIELD(TBFLAG_A64, MTE_ACTIVE, 14, 1) static inline bool bswap_code(bool sctlr_b) { @@ -3293,6 +3296,16 @@ static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; } +static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0; +} + +static inline bool isar_feature_aa64_mte(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2; +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index a915c1247f..fa4c371a47 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -102,3 +102,5 @@ DEF_HELPER_FLAGS_3(autda, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) + +DEF_HELPER_FLAGS_2(mte_check, TCG_CALL_NO_WG, i64, env, i64) diff --git a/target/arm/internals.h b/target/arm/internals.h index 587a1ddf58..6c018e773c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -983,4 +983,22 @@ static inline int exception_target_el(CPUARMState *env) return target_el; } +/* Determine if allocation tags are available. */ +static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, + uint64_t sctlr) +{ + if (el < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_ATA)) { + return false; + } + if (el < 2 + && arm_feature(env, ARM_FEATURE_EL2) + && !(arm_hcr_el2_eff(env) & HCR_ATA)) { + return false; + } + sctlr &= (el == 0 ? SCTLR_ATA0 : SCTLR_ATA); + return sctlr != 0; +} + #endif diff --git a/target/arm/translate.h b/target/arm/translate.h index 33af50a13f..5a101e1c6d 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -70,6 +70,8 @@ typedef struct DisasContext { bool ss_same_el; /* True if v8.3-PAuth is active. */ bool pauth_active; + /* True if v8.5-MTE tag checks affect the PE. */ + bool mte_active; /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ bool bt; /* diff --git a/target/arm/helper.c b/target/arm/helper.c index 6b7b639da5..038e52af4b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3465,22 +3465,31 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, { ARMCPU *cpu = arm_env_get_cpu(env); - if (raw_read(env, ri) == value) { - /* Skip the TLB flush if nothing actually changed; Linux likes - * to do a lot of pointless SCTLR writes. - */ - return; - } - if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { /* M bit is RAZ/WI for PMSA with no MPU implemented */ value &= ~SCTLR_M; } - raw_write(env, ri, value); + if (!cpu_isar_feature(aa64_mte, cpu)) { + if (ri->opc1 == 6) { /* SCTLR_EL3 */ + value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA); + } else { + value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF | + SCTLR_ATA0 | SCTLR_ATA); + } + } + /* ??? Lots of these bits are not implemented. */ - /* This may enable/disable the MMU, so do a TLB flush. */ - tlb_flush(CPU(cpu)); + + if (raw_read(env, ri) != value) { + /* + * This may enable/disable the MMU, so do a TLB flush. + * Skip the TLB flush if nothing actually changed; + * Linux likes to do a lot of pointless SCTLR writes. + */ + raw_write(env, ri, value); + tlb_flush(CPU(cpu)); + } } static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri, @@ -13087,6 +13096,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, if (is_a64(env)) { ARMCPU *cpu = arm_env_get_cpu(env); uint64_t sctlr; + int tbid; *pc = env->pc; flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); @@ -13095,7 +13105,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, { ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); - int tbii, tbid; + int tbii; /* FIXME: ARMv8.1-VHE S2 translation regime. */ if (regime_el(env, stage1) < 2) { @@ -13148,6 +13158,19 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); } + + /* + * If MTE is enabled, and tag checks affect the PE, + * then we check the tag as we strip the TBI field. + * Note that if TBI is disabled, all accesses are unchecked. + */ + if (tbid + && cpu_isar_feature(aa64_mte, cpu) + && allocation_tag_access_enabled(env, current_el, sctlr) + && !(env->pstate & PSTATE_TCO) + && (sctlr & (current_el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) { + flags = FIELD_DP32(flags, TBFLAG_A64, MTE_ACTIVE, 1); + } } else { *pc = env->regs[15]; flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c new file mode 100644 index 0000000000..a3226c44a4 --- /dev/null +++ b/target/arm/mte_helper.c @@ -0,0 +1,32 @@ +/* + * ARM v8.5-MemTag Operations + * + * Copyright (c) 2019 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "exec/exec-all.h" +#include "exec/cpu_ldst.h" +#include "exec/helper-proto.h" + + +uint64_t HELPER(mte_check)(CPUARMState *env, uint64_t ptr) +{ + /* Only unchecked implemented so far. */ + return sextract64(ptr, 0, 55); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ee6f71c98f..0286507bae 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -339,7 +339,13 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) { TCGv_i64 clean = new_tmp_a64(s); - gen_top_byte_ignore(s, clean, addr, s->tbid); + + /* FIXME: SP+OFS is always unchecked. */ + if (s->tbid && s->mte_active) { + gen_helper_mte_check(clean, cpu_env, addr); + } else { + gen_top_byte_ignore(s, clean, addr, s->tbid); + } return clean; } @@ -14000,6 +14006,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE); dc->bt = FIELD_EX32(tb_flags, TBFLAG_A64, BT); dc->btype = FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE); + dc->mte_active = FIELD_EX32(tb_flags, TBFLAG_A64, MTE_ACTIVE); dc->vec_len = 0; dc->vec_stride = 0; dc->cp_regs = arm_cpu->cp_regs; diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 1a4fc06448..c86cb1af5c 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -8,7 +8,7 @@ obj-y += translate.o op_helper.o helper.o cpu.o obj-y += neon_helper.o iwmmxt_helper.o vec_helper.o obj-y += gdbstub.o obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o helper-a64.o gdbstub64.o -obj-$(TARGET_AARCH64) += pauth_helper.o +obj-$(TARGET_AARCH64) += pauth_helper.o mte_helper.o obj-y += crypto_helper.o obj-$(CONFIG_SOFTMMU) += arm-powerctl.o From patchwork Mon Jan 14 01:11:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155389 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3114419jaa; Sun, 13 Jan 2019 17:14:28 -0800 (PST) X-Google-Smtp-Source: ALg8bN68e2b8cK/WYrFosQ4alie5CUEfnccdASdC9DQxfvtF0u4f1aAxalSe8W2tTQ5u45KJRc+/ X-Received: by 2002:a1c:a503:: with SMTP id o3mr9677110wme.122.1547428468204; Sun, 13 Jan 2019 17:14:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547428468; cv=none; d=google.com; s=arc-20160816; b=kWk0V9KLPcojvG4SB5ivmynmzjW1rrSc2UQt2qjF/MXmO36D5iFbniBHIXxFm6EP+F dqBzt0YSnvVA5x8O9DD9/gvSRWxOjvsJ9OmLS4JyIaFMODqlDz0TVtExRTvE4EzO5yAf Toa2sYvLWD+5Oz/iEV1dItZ1T3NLR1lXRL3Jbr4e9jwnXHqKjo7HWst8mI0Fb89DKkGB 8QoM0yjuiqYRGWbefVX88VhHvwzvnl3cJ3fzL9bO/pq2Tg8XDONoELBPEteCDHwQrVtO Kcxn34t+vkdRUfzZpmROR/SxpiY2ksJnP4CMgWvqPBl4lyb6n7s0rRl6i7mx6kWXI2DU TRvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=3J8t9aS2dh0pM+GMneyhpHvQ6P8FhxWkWFs9YiMs0mA=; b=Mq5fm9Ic5EcydqsnLYvMVXpjhJrU+Fgfteo8izLHaoPPur8lRsb5iwjh63ruU0u8mS X1I8+f2Tzhm6uBWyReGUMKD8iORIfTgrEQEynOctHgRMruaT28Khmofg8Ngvk7TtVAK6 iuYaT4Z+ykI6t3rMnykt30SqjvXqdLkdvpzw1XiCHbbxoob+Llg1QMiqMt96OgRsfZYB PWlwK3fQa9xsm7yep5t2AS+5xvtm7dfaC28Rt/38RfR4tk7bhPS/nGUsKsuvETKhFlPv IYRb5r5FkL5gL2P+z9JrMzUlNYH1QF5ffskaKGgX6R+b7zJWtlOacNegb998pnbjTsck OQnA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=b1XvGnKN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH 02/17] target/arm: Extract TCMA with ARMVAParameters X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/internals.h | 1 + target/arm/helper.c | 8 ++++++-- 2 files changed, 7 insertions(+), 2 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/internals.h b/target/arm/internals.h index 6c018e773c..2922324f63 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -959,6 +959,7 @@ typedef struct ARMVAParameters { bool tbid : 1; bool epd : 1; bool hpd : 1; + bool tcma : 1; bool using16k : 1; bool using64k : 1; } ARMVAParameters; diff --git a/target/arm/helper.c b/target/arm/helper.c index 038e52af4b..5a59fc4315 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9789,7 +9789,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, { uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; uint32_t el = regime_el(env, mmu_idx); - bool tbi, tbid, epd, hpd, using16k, using64k; + bool tbi, tbid, epd, hpd, tcma, using16k, using64k; int select, tsz; /* Bit 55 is always between the two regions, and is canonical for @@ -9803,11 +9803,12 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, using16k = extract32(tcr, 15, 1); if (mmu_idx == ARMMMUIdx_S2NS) { /* VTCR_EL2 */ - tbi = tbid = hpd = false; + tbi = tbid = hpd = tcma = false; } else { tbi = extract32(tcr, 20, 1); hpd = extract32(tcr, 24, 1); tbid = extract32(tcr, 29, 1); + tcma = extract32(tcr, 30, 1); } epd = false; } else if (!select) { @@ -9818,6 +9819,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, tbi = extract64(tcr, 37, 1); hpd = extract64(tcr, 41, 1); tbid = extract64(tcr, 51, 1); + tcma = extract64(tcr, 57, 1); } else { int tg = extract32(tcr, 30, 2); using16k = tg == 1; @@ -9827,6 +9829,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, tbi = extract64(tcr, 38, 1); hpd = extract64(tcr, 42, 1); tbid = extract64(tcr, 52, 1); + tcma = extract64(tcr, 58, 1); } tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ @@ -9838,6 +9841,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, .tbid = tbid, .epd = epd, .hpd = hpd, + .tcma = tcma, .using16k = using16k, .using64k = using64k, }; From patchwork Mon Jan 14 01:11:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155393 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3116872jaa; Sun, 13 Jan 2019 17:18:05 -0800 (PST) X-Google-Smtp-Source: ALg8bN5xAT3cpfjNqDPHXLB33Etk9yTWdzAGOXV/3RRFIG18t7LA6xphEy6Baj70SPaXLIiNb2CL X-Received: by 2002:a1c:48d:: with SMTP id 135mr9604135wme.1.1547428685024; Sun, 13 Jan 2019 17:18:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547428685; cv=none; d=google.com; s=arc-20160816; b=w3aHqHAcB/Zc/JyYyPWdVl/Jcv/dlqh4vgChG4Esi9ZeMkfxTcAHQoE88jKRsYjZsq OZ09ho5Nd0cUOnHSf5flE2AhGLSs6Ut1s84sKIFoRzzz2wkKOokIqTeFfo8mdzQBl4AV H+a+Wn1HDFEtIMOj+B4YVJF81eMjIx2cUy00s/Lc4Z1L6L3XIbbV0OwtZ77el9x1AVOk ILl4HXAxFvBS6QSMksSUfSFZrV2cUGfYFm6AeYycvRmwZ1N8jF6+wMIkYbwtYQ5HahH5 oUbLnCiP2tDlhQ6CBTSxyA7QLJ7BFB56deASMFHHua6Jfi6lxcJgWoz5Ozpc87Rwj5UX rnfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=U6gvtB4GZaUVNgdldGItRCxrxALoLGPnopUyctrDnBA=; b=tCEu1PDYvNk2auZf4/dBuEr5v4i2dYV7HzOF6q/Vj7pPUxz3R4oY32uyW1D2vyyNS6 tuwqm9bi2oEP0fs88xugGDygxVlRaH3am/4Hge3U8zHKxzIxo3yCNGoIXHamZnYRJQ9S 8S+rzqUReY2bIBZrXCbWsuNUOwI+hWBG6nrnZymmTFNsP4KPzSbQ98XIyu9ffqpMf/oy yi8QMPCv9xsPXgTBM4wlq1qSwSqhSYyOXjZWqRH+34knT4V4BQAJ0rIrNkmnCF0gZcco zLZmEjiImem1sqmXWlKfZ9GtPXfKFzi6nEBUY5rl5StKFeCJ6J2G3HRVmsHiZ2I8HUEV x17g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LZkLzi6p; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 59si49049349wrg.24.2019.01.13.17.18.04 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sun, 13 Jan 2019 17:18:05 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LZkLzi6p; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:55643 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqt9-0000sQ-Qf for patch@linaro.org; Sun, 13 Jan 2019 20:18:03 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36880) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqn2-0005UY-5U for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:11:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1giqn1-0000nA-6t for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:11:44 -0500 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:37205) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1giqn1-0000md-1v for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:11:43 -0500 Received: by mail-pf1-x443.google.com with SMTP id y126so9555195pfb.4 for ; Sun, 13 Jan 2019 17:11:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=U6gvtB4GZaUVNgdldGItRCxrxALoLGPnopUyctrDnBA=; b=LZkLzi6py4+2Uf1bP5l2zbgiqOZmn14PGSQZXkkSDsKebtWnGKXOzFu7AXpQ83f/+s 9HopvOL5tv4VXDdNrD4O0BJkdrOqCSh7rJNuLbRCFC7o2l+oHz87zc2/KvqoABtTGp1b SY9P9wlwbQ5GQwcvww+CHJtz6fnMJvRIlcWFQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=U6gvtB4GZaUVNgdldGItRCxrxALoLGPnopUyctrDnBA=; b=eLh8mYc0d7n3AWcNFWBzvXoIUYqxwUkCwshv6/DgrfOPtO6ox65kh2X8l+yEZdjzr9 AaQGG2X5CVpzRIjHO+P82rDeDXwrvJQ0sirKJHGTkooGkTfZo1sAyjSoxlP9QGslps60 sPxEyBt46it7wTgTrFPyzfD1JAtVcSOVCz2BUGP3KfhbWNwesHin2YmUFnFFAbLmA2zC ssiS+1ko+D+brelsDNYFNDByh6aQqGREl4pD8s1/FIjHEhiK4QpqMsDMwhR/wer4ubZl 8Crc15Rivn2KR26GuwlrIwEzjUzyW4VushhQwi3F+QtPuLsP8iPotZQqbZPlsru+iYX9 KuKg== X-Gm-Message-State: AJcUukdSNilZ1/r54pKfxb0iQ1pJQw4sIU/adsIT/Dj8OeFMBiD/srv+ PTe786fvtfXmZ72hFNQ78oUeLuWG7L0umw== X-Received: by 2002:a63:9256:: with SMTP id s22mr20518382pgn.224.1547428301751; Sun, 13 Jan 2019 17:11:41 -0800 (PST) Received: from cloudburst.twiddle.net ([2001:8000:1064:7600:4085:6ae6:1bde:1c45]) by smtp.gmail.com with ESMTPSA id 5sm159602229pfz.149.2019.01.13.17.11.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 13 Jan 2019 17:11:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 12:11:08 +1100 Message-Id: <20190114011122.5995-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190114011122.5995-1-richard.henderson@linaro.org> References: <20190114011122.5995-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH 03/17] target/arm: Add MTE system registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, RGSR_EL1, GCR_EL1, and PSTATE.TCO. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++++ target/arm/translate.h | 11 ++++++++++ target/arm/helper.c | 45 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 11 ++++++++++ 4 files changed, 72 insertions(+) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 22163c9c3f..c8b447e30a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -482,6 +482,11 @@ typedef struct CPUARMState { uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */ uint64_t vpidr_el2; /* Virtualization Processor ID Register */ uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */ +#ifdef TARGET_AARCH64 + uint64_t tfsr_el[4]; /* tfsrel0_el1 is index 0. */ + uint64_t gcr_el1; + uint64_t rgsr_el1; +#endif } cp15; struct { diff --git a/target/arm/translate.h b/target/arm/translate.h index 5a101e1c6d..a24757d3d7 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -204,6 +204,17 @@ static inline TCGv_i32 get_ahp_flag(void) return ret; } +/* Set bits within PSTATE. */ +static inline void set_pstate_bits(uint32_t bits) +{ + TCGv_i32 p = tcg_temp_new_i32(); + + tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); + tcg_gen_ori_i32(p, p, bits); + tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); + tcg_temp_free_i32(p); +} + /* Clear bits within PSTATE. */ static inline void clear_pstate_bits(uint32_t bits) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 5a59fc4315..df43deb0f8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5132,6 +5132,48 @@ static const ARMCPRegInfo pauth_reginfo[] = { .fieldoffset = offsetof(CPUARMState, apib_key.hi) }, REGINFO_SENTINEL }; + +static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_TCO; +} + +static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val) +{ + env->pstate = (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO); +} + +static const ARMCPRegInfo mte_reginfo[] = { + { .name = "TFSRE0_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 6, .crm = 6, .opc2 = 1, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[0]) }, + { .name = "TFSR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 6, .crm = 5, .opc2 = 0, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[1]) }, + { .name = "TFSR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 5, .opc2 = 0, + .access = PL2_RW, + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[2]) }, + { .name = "TFSR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 6, .opc2 = 0, + .access = PL3_RW, + .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[3]) }, + { .name = "RGSR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 5, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.rgsr_el1) }, + { .name = "GCR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6, + .access = PL1_RW, + .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) }, + { .name = "TCO", .state = ARM_CP_STATE_AA64, + .opc0 = 0, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, + .type = ARM_CP_NO_RAW, + .access = PL0_RW, .readfn = tco_read, .writefn = tco_write }, + REGINFO_SENTINEL +}; #endif void register_cp_regs_for_features(ARMCPU *cpu) @@ -5923,6 +5965,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_pauth, cpu)) { define_arm_cp_regs(cpu, pauth_reginfo); } + if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { + define_arm_cp_regs(cpu, mte_reginfo); + } #endif } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 0286507bae..5c2577a9ac 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1668,6 +1668,17 @@ static void handle_msr_i(DisasContext *s, uint32_t insn, s->base.is_jmp = DISAS_UPDATE; break; + case 0x1c: /* TCO */ + if (!dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + if (crm & 1) { + set_pstate_bits(PSTATE_TCO); + } else { + clear_pstate_bits(PSTATE_TCO); + } + break; + default: do_unallocated: unallocated_encoding(s); From patchwork Mon Jan 14 01:11:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155391 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3114765jaa; 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[209.51.188.17]) by mx.google.com with ESMTPS id c2si19167954wmk.151.2019.01.13.17.14.57 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sun, 13 Jan 2019 17:14:57 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gnny0ZGD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:55172 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqq8-0007os-MR for patch@linaro.org; Sun, 13 Jan 2019 20:14:56 -0500 Received: from eggs.gnu.org ([209.51.188.92]:36901) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqn6-0005Vb-Cf for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:11:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1giqn5-0000ox-Jm for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:11:48 -0500 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:44269) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1giqn5-0000oT-EE for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:11:47 -0500 Received: by mail-pl1-x636.google.com with SMTP id e11so9337510plt.11 for ; Sun, 13 Jan 2019 17:11:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=k193oIJuWHKJSh/ld1DTHsXHomhufh+pF4VSc8r0za4=; b=gnny0ZGDj+saAhIbe5JCMAVn9AaA9pJMSu8kjRZPumbLA/s/pX+5mWNidPVbOAJR64 1DE/laG55VGrZhL+ttIGQcpKh0thNJVq/rfj2D4HZNsTG9YnYaUJ3R5mRmc0kyiQgvLA l42xGTIWG+fQGCNOg028gdIL7gQ1KrCK4UC+Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=k193oIJuWHKJSh/ld1DTHsXHomhufh+pF4VSc8r0za4=; b=EeQZP0fYGUu49INuxAQsJhAKmLPNFuhOKicqmi1vn/Yahw9ijtOZalUSzld4cVBfMx O1o9dmdLXbmOWoNTdcXyR5GQe6PdlKl95vs/OSCWNNiI9BdQRVmg4Lv23NifoCQbIags 8sReqohOMd7722vSw3GeBSjWgzj2Iihd/DMiqa1HSulrvG2qkxN0bK37gkatoAo7WgXG gWQgbKF9e4JOkc+LxR0+RwP3JyKXTHJ+MkVCU5F6thhsnjcfOU1aEYDFrtxa2SS8kiK7 yhSECqKf/UuTkDMNs9BAjk0fxXbMAnUSe2vWKkmgqQUpqyavQYkufpRbTDybkIBKw2xR ubSQ== X-Gm-Message-State: AJcUukfx8HTncHNPYrkWmhX/vaaxWA0YmCClPo7hrn5sVnowV0pd2rAi R4HKgPH4Hlocg+AEio6869OlzMkVGVE4pQ== X-Received: by 2002:a17:902:7e0d:: with SMTP id b13mr23702510plm.154.1547428304988; Sun, 13 Jan 2019 17:11:44 -0800 (PST) Received: from cloudburst.twiddle.net ([2001:8000:1064:7600:4085:6ae6:1bde:1c45]) by smtp.gmail.com with ESMTPSA id 5sm159602229pfz.149.2019.01.13.17.11.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 13 Jan 2019 17:11:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 12:11:09 +1100 Message-Id: <20190114011122.5995-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190114011122.5995-1-richard.henderson@linaro.org> References: <20190114011122.5995-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::636 Subject: [Qemu-devel] [PATCH 04/17] target/arm: Fill in helper_mte_check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Implements the rules of "PE generation of Checked and Unchecked accesses" which aren't already covered by XXX. Implements the rules of "PE handling of Tag Check Failure". Does not implement tag physical address space, so all operations reduce to unchecked so far. Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 80 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index a3226c44a4..6f4bc0aa04 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -25,8 +25,86 @@ #include "exec/helper-proto.h" +static int get_allocation_tag(CPUARMState *env, uint64_t ptr) +{ + /* Tag storage not implemented. */ + return -1; +} + +static int allocation_tag_from_addr(uint64_t ptr) +{ + return (extract64(ptr, 56, 4) + extract64(ptr, 55, 1)) & 15; +} + uint64_t HELPER(mte_check)(CPUARMState *env, uint64_t ptr) { - /* Only unchecked implemented so far. */ + ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); + ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, true); + int ptr_tag, mem_tag; + + /* + * If TBI is disabled, then the access is unchecked. + * While we filtered out TBI0==0 && TBI1==0 in cpu_get_tb_cpu_state, + * we did not save separate bits for TBI0 != TBI1. + */ + if (!param.tbi) { + /* Do not ignore the top byte. */ + return ptr; + } + + /* + * If TCMA is enabled, then physical tag 0 is unchecked. + * Note the rules R0076 & R0077 are written with logical tags, + * and we need the physical tag below anyway. + */ + ptr_tag = allocation_tag_from_addr(ptr); + if (param.tcma && ptr_tag == 0) { + goto pass; + } + + /* + * If an access is made to an address that does not provide tag storage, + * the result is implementation defined (R0006). We choose to treat the + * access as unchecked. + * This is similar to MemAttr != Tagged, which are also unchecked. + */ + mem_tag = get_allocation_tag(env, ptr); + if (mem_tag < 0) { + goto pass; + } + + /* If the tags do not match, the tag check operation fails. */ + if (ptr_tag != mem_tag) { + int el = arm_current_el(env); + int tcf; + + /* Indicate the tag check fail, both async and sync reporting. */ + env->cp15.tfsr_el[el] |= 1 << param.select; + + if (el == 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + tcf = extract64(env->cp15.sctlr_el[1], 38, 2); + } else { + tcf = extract64(env->cp15.sctlr_el[el], 40, 2); + } + if (tcf == 1) { + /* Tag check fail causes a synchronous exception. */ + CPUState *cs = ENV_GET_CPU(env); + + /* + * In restore_state_to_opc, we set the exception syndrome + * for the load or store operation. Do that first so we + * may overwrite that with the syndrome for the tag check. + */ + cpu_restore_state(cs, GETPC(), true); + env->exception.vaddress = ptr; + raise_exception(env, EXCP_DATA_ABORT, + syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, 0x11), + exception_target_el(env)); + } + } + + pass: + /* Unchecked, or tag check pass. Ignore the top byte. */ return sextract64(ptr, 0, 55); } From patchwork Mon Jan 14 01:11:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155394 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3117084jaa; Sun, 13 Jan 2019 17:18:23 -0800 (PST) X-Google-Smtp-Source: ALg8bN7s5/kx69W2oWfAkUjdjh0vtq5vQpoOYG8u29HG0QTiJF+N1J7c06kfYERPozLg9J1XKQfB X-Received: by 2002:adf:fa90:: with SMTP id h16mr23439016wrr.326.1547428703176; Sun, 13 Jan 2019 17:18:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547428703; cv=none; d=google.com; s=arc-20160816; b=nFV3VLMoSbGwF0+Mn1et2RWzO2Gu7hZYR+Faz4W3HhnSUHdFELA/1GQqrAPfmr/hOS 8VMNOS/SJ9N9q3CAIbxal3NVpKlbfnmp76XVcToJH70PClFwVsUz1iIn1ZCoqm7kD+9x +O/c2TaugOcHJ21gjVUAf/B/5gcK0abTWJeU8Drrye8/Vbwd2nK92D3uuf4kiQ22r1co xxq5Snu5KwLhAyLHafcS8AHO3aToeBlL0Jm+04xsD/iFbbZNw/oGOexvISfWoBGbsPPQ 0DgLBippN1H/q4rY7y11uNo4s1NtqBbcwDv91Bt0Pd96m03wW4CY8bvaURUjxCaoIWcC i6Tg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=bXhPStNSlDCbXnTGxtTMCZgmzW/jvr/X9ejRqXKxxc8=; b=VqLpikId/3b1thrZv6qXQisojDX7S4pU3ZSxtSsHrsg8H2MopwggdfVpoIhkVX6PIA TdsTyTC4P2kmTG4ipLNFAxGsR7XeO+n9niT0hPX4E4Zm6spgn0/P+hNZn/VIZUwYNwFq XJdVfX1Ef0Fh7LCMXjdjfJq3nK/S9YyKuWieQ1wUrx7AqCp7Ne019CmJH/I3ngdOQJjm LURcC394i37RrIYgzO4WesxdjWIfOBhOxO36yUAL2LfaDiqO+Pt3t+fTo8MFRpMBNlid xg7N3sidz2Jox6gU647oOXyKhdZF2mP65WbZBvQKJxVvR8yoedMIcZbT/ejPbNppnAbP Exzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OhsAcvJl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 05/17] target/arm: Suppress tag check for sp+offset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" R0078 specifies that base register, or base register plus immediate offset, is unchecked when the base register is SP. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 37 ++++++++++++++++++------------------- 1 file changed, 18 insertions(+), 19 deletions(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5c2577a9ac..ee95ba7165 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -336,12 +336,11 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src) * This is always a fresh temporary, as we need to be able to * increment this independently of a dirty write-back address. */ -static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) +static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr, bool sp_off) { TCGv_i64 clean = new_tmp_a64(s); - /* FIXME: SP+OFS is always unchecked. */ - if (s->tbid && s->mte_active) { + if (s->tbid && s->mte_active && !sp_off) { gen_helper_mte_check(clean, cpu_env, addr); } else { gen_top_byte_ignore(s, clean, addr, s->tbid); @@ -2374,7 +2373,7 @@ static void gen_compare_and_swap(DisasContext *s, int rs, int rt, if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn == 31); tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx, size | MO_ALIGN | s->be_data); } @@ -2392,7 +2391,7 @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn == 31); if (size == 2) { TCGv_i64 cmp = tcg_temp_new_i64(); @@ -2517,7 +2516,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn == 31); gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false); return; @@ -2526,7 +2525,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn == 31); s->is_ldex = true; gen_load_exclusive(s, rt, rt2, clean_addr, size, false); if (is_lasr) { @@ -2546,7 +2545,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) gen_check_sp_alignment(s); } tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn == 31); do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; @@ -2562,7 +2561,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn == 31); do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); @@ -2576,7 +2575,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn == 31); gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true); return; } @@ -2594,7 +2593,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn == 31); s->is_ldex = true; gen_load_exclusive(s, rt, rt2, clean_addr, size, true); if (is_lasr) { @@ -2784,7 +2783,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) if (!postindex) { tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); } - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = clean_data_tbi(s, dirty_addr, rn == 31); if (is_vector) { if (is_load) { @@ -2922,7 +2921,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, if (!post_index) { tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); } - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = clean_data_tbi(s, dirty_addr, rn == 31); if (is_vector) { if (is_store) { @@ -3029,7 +3028,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = clean_data_tbi(s, dirty_addr, false); if (is_vector) { if (is_store) { @@ -3114,7 +3113,7 @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, dirty_addr = read_cpu_reg_sp(s, rn, 1); offset = imm12 << size; tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = clean_data_tbi(s, dirty_addr, rn == 31); if (is_vector) { if (is_store) { @@ -3198,7 +3197,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn, if (rn == 31) { gen_check_sp_alignment(s); } - clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn), rn == 31); tcg_rs = read_cpu_reg(s, rs, true); if (o3_opc == 1) { /* LDCLR */ @@ -3259,7 +3258,7 @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn, tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); /* Note that "clean" and "dirty" here refer to TBI not PAC. */ - clean_addr = clean_data_tbi(s, dirty_addr); + clean_addr = clean_data_tbi(s, dirty_addr, rn == 31); tcg_rt = cpu_reg(s, rt); do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false, @@ -3413,7 +3412,7 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) elements = (is_q ? 16 : 8) / ebytes; tcg_rn = cpu_reg_sp(s, rn); - clean_addr = clean_data_tbi(s, tcg_rn); + clean_addr = clean_data_tbi(s, tcg_rn, rn == 31); tcg_ebytes = tcg_const_i64(ebytes); for (r = 0; r < rpt; r++) { @@ -3547,7 +3546,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) } tcg_rn = cpu_reg_sp(s, rn); - clean_addr = clean_data_tbi(s, tcg_rn); + clean_addr = clean_data_tbi(s, tcg_rn, rn == 31); tcg_ebytes = tcg_const_i64(ebytes); for (xs = 0; xs < selem; xs++) { From patchwork Mon Jan 14 01:11:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155398 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3119336jaa; Sun, 13 Jan 2019 17:22:00 -0800 (PST) X-Google-Smtp-Source: ALg8bN4fF0XdBBlKSQwauxYQ3N+Ndy+PSMimEMAmsRyMvlpS4/LoNDGQnimmIi8bPYy9cxg1XKbu X-Received: by 2002:a5d:43d0:: with SMTP id v16mr23361141wrr.67.1547428920626; Sun, 13 Jan 2019 17:22:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547428920; cv=none; d=google.com; s=arc-20160816; b=visF+gjRxq5g5sz5vYJZUKuGzlyi+0jyloR6joRAmMCJ72Zf431VjUglYC6cdDIPU9 sQXdb4h+5P0u9tqVaCy7hXTNrBX56QEVy8a2noX29I5BwPY+vCoeoFGd0S63n94CzfNC ZfZIBa3yNNfqYkavb5w0uhc28YFBAQJHiMVy6Dhqj2pAuW0lWxZaEL7ZLAUKV/Sn4+Cl mamrgszs+WtH4KfKyBORIDLLVQw7EV12EaZz4453hAPYDeD9sA/xvAsPTjyVum1U8RRM 1bE9KsjCIWKc2Ks6x5b7q8ESYdjcfyNNbJEJDOCS6qOcGOe5lkAtnDzt9ePg5AIm8dyy 1yIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=2PYs5yE9xS8a3r0HkYRgoMY35uJiqcAT1vOz7tayvVQ=; b=PSp3cSdPfvFCLCwyUigoxOlCz9eNpaLURZWog/Nyi2H7wg6FGiWC9SWzi3JkhPVUS1 xmgejEFWrrIsBHepu/KtjqzsyxwPfwhPkE+bw/cUAZ8vlKj3KNdMGxiz/s2iBYO35xHw dvta/spXIRJBrhNRiJ444vymqTyT4rlFjOkl/2rf0/rGC/BTtcO3V7zULb0HyZoPt5qK /a3SOj9uVdLNvJSAW3TDf1E+R6IfIapEasGtI+i9/IKDO+2gAYh90P0SWrjIVnyvuf9E +q7Vxqd6K37BXYmFvysTVrcFjfLJbdU0miptA1zbH2ptJrJ1dKcmU+EfosBRsPiCUQQ3 +bdQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Zdq5yMz0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH 06/17] target/arm: Implement the IRG instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 1 + target/arm/mte_helper.c | 55 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 7 +++++ 3 files changed, 63 insertions(+) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index fa4c371a47..7a6051fdab 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -104,3 +104,4 @@ DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(mte_check, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 6f4bc0aa04..1878393fc4 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -36,6 +36,48 @@ static int allocation_tag_from_addr(uint64_t ptr) return (extract64(ptr, 56, 4) + extract64(ptr, 55, 1)) & 15; } +/* Like ChooseNonExcludedTag, except that GCR_EL1 is already in. */ +static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude) +{ + if (exclude != 0xffff) { + int i; + for (i = 0; i < offset; ++i) { + do { + tag = (tag + 1) & 15; + } while (exclude & (1 << tag)); + } + } + return tag; +} + +static int choose_random_nonexcluded_tag(CPUARMState *env, uint16_t exclude) +{ + /* Ignore GCR_EL1.RRND. Always produce deterministic results. */ + int start = extract32(env->cp15.rgsr_el1, 0, 4); + int seed = extract32(env->cp15.rgsr_el1, 8, 16); + int offset, rtag, i; + + /* RandomTag */ + for (i = offset = 0; i < 4; ++i) { + /* NextRandomTagBit */ + int top = (extract32(seed, 5, 1) ^ extract32(seed, 3, 1) ^ + extract32(seed, 2, 1) ^ extract32(seed, 0, 1)); + seed = (top << 15) | (seed >> 1); + offset |= top << i; + } + rtag = choose_nonexcluded_tag(start, offset, exclude); + + env->cp15.rgsr_el1 = rtag | (seed << 8); + + return rtag; +} + +static uint64_t address_with_allocation_tag(uint64_t ptr, int rtag) +{ + rtag -= extract64(ptr, 55, 1); + return deposit64(ptr, 56, 4, rtag); +} + uint64_t HELPER(mte_check)(CPUARMState *env, uint64_t ptr) { ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); @@ -108,3 +150,16 @@ uint64_t HELPER(mte_check)(CPUARMState *env, uint64_t ptr) /* Unchecked, or tag check pass. Ignore the top byte. */ return sextract64(ptr, 0, 55); } + +uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) +{ + int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); + int rtag = 0; + + if (allocation_tag_access_enabled(env, el, sctlr)) { + uint16_t exclude = rm | env->cp15.gcr_el1; + rtag = choose_random_nonexcluded_tag(env, exclude); + } + return address_with_allocation_tag(rn, rtag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ee95ba7165..b0349bffc4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5105,6 +5105,13 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) case 3: /* SDIV */ handle_div(s, true, sf, rm, rn, rd); break; + case 4: /* IRG */ + if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + gen_helper_irg(cpu_reg_sp(s, rd), cpu_env, + cpu_reg_sp(s, rn), cpu_reg(s, rm)); + break; case 8: /* LSLV */ handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); break; From patchwork Mon Jan 14 01:11:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155402 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3121302jaa; Sun, 13 Jan 2019 17:25:11 -0800 (PST) X-Google-Smtp-Source: ALg8bN6e+FIXYTBkC9nzWica3ji7MEWDvKeML1WiPQWBLDsKHajPK1pa7gONAbV17bi6d3yL0xwB X-Received: by 2002:adf:9f10:: with SMTP id l16mr22769169wrf.206.1547429111003; Sun, 13 Jan 2019 17:25:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547429110; cv=none; d=google.com; s=arc-20160816; b=FoQc1BDsV09vEgO/LqzEeUOUXhOHx6PPPqcVwxqEgvSJw3gkkWT2ThLE9Q/oA/rA4M 0+vzPx4VRmWYOF0sHfb/ofvg6R/jqsAsgnwH9vrH7TYBgo+8ny5/g8lYWyVZ+Y/OpyGR 5XeJynvkJ5BJAYnX15tcGPni+oJeU8LGCIqgPUwjDzOtmmOEfXjIgin98Cv3b9hJ5x5k 4NsEEdW/J6G9LIhF85/1dUQesARmd0KfcWibdq1qQdpF518dVAcbhKW+qM6nRhycV8EC yRUFu4BsMVMjcxAFgTnLFx7BIDYM81XHEpAZiLl2ZKMmAIS48Q4aYb1++tJc55w8G9+r nVUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=zQWwHZdE0XEmu0eOmYlElX3aU8HsD5IKAzX45HBjqL0=; b=OenuM6ePv0Wsnx+jQm0KMosVGvrrow2I++cV7SM6SVndwHNWSbTwvSDK1q0bMaj5KU UQx78mje4zgSC7XtvbSkvrE6q63y4YOVpdT9q0es5u8WTi0E83UOijvQFF3OaTH8TF3L y6uN0kpjadJu7sGTVhdUuVCu/oKaEW0ARG9783Lx7riiXcW6llogGWrwMjrGcpEh76r1 UKvwWg4K3hbH6jz6w4+CPIa15Vq18QW7yf6GMKWGxQN24euBOofF/K9jehu27hUnhnMO FuKKNyrDUM9OUHGQ2Olvcku5MIBH3WRcOkCsGHEFdVTvAqvnjBYh3+R6igQOQEy68i7z 6c8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=eVakkAEg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 07/17] target/arm: Implement ADDG, SUBG instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 2 ++ target/arm/internals.h | 3 ++ target/arm/mte_helper.c | 34 ++++++++++++++++++ target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++------------ 4 files changed, 87 insertions(+), 23 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 7a6051fdab..47577207b2 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -105,3 +105,5 @@ DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(mte_check, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) +DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) diff --git a/target/arm/internals.h b/target/arm/internals.h index 2922324f63..a5a249b001 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1002,4 +1002,7 @@ static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, return sctlr != 0; } +/* We associate one allocation tag per 16 bytes, the minimum. */ +#define LOG2_TAG_GRANULE 4 + #endif diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 1878393fc4..e2b1a5dd40 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -163,3 +163,37 @@ uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) } return address_with_allocation_tag(rn, rtag); } + +uint64_t HELPER(addg)(CPUARMState *env, uint64_t ptr, + uint32_t offset, uint32_t tag_offset) +{ + int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); + int rtag = 0; + + if (allocation_tag_access_enabled(env, el, sctlr)) { + int start_tag = allocation_tag_from_addr(ptr); + uint16_t exclude = env->cp15.gcr_el1; + rtag = choose_nonexcluded_tag(start_tag, tag_offset, exclude); + } + + offset <<= LOG2_TAG_GRANULE; + return address_with_allocation_tag(ptr + offset, rtag); +} + +uint64_t HELPER(subg)(CPUARMState *env, uint64_t ptr, + uint32_t offset, uint32_t tag_offset) +{ + int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); + int rtag = 0; + + if (allocation_tag_access_enabled(env, el, sctlr)) { + int start_tag = allocation_tag_from_addr(ptr); + uint16_t exclude = env->cp15.gcr_el1; + rtag = choose_nonexcluded_tag(start_tag, tag_offset, exclude); + } + + offset <<= LOG2_TAG_GRANULE; + return address_with_allocation_tag(ptr - offset, rtag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b0349bffc4..879d6b8d46 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3652,7 +3652,9 @@ static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) * sf: 0 -> 32bit, 1 -> 64bit * op: 0 -> add , 1 -> sub * S: 1 -> set flags - * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12 + * shift: 00 -> LSL imm by 0, + * 01 -> LSL imm by 12 + * 10 -> ADDG, SUBG */ static void disas_add_sub_imm(DisasContext *s, uint32_t insn) { @@ -3663,10 +3665,10 @@ static void disas_add_sub_imm(DisasContext *s, uint32_t insn) bool setflags = extract32(insn, 29, 1); bool sub_op = extract32(insn, 30, 1); bool is_64bit = extract32(insn, 31, 1); + bool is_tag = false; TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd); - TCGv_i64 tcg_result; switch (shift) { case 0x0: @@ -3674,35 +3676,58 @@ static void disas_add_sub_imm(DisasContext *s, uint32_t insn) case 0x1: imm <<= 12; break; + case 0x2: + /* ADDG, SUBG */ + if (!is_64bit || setflags || (imm & 0x30) || + !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + is_tag = true; + break; default: + do_unallocated: unallocated_encoding(s); return; } - tcg_result = tcg_temp_new_i64(); - if (!setflags) { - if (sub_op) { - tcg_gen_subi_i64(tcg_result, tcg_rn, imm); - } else { - tcg_gen_addi_i64(tcg_result, tcg_rn, imm); - } - } else { - TCGv_i64 tcg_imm = tcg_const_i64(imm); - if (sub_op) { - gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); - } else { - gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); - } - tcg_temp_free_i64(tcg_imm); - } + if (is_tag) { + TCGv_i32 tag_offset = tcg_const_i32(imm & 15); + TCGv_i32 offset = tcg_const_i32(imm >> 6); - if (is_64bit) { - tcg_gen_mov_i64(tcg_rd, tcg_result); + if (sub_op) { + gen_helper_subg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset); + } else { + gen_helper_addg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset); + } + tcg_temp_free_i32(tag_offset); + tcg_temp_free_i32(offset); } else { - tcg_gen_ext32u_i64(tcg_rd, tcg_result); - } + TCGv_i64 tcg_result; - tcg_temp_free_i64(tcg_result); + if (!setflags) { + tcg_result = tcg_rd; + if (sub_op) { + tcg_gen_subi_i64(tcg_result, tcg_rn, imm); + } else { + tcg_gen_addi_i64(tcg_result, tcg_rn, imm); + } + } else { + TCGv_i64 tcg_imm = tcg_const_i64(imm); + tcg_result = new_tmp_a64(s); + if (sub_op) { + gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); + } else { + gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); + } + tcg_temp_free_i64(tcg_imm); + } + + if (is_64bit) { + tcg_gen_mov_i64(tcg_rd, tcg_result); + } else { + tcg_gen_ext32u_i64(tcg_rd, tcg_result); + } + } } /* The input should be a value in the bottom e bits (with higher From patchwork Mon Jan 14 01:11:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155396 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3119024jaa; Sun, 13 Jan 2019 17:21:27 -0800 (PST) X-Google-Smtp-Source: ALg8bN6Uxmd3qNUqpCOd+D+Hst/wvUVk9R7BtfY98iCjuyff6V0Ubmrrm+jfrk4NeKHf5uxWEWOZ X-Received: by 2002:a1c:1b4f:: with SMTP id b76mr9975877wmb.147.1547428887738; Sun, 13 Jan 2019 17:21:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547428887; cv=none; d=google.com; s=arc-20160816; b=ba1V10yLNqxOnJ57/BG9fWtuMoi4YQjO6XVxf8Z5+i09wlwa95PRlbE4TZtHNTChyG r9VJLQN8JdhJ1coE8euGJ7+G096Cp5sEvRKWVDhmhfueSH9fX7ev5N4svGifoN6fxgJU 2g3xx5e3gDOIlOA+xEHYAChCRcSVnfrwWmFHbn0GSJlk2vLtf+fIwW0pETOFU+Z98wtx VgYHgtH0Amy1Qd8rwdYtqN1GPvU4ZqUbeB1e3Rz6XPjrFyvj8Uu6CLjViOVNFce4DUhO SkILBk0JwDY4g1xz09+Xlx8QjdAA0xzl/3ESYrOBKarQSXAYWGElJo/o6Sz0J99i5FVg 1DiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=9sPdVbj9dZn6pAYd1DuwtQyLD564k7UzO/H76KQKWTg=; b=XET679P0LLcqUtweUnmfUI7qncrSVADkP2sHRCs7XEwYQuC2PSY7YNkvHvviAdQ7th n31ylplp91kqF/yl5cPWAgt0cyoYmFwUl2er/EMXQSXaxIo+5oKydxYcNYx2iG7seRto 4bvc7vsYcsoks90W0ojiCqF0xnHVVZihWZjmiBkmG4bY/wXmlLHYtoV1vHChJAd8+zHI ASgNbn02fJHa8iE8FZRKG1rdRyGpr0wgjzb9AsVi+3tLvVRnjspBJgAuWdrdX7q9b3E3 x7cNZYXletJ4mLJUSDOQX7eoiPPrS9ZGibebzX27GY+HzWQh6EgJxoZtWb+xDLOUVf3f mjSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="h5O/EScv"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s8si19258689wra.403.2019.01.13.17.21.27 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sun, 13 Jan 2019 17:21:27 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="h5O/EScv"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:56441 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqwQ-0003fu-Kg for patch@linaro.org; Sun, 13 Jan 2019 20:21:26 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37031) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqnH-0005gN-8a for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1giqnG-0000x3-Ia for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:11:59 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:38310) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1giqnG-0000vd-DE for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:11:58 -0500 Received: by mail-pg1-x543.google.com with SMTP id g189so8738527pgc.5 for ; Sun, 13 Jan 2019 17:11:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9sPdVbj9dZn6pAYd1DuwtQyLD564k7UzO/H76KQKWTg=; b=h5O/EScvfNzM+AhthVKf9PITJYqLSowqsuPE7s+Vw0zkSYTpmbF+dM1pkW+YmtRfok 6RJ8ZTkXme3Rjdc8V79/2knU4TjiyzRIxp2hwEsQZ9n6bzuNjPi+QzfAWIntrvM4K5B2 so/tWK4cIOikX3caPovNUOltOs6klTtHPJAos= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9sPdVbj9dZn6pAYd1DuwtQyLD564k7UzO/H76KQKWTg=; b=aY7YvdPJUNp+vn5WHmK3WtDLoC7bR+z4Lms/0wr0RmiXejsYMb6ZWKcURUaxhJ0/QV nR9LDoRyEGYJ9+O+SIlByDx+ixjHRjOJJY/o/uo1IQg9FvKk2rNJUVBqx4p6Faa42cb4 GYKDPlmTb/1JJr8LCn2vK1rOQ2Dd2H3xUfbCW6DFWhssXjHgeWX6ri5xo4qJJBIjxmO6 mLiCO3BaQ5XO5oHK7ALg2pdngVHeUMMMiahBuayhhmY3tuJHv1Tw0tKmv4tZPQCVPj/7 O0ZE8iER16rqxK3bTnkKokiN96PYwg5t4QlhKcdtYIwFdYpygUReDO2ONfYzFyEZMlPH +8Tw== X-Gm-Message-State: AJcUukepY/s9ogBuX4ropAqb6KzE9U8ZJqMGOCJiydOkJSxwkAAyCJVP 9A30DQ70qfs4xLR1mV5VA5g6yaAf2N9JCQ== X-Received: by 2002:aa7:8354:: with SMTP id z20mr23059498pfm.81.1547428317101; Sun, 13 Jan 2019 17:11:57 -0800 (PST) Received: from cloudburst.twiddle.net ([2001:8000:1064:7600:4085:6ae6:1bde:1c45]) by smtp.gmail.com with ESMTPSA id 5sm159602229pfz.149.2019.01.13.17.11.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 13 Jan 2019 17:11:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 12:11:13 +1100 Message-Id: <20190114011122.5995-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190114011122.5995-1-richard.henderson@linaro.org> References: <20190114011122.5995-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 08/17] target/arm: Implement the GMI instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 1 + target/arm/mte_helper.c | 6 ++++++ target/arm/translate-a64.c | 6 ++++++ 3 files changed, 13 insertions(+) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 47577207b2..ef340cb6f9 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -107,3 +107,4 @@ DEF_HELPER_FLAGS_2(mte_check, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) +DEF_HELPER_FLAGS_2(gmi, TCG_CALL_NO_RWG_SE, i64, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index e2b1a5dd40..2f6ac45150 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -197,3 +197,9 @@ uint64_t HELPER(subg)(CPUARMState *env, uint64_t ptr, offset <<= LOG2_TAG_GRANULE; return address_with_allocation_tag(ptr - offset, rtag); } + +uint64_t HELPER(gmi)(uint64_t ptr, uint64_t mask) +{ + int tag = allocation_tag_from_addr(ptr); + return mask | (1ULL << tag); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 879d6b8d46..6583ad93b1 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5137,6 +5137,12 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) gen_helper_irg(cpu_reg_sp(s, rd), cpu_env, cpu_reg_sp(s, rn), cpu_reg(s, rm)); break; + case 5: /* GMI */ + if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + gen_helper_gmi(cpu_reg(s, rd), cpu_reg_sp(s, rn), cpu_reg(s, rm)); + break; case 8: /* LSLV */ handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); break; From patchwork Mon Jan 14 01:11:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155392 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3115680jaa; Sun, 13 Jan 2019 17:16:22 -0800 (PST) X-Google-Smtp-Source: ALg8bN7VFxefWVSfgwyfnJGzRvlUb0KhzdlKMa0maGE6ROV8Z8R1qlQa5Mo4ETGSDjA6KX/oDmb7 X-Received: by 2002:a7b:c852:: with SMTP id c18mr9406224wml.49.1547428582522; Sun, 13 Jan 2019 17:16:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547428582; cv=none; d=google.com; s=arc-20160816; b=bZ47s5HAfJNhHa16mgBjqaVdWhhMOgL0WB7AsjscY/QIK1jTWn+OIFddpiQThX8ML+ wv3sIbNYxv4hvOBWrOLYqcM+XbV9W4f4kM6P2rpszrdIHEdLtTrPEMqzfQp8goXW6A3/ JKvibrWg8H9zK116wFe0PHQPEfMZUm3uGb9Omx5NyzMGujQCYQVT/GW1qwYnO2fuVYZl klArpiwPPjS+uAjbFtM4VuNu9WGHUyuVNMMlZNqDfrjBwcxArPOILehAXTkYDUcFg3o0 zndUMPwtxolmaeEVLrpl2Gm6f0Ljtvri2hr/vYkWQU0UtW1APs81JWm3wzXf1W3jIPa5 86Bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=iWhPOgkpsGfL+y7+DJO0d97xBYz3hpRVJdQBJAPKZLY=; b=Fff6ZPQXOOdqTAZB4N5LHMJ/X6bzM1xj7Wlpooxy4tX3m/SYQM4wKLyYRXjHoR/2xc 8tDzVl/o6mCBccjT/PKjLOLJkGD/H5/xIP60mvsn39Nbq5zVr61lGGeL9GtipiNHbrFI 93M5Eg9U9UVKx/9AFKP3QhGd7ic+XHNWzWGl8pCYdsAVMsNlFWfLj63i74153PtVH9aa KyEnQh5dQMnLG45vXegDURQrjE0F0mOP1jk0kyQHjrgUA5cT1C0y/VqWoUjyzgwfSTqP qQJZXIOTMyBSJHqmZoqyjUOvwyBb8tCYIOXDxVtbtV3cu2GYj59qOxT1IubCMol98GBS dGKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OBj9qFKj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w129si19264830wmb.25.2019.01.13.17.16.22 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sun, 13 Jan 2019 17:16:22 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OBj9qFKj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:55249 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqrV-000837-D3 for patch@linaro.org; Sun, 13 Jan 2019 20:16:21 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37057) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqnK-0005jP-D3 for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1giqnJ-0000zB-Mu for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:02 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:33364) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1giqnJ-0000yk-Hl for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:01 -0500 Received: by mail-pf1-x444.google.com with SMTP id c123so9556391pfb.0 for ; Sun, 13 Jan 2019 17:12:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iWhPOgkpsGfL+y7+DJO0d97xBYz3hpRVJdQBJAPKZLY=; b=OBj9qFKjvb9wJ25lBAGYi8YjdU2vI8RakjS0qpew4ZyAX7vuNZVBuMnVA1psKI4VvB ZSMyCNzj3l+hLRcxn3UdXwsw69rR5y8YIGC1mDYpIBGukcu6qpFvZoW7gNHdEtZ33hRs VsVbkE9fZGYBxmwxN1Dn3zesre2O+ln1HoddM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iWhPOgkpsGfL+y7+DJO0d97xBYz3hpRVJdQBJAPKZLY=; b=CfLuzvOnfB846KFItjGoBkyixxhRDdHr12PyIY3+o2+PAh03lDm7AF/U1Z+0E4mrNt MJuQNRkDv28G5iBUKwPZdk1s+rhPUvmpP5I7+0Tk0P3gOcgAonqg6sZg+yH7Kg+ZE0rO cFnLoSLFnp5KGqGU2Yx8Y1xm3CIT8RQhVQtTiO5TOYcmFSvjS4tyynjZ+IiymVvqjcX+ Nz5BBvjaulc4Z9MB34TIHwIrG2tCUuKay4q/T3HEnQtxXMUMnMcbRODvbROeb4cpQGkP LfBzO++3SYcWDb13He/hv1kiOWSVoHM8I8HZuIaypmXGVCDsklRZspvHEuBkgxjWZNh2 nUuQ== X-Gm-Message-State: AJcUukf7ucwcWCHqT2Cg0wnJu9870BmhUdeoQULX9g/Cb6iqnO7dMtSM azp93Dp7s4UysI0gVTy+U/tZp1cbMAwZjQ== X-Received: by 2002:a63:a41:: with SMTP id z1mr21085462pgk.117.1547428320372; Sun, 13 Jan 2019 17:12:00 -0800 (PST) Received: from cloudburst.twiddle.net ([2001:8000:1064:7600:4085:6ae6:1bde:1c45]) by smtp.gmail.com with ESMTPSA id 5sm159602229pfz.149.2019.01.13.17.11.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 13 Jan 2019 17:11:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 12:11:14 +1100 Message-Id: <20190114011122.5995-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190114011122.5995-1-richard.henderson@linaro.org> References: <20190114011122.5995-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 09/17] target/arm: Implement the SUBP instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 6583ad93b1..98ff60c161 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5111,19 +5111,39 @@ static void handle_crc32(DisasContext *s, */ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) { - unsigned int sf, rm, opcode, rn, rd; + unsigned int sf, rm, opcode, rn, rd, setflag; sf = extract32(insn, 31, 1); + setflag = extract32(insn, 29, 1); rm = extract32(insn, 16, 5); opcode = extract32(insn, 10, 6); rn = extract32(insn, 5, 5); rd = extract32(insn, 0, 5); - if (extract32(insn, 29, 1)) { + if (setflag && opcode != 0) { unallocated_encoding(s); return; } switch (opcode) { + case 0: /* SUBP(S) */ + if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } else { + TCGv_i64 tcg_n, tcg_m, tcg_d; + + tcg_n = read_cpu_reg_sp(s, rn, true); + tcg_m = read_cpu_reg_sp(s, rm, true); + tcg_gen_sextract_i64(tcg_n, tcg_n, 0, 55); + tcg_gen_sextract_i64(tcg_m, tcg_m, 0, 55); + tcg_d = cpu_reg(s, rd); + + if (setflag) { + gen_sub_CC(true, tcg_d, tcg_n, tcg_m); + } else { + tcg_gen_sub_i64(tcg_d, tcg_n, tcg_m); + } + } + break; case 2: /* UDIV */ handle_div(s, false, sf, rm, rn, rd); break; From patchwork Mon Jan 14 01:11:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155395 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3117872jaa; Sun, 13 Jan 2019 17:19:37 -0800 (PST) X-Google-Smtp-Source: ALg8bN4Z22K6CzhwN9UOMqeppRwhVzOo9d3lvTy4wq/hOgOyKn0kq038KztKp5JVCH8z4M/mYqcn X-Received: by 2002:a5d:4652:: with SMTP id j18mr22686448wrs.279.1547428777184; Sun, 13 Jan 2019 17:19:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547428777; cv=none; d=google.com; s=arc-20160816; b=tn+qDG/6a8VNZrcAcnIj7Uj9Jlc1OMWMEo53WWETbgi3No2pwhoR7qpd5DZmPylLvK xk8k3S0PPGLmYMQwlXzyFuJLDve3yZ73PYcG/Uteu271S+q3Xi32GQiBL2SymO1bVReb XIoegCAhp/KaRagHWPGwuY9hTQv9Zkn3GmmTUNP5jgXTmr1IrKyPsf+8eR69S/wj3jIo hVSRVv4e2INV901YiB/9zjJnXa1BO3aqbtMcVldbRyzymtXPkuGvpfNYhrL/Bb0x5nWX EGJgoII2S8I8HVfD6IaM28VRmHHPDhtpiq3V5f1k05RasSNii01+kiV5pp4ka0Pg2NZO lkFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=CdcikpfvgRTScnQTPdCBXTKkG5ZSgGsXmUil1ktXF7E=; b=BCPavIASs8kp29Suat+NL62q8B+a6fuRMv7/T6hXKAjINHvI/hSU6jB+Wdd+ORzLSa rlPgTMiKbrEbTUNSnWbO7lIZsHExvELCoUUqc28BACQO79+VnVaqtdpIaNUSAd+qw+RP yBbEx+20YTh4nW1lhGsC6sjtu8LP6Nr/Rj8Tu18UDWaC4GOkJAyBpf+qDanXiNtNjOeH g/HnNKvE1iUWV1ddmXQ4gcFV5lQ0YVGzD1M+5oJYdWBPGKeujCMto5SW/swgqlkTpFiA IPq+lJV6dZqUFFEH544G1h4lbagPR5WVg35tLiYcdQHkURTKoS7CyRG3PgSPC+o0/AZm lA0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NKkxLJLB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x7si5637629wrd.354.2019.01.13.17.19.36 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sun, 13 Jan 2019 17:19:37 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NKkxLJLB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:55979 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gique-000221-1J for patch@linaro.org; Sun, 13 Jan 2019 20:19:36 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37078) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqnO-0005ml-95 for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1giqnN-000111-6D for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:06 -0500 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:43030) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1giqnN-00010i-1F for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:05 -0500 Received: by mail-pf1-x441.google.com with SMTP id w73so9535309pfk.10 for ; Sun, 13 Jan 2019 17:12:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CdcikpfvgRTScnQTPdCBXTKkG5ZSgGsXmUil1ktXF7E=; b=NKkxLJLBtI2WKq+qSqY6IAk102KrW4TYpHy7SNywEPWtz4cBWpR7eObGyxXBL/pI8V OVvcosKxhjSyy6S/wHkUuKZ1oZScDQHjbBg7ywdTn1E8+tV0rl9mjbbWXCM2O5v7ZZn3 DiXvY2xTsUEhBGyqUU/BOw2Krp1t4/t9Ir3u0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CdcikpfvgRTScnQTPdCBXTKkG5ZSgGsXmUil1ktXF7E=; b=JXAfYaTiOQgvpvojnDIFNQGCa99HYwQy+CdUe51QJ3zUYWv+ODyHP1VjdaPOK5DbXZ 9mpXwUHUoCsVG91nglFbJaTu+XzB/fQ/zESKKj/NzwazxvUs+AMUP0Q/0c+E3lW9wE0O 9P+H3+N8ZTC210Wq4t3AoPsPp/UZ6SWqzHSPtS4B8nYbNsNtHFcVwhC8NNs6zJHSy6KJ bgYcEUh1JlchjFRWjjYth0ClKC5eYD7V+AMY+kcxm5ONBmgQP8MCQSsp+bPiLjeMXzud NdrsaodhnYC0/yD5t2IsvEzSj2Wmqs78vm2fzIsl7olCujh/KYJdj+2l6RMoFsqEgbwH J97w== X-Gm-Message-State: AJcUukeoVcGoQhrADUCz+XNPBTzcsqp03NrnTka7xqFZ4aIB+ujmFIau ZiztzIY0YC2FbQzlpc3TBB5C3DQJhgNrLA== X-Received: by 2002:a63:af52:: with SMTP id s18mr21297586pgo.385.1547428323725; Sun, 13 Jan 2019 17:12:03 -0800 (PST) Received: from cloudburst.twiddle.net ([2001:8000:1064:7600:4085:6ae6:1bde:1c45]) by smtp.gmail.com with ESMTPSA id 5sm159602229pfz.149.2019.01.13.17.12.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 13 Jan 2019 17:12:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 12:11:15 +1100 Message-Id: <20190114011122.5995-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190114011122.5995-1-richard.henderson@linaro.org> References: <20190114011122.5995-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH 10/17] target/arm: Implement LDG, STG, ST2G instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 3 ++ target/arm/mte_helper.c | 53 +++++++++++++++++++ target/arm/translate-a64.c | 106 +++++++++++++++++++++++++++++++++++++ 3 files changed, 162 insertions(+) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index ef340cb6f9..ff37c8975a 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -108,3 +108,6 @@ DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_4(addg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) DEF_HELPER_FLAGS_4(subg, TCG_CALL_NO_RWG_SE, i64, env, i64, i32, i32) DEF_HELPER_FLAGS_2(gmi, TCG_CALL_NO_RWG_SE, i64, i64, i64) +DEF_HELPER_FLAGS_2(ldg, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(stg, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(st2g, TCG_CALL_NO_WG, i64, env, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 2f6ac45150..06fd9c18f9 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -31,6 +31,12 @@ static int get_allocation_tag(CPUARMState *env, uint64_t ptr) return -1; } +static bool set_allocation_tag(CPUARMState *env, uint64_t ptr, int tag) +{ + /* Tag storage not implemented. */ + return false; +} + static int allocation_tag_from_addr(uint64_t ptr) { return (extract64(ptr, 56, 4) + extract64(ptr, 55, 1)) & 15; @@ -203,3 +209,50 @@ uint64_t HELPER(gmi)(uint64_t ptr, uint64_t mask) int tag = allocation_tag_from_addr(ptr); return mask | (1ULL << tag); } + +uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr) +{ + int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); + int rtag = 0; + + if (allocation_tag_access_enabled(env, el, sctlr)) { + rtag = get_allocation_tag(env, ptr); + if (rtag < 0) { + rtag = 0; + } + } + return address_with_allocation_tag(ptr, rtag); +} + +uint64_t HELPER(stg)(CPUARMState *env, uint64_t ptr) +{ + int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); + + if (allocation_tag_access_enabled(env, el, sctlr)) { + int tag = allocation_tag_from_addr(ptr); + set_allocation_tag(env, ptr, tag); + } + + /* Clean the pointer for use by stgz. */ + /* ??? Do we need a more precise TBI here? */ + return sextract64(ptr, 0, 55); +} + +uint64_t HELPER(st2g)(CPUARMState *env, uint64_t ptr) +{ + int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); + + if (allocation_tag_access_enabled(env, el, sctlr)) { + int tag = allocation_tag_from_addr(ptr); + if (set_allocation_tag(env, ptr, tag)) { + set_allocation_tag(env, ptr + (1 << LOG2_TAG_GRANULE), tag); + } + } + + /* Clean the pointer for use by stgz. */ + /* ??? Do we need a more precise TBI here? */ + return sextract64(ptr, 0, 55); +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 98ff60c161..60865945e4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3583,6 +3583,109 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) } } +/* + * Load/Store memory tags + * + * 31 30 29 24 22 21 12 10 5 0 + * +-----+-------------+-----+---+------+-----+------+------+ + * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt | + * +-----+-------------+-----+---+------+-----+------+------+ + */ +static void disas_ldst_tag(DisasContext *s, uint32_t insn) +{ + int rt = extract32(insn, 0, 5); + int rn = extract32(insn, 5, 5); + uint64_t offset = sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; + int op2 = extract32(insn, 10, 3); + int op1 = extract32(insn, 22, 2); + bool is_load = false, is_pair = false, is_zero = false; + int index = 0; + TCGv_i64 dirty_addr, clean_addr; + + if ((insn & 0xff200000) != 0xd9200000 + || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } + + switch (op1) { + case 0: /* STG */ + if (op2 != 0) { + /* STG */ + index = op2 - 2; + break; + } + goto do_unallocated; + case 1: + if (op2 != 0) { + /* STZG */ + is_zero = true; + index = op2 - 2; + } else { + /* LDG */ + is_load = true; + } + break; + case 2: + if (op2 != 0) { + /* ST2G */ + is_pair = true; + index = op2 - 2; + break; + } + goto do_unallocated; + case 3: + if (op2 != 0) { + /* STZ2G */ + is_pair = is_zero = true; + index = op2 - 2; + break; + } + goto do_unallocated; + + default: + do_unallocated: + unallocated_encoding(s); + return; + } + + dirty_addr = read_cpu_reg_sp(s, rn, true); + if (index <= 0) { + /* pre-index or signed offset */ + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + } + + clean_addr = tcg_temp_new_i64(); + if (is_load) { + gen_helper_ldg(cpu_reg(s, rt), cpu_env, dirty_addr); + } else if (is_pair) { + gen_helper_st2g(clean_addr, cpu_env, dirty_addr); + } else { + gen_helper_stg(clean_addr, cpu_env, dirty_addr); + } + + if (is_zero) { + TCGv_i64 tcg_zero = tcg_const_i64(0); + int mem_index = get_mem_index(s); + int i, n = (1 + is_pair) << LOG2_TAG_GRANULE; + + for (i = 0; i < n; i += 8) { + tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, MO_Q); + tcg_gen_addi_i64(clean_addr, clean_addr, 8); + } + tcg_temp_free_i64(tcg_zero); + } + tcg_temp_free_i64(clean_addr); + + if (index != 0) { + /* pre-index or post-index */ + if (index > 0) { + /* post-index */ + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + } + tcg_gen_mov_i64(cpu_reg_sp(s, rn), dirty_addr); + } +} + /* Loads and stores */ static void disas_ldst(DisasContext *s, uint32_t insn) { @@ -3607,6 +3710,9 @@ static void disas_ldst(DisasContext *s, uint32_t insn) case 0x0d: /* AdvSIMD load/store single structure */ disas_ldst_single_struct(s, insn); break; + case 0x19: /* Load/store tag */ + disas_ldst_tag(s, insn); + break; default: unallocated_encoding(s); break; From patchwork Mon Jan 14 01:11:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155399 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3119828jaa; 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[209.51.188.17]) by mx.google.com with ESMTPS id w203si18017968wma.43.2019.01.13.17.22.49 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sun, 13 Jan 2019 17:22:49 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=F0BObSRX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:56794 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqxj-0004hy-4m for patch@linaro.org; Sun, 13 Jan 2019 20:22:47 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37108) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqnQ-0005p8-JB for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1giqnP-00012K-Na for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:08 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:42151) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1giqnP-00011v-Ia for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:07 -0500 Received: by mail-pf1-x444.google.com with SMTP id 64so9532245pfr.9 for ; Sun, 13 Jan 2019 17:12:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=X08leWf/xNJZ1dHLJE3vkUkRS4X1tK3TxBJrpZ1VA/U=; b=F0BObSRXmP7jI7eDtpku8ieI/fHZUk4vCfE79owe3NzNNroeFtTePOCbhUaUR4oM5h bL3zwL8KQT3PBqPI9yPRLKMsSSkRjdOrEQKwz9k1+WLJQ4G5fRUMAV/TqnePZBueEptI XsQk6pHZsys/I2AffzHrGey7oWS5q0igPFWuk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=X08leWf/xNJZ1dHLJE3vkUkRS4X1tK3TxBJrpZ1VA/U=; b=mkl7Xtek63RYrGS5/ilPtTcJz5Fgv9Js1pYyDb5o8sdmTuxGxs81As9oCKaUO703gE Aah3EfAfTQguaVS1kOVT/aZKeZfId8WzS0q5OpYBCRfws/Le7ygGvQMnvpe5TiYFLCRv vkjHX9dKXOqkoS43zEU/BmNMwiWztnswfk7waZjWvx6a1yt7ERevovwkCoTEYJLo0HDF jQQvmy/NsxhSoXVbTnns/PMCHDI7y4Yrxyc7tYeS2Hbmxpuj3tu+aLm4+8BpWvKADZa+ /OQKPsb1mzKemd2d+LfMj7NYoXaYWmrCqrL78cHedwv5851UFpZr8Dzb6ZhKNouDnJgH MD5Q== X-Gm-Message-State: AJcUukciZASBXs4qub7L+uH7MWFc+H/iAQOnliDjZZ3UHqUDoqNMFkxC bqgu8qkg0FRvPTEHz+Hy3kCVpibkxz/YHQ== X-Received: by 2002:a62:ca05:: with SMTP id n5mr23390909pfg.154.1547428326344; Sun, 13 Jan 2019 17:12:06 -0800 (PST) Received: from cloudburst.twiddle.net ([2001:8000:1064:7600:4085:6ae6:1bde:1c45]) by smtp.gmail.com with ESMTPSA id 5sm159602229pfz.149.2019.01.13.17.12.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 13 Jan 2019 17:12:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 12:11:16 +1100 Message-Id: <20190114011122.5995-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190114011122.5995-1-richard.henderson@linaro.org> References: <20190114011122.5995-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 11/17] target/arm: Implement the STGP instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 60865945e4..911d6f06b3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2696,7 +2696,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn) * +-----+-------+---+---+-------+---+-------+-------+------+------+ * * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit - * LDPSW 01 + * LDPSW/STGP 01 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit * V: 0 -> GPR, 1 -> Vector * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index, @@ -2721,6 +2721,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) bool is_signed = false; bool postindex = false; bool wback = false; + bool set_tag = false; TCGv_i64 clean_addr, dirty_addr; @@ -2733,6 +2734,14 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) if (is_vector) { size = 2 + opc; + } else if (opc == 1 && !is_load) { + /* STGP */ + if (!dc_isar_feature(aa64_mte_insn_reg, s) || index == 0) { + unallocated_encoding(s); + return; + } + size = 3; + set_tag = true; } else { size = 2 + extract32(opc, 1, 1); is_signed = extract32(opc, 0, 1); @@ -2783,7 +2792,12 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn) if (!postindex) { tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); } - clean_addr = clean_data_tbi(s, dirty_addr, rn == 31); + if (set_tag) { + clean_addr = new_tmp_a64(s); + gen_helper_stg(clean_addr, cpu_env, dirty_addr); + } else { + clean_addr = clean_data_tbi(s, dirty_addr, rn == 31); + } if (is_vector) { if (is_load) { From patchwork Mon Jan 14 01:11:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155397 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3119088jaa; Sun, 13 Jan 2019 17:21:33 -0800 (PST) X-Google-Smtp-Source: ALg8bN5Wyx8IZZjp32WxuY7hOzkxHPwWn+sJllAtHT0NSO39whzJoQ956oObnjVIu1bI/Wfg/E8Z X-Received: by 2002:a1c:8acd:: with SMTP id m196mr9942329wmd.120.1547428893640; Sun, 13 Jan 2019 17:21:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547428893; cv=none; d=google.com; s=arc-20160816; b=mXKP+MvwuvfqcB40pZ9tr4RDkdi4atniWMcQgH+nnXYhKY9Qpu5cu4VM+VNnxUwEEB muyp4kFb/KpVtLLvaXbDH+ZaCqNY9f/ta4K3Uk6j8KPXn+uJfYHzmmfL6HjPCJtCKN8I lruJCNHkoqKB1SHl1nkmXWPQACf+rYPRKzn8bLtYPqpbvJFX2HPnPcHj5UNbF/Laq2Fo 4APy1Yd7v3IWhbX6uk4SYSpfSZbCFy37BL/ELPF7d14o6bowXH7AyWSU7m5CWioDXEVz jDMKbOwbmZNJ2gkkrcNMIZ2P64G2m7WT7ziRd2jqvTmj6Hd14uzUSEWYVKBwxIiRbu65 6nig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ahPLim/iyNOWm0ysZUMOW39UhmJ/M0Ol12YT99+6l5E=; b=L+1zkTy6BuPbqchz4oLsj+49HJGeHfthBZa6Wch2NSmrqEWHYyeBQ/M2cuIj2z7ETo e8W5Isut2zAHzQCRRoUPJJI22wh+NlzO2+EDlt6KnHwO2fQ+g4t2cW2cp6Truf/FBV3U pTIsoQIRRnVXtF5b9HlREHubTkaEid1dAuGwXUaiV1vgPLo/AWr0nju+fQjW341hINyi F7r3kVbK2aUbzM3/IgdysF6RaaKACFfjZQtOzW4NBXZUDfLrU3/5nKwG4orAD4PvJLXF 4ohMdEcHYiOv1gyWgW4/Do6lR0MENtoXcLFzzOdayLEeDJUPeKg8TbeONU/puMuTmMjL tpZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ffYZ7nR3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y16si47722580wrt.269.2019.01.13.17.21.33 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sun, 13 Jan 2019 17:21:33 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ffYZ7nR3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:56459 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqwW-0003ir-Fb for patch@linaro.org; Sun, 13 Jan 2019 20:21:32 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37127) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqnT-0005s7-Qb for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1giqnS-00013x-Rq for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:11 -0500 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:43667) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1giqnS-00013e-Mo for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:10 -0500 Received: by mail-pg1-x541.google.com with SMTP id v28so8722866pgk.10 for ; Sun, 13 Jan 2019 17:12:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ahPLim/iyNOWm0ysZUMOW39UhmJ/M0Ol12YT99+6l5E=; b=ffYZ7nR3c6JJJZUmhH/pRzwmYKAylpT/PLahKAYXLa5mtud4+NolqbYPELj/aBdHmc ZZ+vbUXhmaDtigFpy9YLit6hqGCi5vZ2QKJL124bArQvjqdsWSUy2b0ayi31yGAT4aq6 trYCNe69fUciI9tOtNGgV1zbRX4gU8DHQ3LU0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ahPLim/iyNOWm0ysZUMOW39UhmJ/M0Ol12YT99+6l5E=; b=RA7HjUKQ/TdWMehzple31THKjg/Pu9gwLCak9NXglxiokS197nchJUzhPPew1rAa14 IwsFnZuBKjNHl7IodpZ6uMfx5l3VJqgKg1lK7zO57SCGulCa4uexe1vIdiwjojS/mnu0 jCtU8XGrA+nqPIYj9R1qVGoz8OX7umlDC0NvObDUY0CXnW+ZV20HMJRe1oC1YlS+mka7 mZwj1UgTIZWiQG569a7ZeoRTDN1XnQ5N8oDojJRlQxKqjxiYppLAkyao5s/tl1QooJOm dPeYR+zcu3NeiUUxDgNLxrbbM5+BY6fcWGmxmPY1Da/tWLz1PT5i6iFlI1uKSa+hJovq PEKw== X-Gm-Message-State: AJcUukcXIGwnA8LrqzMQ5Da1tFsf8R26A6N0vlyyzBzeRHM0JKFAddjM Tdxjn241M5YN4zjot4yFwVRvUUMFAjbRPg== X-Received: by 2002:a63:9b11:: with SMTP id r17mr21283758pgd.416.1547428329438; Sun, 13 Jan 2019 17:12:09 -0800 (PST) Received: from cloudburst.twiddle.net ([2001:8000:1064:7600:4085:6ae6:1bde:1c45]) by smtp.gmail.com with ESMTPSA id 5sm159602229pfz.149.2019.01.13.17.12.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 13 Jan 2019 17:12:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 12:11:17 +1100 Message-Id: <20190114011122.5995-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190114011122.5995-1-richard.henderson@linaro.org> References: <20190114011122.5995-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 12/17] target/arm: Implement the LDGV and STGV instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 2 ++ target/arm/mte_helper.c | 51 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 34 ++++++++++++++++++++----- 3 files changed, 81 insertions(+), 6 deletions(-) -- 2.17.2 diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index ff37c8975a..5bbfe43c13 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -111,3 +111,5 @@ DEF_HELPER_FLAGS_2(gmi, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_2(ldg, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(stg, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(st2g, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(ldgv, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_3(stgv, TCG_CALL_NO_WG, void, env, i64, i64) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 06fd9c18f9..b125f49258 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -256,3 +256,54 @@ uint64_t HELPER(st2g)(CPUARMState *env, uint64_t ptr) /* ??? Do we need a more precise TBI here? */ return sextract64(ptr, 0, 55); } + +uint64_t HELPER(ldgv)(CPUARMState *env, uint64_t ptr) +{ + int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); + uint64_t ret; + int rtag, i; + + if (!allocation_tag_access_enabled(env, el, sctlr)) { + return 0; + } + + ptr = QEMU_ALIGN_DOWN(ptr, 1 << LOG2_TAG_GRANULE); + rtag = get_allocation_tag(env, ptr); + if (rtag < 0) { + /* The entire page does not have tags. */ + return 0; + } + + i = extract32(ptr, LOG2_TAG_GRANULE, 4); + ret = (uint64_t)rtag << i; + for (i++; i < 16; i++) { + rtag = get_allocation_tag(env, ptr + (i << LOG2_TAG_GRANULE)); + ret |= (uint64_t)rtag << i; + } + + return ret; +} + +void HELPER(stgv)(CPUARMState *env, uint64_t ptr, uint64_t val) +{ + int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); + int rtag, i; + + if (!allocation_tag_access_enabled(env, el, sctlr)) { + return; + } + + rtag = allocation_tag_from_addr(ptr); + ptr = QEMU_ALIGN_DOWN(ptr, 1 << LOG2_TAG_GRANULE); + if (!set_allocation_tag(env, ptr, rtag)) { + /* The entire page does not have tags. */ + return; + } + + i = extract32(ptr, LOG2_TAG_GRANULE, 4); + for (i++; i < 16; i++) { + set_allocation_tag(env, ptr + (i << LOG2_TAG_GRANULE), rtag); + } +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 911d6f06b3..b4226def40 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3612,7 +3612,7 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) uint64_t offset = sextract64(insn, 12, 9) << LOG2_TAG_GRANULE; int op2 = extract32(insn, 10, 3); int op1 = extract32(insn, 22, 2); - bool is_load = false, is_pair = false, is_zero = false; + bool is_load = false, is_pair = false, is_zero = false, is_tagv = false; int index = 0; TCGv_i64 dirty_addr, clean_addr; @@ -3644,17 +3644,29 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) /* ST2G */ is_pair = true; index = op2 - 2; - break; + } else { + /* STGV */ + if (s->current_el == 0 || offset != 0) { + goto do_unallocated; + } + is_tagv = true; + index = 1; } - goto do_unallocated; + break; case 3: if (op2 != 0) { /* STZ2G */ is_pair = is_zero = true; index = op2 - 2; - break; + } else { + /* LDGV */ + if (s->current_el == 0 || offset != 0 || rt == rn) { + goto do_unallocated; + } + is_load = is_tagv = true; + index = 1; } - goto do_unallocated; + break; default: do_unallocated: @@ -3669,7 +3681,17 @@ static void disas_ldst_tag(DisasContext *s, uint32_t insn) } clean_addr = tcg_temp_new_i64(); - if (is_load) { + if (is_tagv) { + if (is_load) { + gen_helper_ldgv(cpu_reg(s, rt), cpu_env, dirty_addr); + } else { + gen_helper_stgv(cpu_env, dirty_addr, cpu_reg(s, rt)); + } + + /* Post-increment with dirty = align_up(dirty, 16*TAG_GRANULE). */ + tcg_gen_ori_i64(dirty_addr, dirty_addr, (16 << LOG2_TAG_GRANULE) - 1); + tcg_gen_addi_i64(dirty_addr, dirty_addr, 1); + } else if (is_load) { gen_helper_ldg(cpu_reg(s, rt), cpu_env, dirty_addr); } else if (is_pair) { gen_helper_st2g(clean_addr, cpu_env, dirty_addr); From patchwork Mon Jan 14 01:11:18 2019 Content-Type: text/plain; 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X-Received-From: 2607:f8b0:4864:20::535 Subject: [Qemu-devel] [PATCH 13/17] target/arm: Set PSTATE.TCO on exception entry X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" R0085 specifies that exception handlers begin with tag checks overridden. Signed-off-by: Richard Henderson --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.2 Reviewed-by: Peter Maydell diff --git a/target/arm/helper.c b/target/arm/helper.c index df43deb0f8..1e9ccf0b2e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8830,7 +8830,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", env->elr_el[new_el]); - pstate_write(env, PSTATE_DAIF | new_mode); + pstate_write(env, PSTATE_DAIF | PSTATE_TCO | new_mode); env->aarch64 = 1; aarch64_restore_sp(env, new_el); From patchwork Mon Jan 14 01:11:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155401 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3121011jaa; Sun, 13 Jan 2019 17:24:44 -0800 (PST) X-Google-Smtp-Source: ALg8bN4EKsdLtFvQG1j+3f4PtRzLgTuvnrHyvR2I9E4wjctyFNcnpmKUFOKkvDFbViCuvi9ccxcp X-Received: by 2002:a05:6000:1251:: with SMTP id j17mr21542596wrx.315.1547429084673; Sun, 13 Jan 2019 17:24:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547429084; cv=none; d=google.com; s=arc-20160816; b=fa3jXW8749e4RHzhZIi6DF3CnYPcKxBu1w3cvHspoIFb6gSbncdZa18E6nHRlDYwec KWHTt1Tx+PTlZdZ+UXzqAeJfXPK3uKzulVFuSdlfPguP8wbNYAo+KHZ+baAVYY+0rpUR +gm+Owno4x8iy6Io3bWBKOO6k391O/moQDAOzMV7/gfcm2SaHgjR+pjbnHhYAWu7mr1/ JE0HouJgRMHBfcHkILkZ4VX+WCbDMeqRovokQrUl6o5McylVk3JALhwu4gkCrsdbPf77 Eqm4JvQliYXSCFAGqj8+Q5eDwvZxqSwQYeS/3YERUYReKHywCydvoKlGdeYeN0VVE1nw Bfzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=QEnnJ0lnXGNqeUVPB5fOxxV2hOiG+cnB1X7vEWDXqS0=; b=QGhZ4q/8VQlg1RprYJepA4RlGm75M+9u9zc43P65cKLtB050AfO1TBpZHlEC9u2eIk proePr4NFugOSzw4MycaGc+CzI9cbed0hw2adwChUpg20uqcylUGvKhsq8SrDxDT54XV RC77uN9phXPeDqkO8//JvSw4muy7VO0L0vcG709VbD0zeRpIA+OjbHlMz+0VxBgWfQ2A JGtY+ot58WqRM4M8/o9O8QnHVaAHeePGhXmuCoQcDM01jqVp+c1Xbdc4RXraiCMMRWSj 6Q70YvmPG1y+iWs2X7MpEFoV/JuX8X69RaPhJElckVI46ahrPKMg7PFLUZaXc6SEKVJl OiTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DwWoYC8H; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o204si18531499wme.148.2019.01.13.17.24.44 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sun, 13 Jan 2019 17:24:44 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DwWoYC8H; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:57274 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqzb-00065y-F6 for patch@linaro.org; Sun, 13 Jan 2019 20:24:43 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37183) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqni-000653-38 for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1giqnZ-00016v-1M for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:21 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:37008) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1giqnY-00016a-Rb for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:16 -0500 Received: by mail-pg1-x543.google.com with SMTP id c25so8739326pgb.4 for ; Sun, 13 Jan 2019 17:12:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QEnnJ0lnXGNqeUVPB5fOxxV2hOiG+cnB1X7vEWDXqS0=; b=DwWoYC8HbRPzOlRLwQsLFonSKFOPmWhpB51Y7KnksUeC/e7ZlwkyHiZo+qyZDNtKdq 4FL7XWzI8hQfYWMPgBaDFaaGMudBZyJEUdzbEZfUceONUkRyi3MrMhNVOi+fpY4g/NzB iAsL4wU1+haZCDKwNjEZZXn3rMzgmKtMvpTEY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QEnnJ0lnXGNqeUVPB5fOxxV2hOiG+cnB1X7vEWDXqS0=; b=GslDnE3Tmpxxfm/uHkAwPs7vZDr+p67ghaz42tMOUfbYCr46wrIvAXje95LWQZEn93 ruzUUVFnvycQtJ4Znzi/FdLkbOpwwIy+GKCzK5nuOsD8f+yh22Oc/1JfoO1FrMy6RJA6 X4M1BBjtJ2BJ99oJpD9O5kOqco7xEcD3+S3D6yR/pmydznoOpJjyY4M0hfFm9WMddOdS DAStOYg1qxgn1e6JJE8N1lkJ/kJ8u3lHBDi4jDPzCF3KsfPZiJQT78Tp/o0EjTOWxcLi Q52NPyfkP+eMbZYH726SyTc87BoYHBfsttNKWNH79b0cwy0h7n4hpgDpRrQozR6g96cY OLjw== X-Gm-Message-State: AJcUukc6e7ouH7ph/G2akX3dBf3TL7kakVT+q1UmrgnmiQT9OfO5seaH brgvV6NN1gSbzB+L/C0UANqC7xN7XqB+xQ== X-Received: by 2002:a63:ed42:: with SMTP id m2mr21204447pgk.147.1547428335527; Sun, 13 Jan 2019 17:12:15 -0800 (PST) Received: from cloudburst.twiddle.net ([2001:8000:1064:7600:4085:6ae6:1bde:1c45]) by smtp.gmail.com with ESMTPSA id 5sm159602229pfz.149.2019.01.13.17.12.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 13 Jan 2019 17:12:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 12:11:19 +1100 Message-Id: <20190114011122.5995-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190114011122.5995-1-richard.henderson@linaro.org> References: <20190114011122.5995-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 14/17] tcg: Introduce target-specific page data for user-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" At the same time, remember MAP_SHARED as PAGE_SHARED. When mapping new pages, make sure that old target-specific page data is removed. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 10 ++++++++-- accel/tcg/translate-all.c | 28 ++++++++++++++++++++++++++++ linux-user/mmap.c | 10 ++++++++-- linux-user/syscall.c | 4 ++-- 4 files changed, 46 insertions(+), 6 deletions(-) -- 2.17.2 diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 117d2fbbca..92ec47dc79 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -244,10 +244,14 @@ extern intptr_t qemu_host_page_mask; #define PAGE_WRITE_ORG 0x0010 /* Invalidate the TLB entry immediately, helpful for s390x * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() */ -#define PAGE_WRITE_INV 0x0040 +#define PAGE_WRITE_INV 0x0020 +/* Page is mapped shared. */ +#define PAGE_SHARED 0x0040 +/* For use with page_set_flags: page is being replaced; target_data cleared. */ +#define PAGE_RESET 0x0080 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) /* FIXME: Code that sets/uses this is broken and needs to go away. */ -#define PAGE_RESERVED 0x0020 +#define PAGE_RESERVED 0x0100 #endif #if defined(CONFIG_USER_ONLY) @@ -260,6 +264,8 @@ int walk_memory_regions(void *, walk_memory_regions_fn); int page_get_flags(target_ulong address); void page_set_flags(target_ulong start, target_ulong end, int flags); int page_check_range(target_ulong start, target_ulong len, int flags); +void *page_get_target_data(target_ulong address); +void *page_alloc_target_data(target_ulong address, size_t size); #endif CPUArchState *cpu_copy(CPUArchState *env); diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 639f0b2728..047cd2f50d 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -111,6 +111,7 @@ typedef struct PageDesc { unsigned int code_write_count; #else unsigned long flags; + void *target_data; #endif #ifndef CONFIG_USER_ONLY QemuSpin lock; @@ -2477,6 +2478,7 @@ int page_get_flags(target_ulong address) void page_set_flags(target_ulong start, target_ulong end, int flags) { target_ulong addr, len; + bool reset_target_data; /* This function should never be called with addresses outside the guest address space. If this assert fires, it probably indicates @@ -2493,6 +2495,8 @@ void page_set_flags(target_ulong start, target_ulong end, int flags) if (flags & PAGE_WRITE) { flags |= PAGE_WRITE_ORG; } + reset_target_data = !(flags & PAGE_VALID) || (flags & PAGE_RESET); + flags &= ~PAGE_RESET; for (addr = start, len = end - start; len != 0; @@ -2506,10 +2510,34 @@ void page_set_flags(target_ulong start, target_ulong end, int flags) p->first_tb) { tb_invalidate_phys_page(addr, 0); } + if (reset_target_data && p->target_data) { + g_free(p->target_data); + p->target_data = NULL; + } p->flags = flags; } } +void *page_get_target_data(target_ulong address) +{ + PageDesc *p = page_find(address >> TARGET_PAGE_BITS); + return p ? p->target_data : NULL; +} + +void *page_alloc_target_data(target_ulong address, size_t size) +{ + PageDesc *p = page_find(address >> TARGET_PAGE_BITS); + void *ret = NULL; + + if (p) { + ret = p->target_data; + if (!ret && (p->flags & PAGE_VALID)) { + p->target_data = ret = g_malloc0(size); + } + } + return ret; +} + int page_check_range(target_ulong start, target_ulong len, int flags) { PageDesc *p; diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 41e0983ce8..f83874b8c1 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -562,7 +562,11 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int prot, } } the_end1: - page_set_flags(start, start + len, prot | PAGE_VALID); + if ((flags & MAP_TYPE) == MAP_SHARED) { + prot |= PAGE_SHARED; + } + prot |= PAGE_RESET | PAGE_VALID; + page_set_flags(start, start + len, prot); the_end: #ifdef DEBUG_MMAP printf("ret=0x" TARGET_ABI_FMT_lx "\n", start); @@ -754,9 +758,11 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong old_size, new_addr = -1; } else { new_addr = h2g(host_addr); + /* FIXME: Move page flags (and target_data?) for each page. */ prot = page_get_flags(old_addr); page_set_flags(old_addr, old_addr + old_size, 0); - page_set_flags(new_addr, new_addr + new_size, prot | PAGE_VALID); + page_set_flags(new_addr, new_addr + new_size, + prot | PAGE_VALID | PAGE_RESET); } tb_invalidate_phys_range(new_addr, new_addr + new_size); mmap_unlock(); diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 280137da8c..715101816d 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -3845,8 +3845,8 @@ static inline abi_ulong do_shmat(CPUArchState *cpu_env, raddr=h2g((unsigned long)host_raddr); page_set_flags(raddr, raddr + shm_info.shm_segsz, - PAGE_VALID | PAGE_READ | - ((shmflg & SHM_RDONLY)? 0 : PAGE_WRITE)); + PAGE_VALID | PAGE_SHARED | PAGE_RESET | PAGE_READ | + (shmflg & SHM_RDONLY ? 0 : PAGE_WRITE)); for (i = 0; i < N_SHM_REGIONS; i++) { if (!shm_regions[i].in_use) { From patchwork Mon Jan 14 01:11:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155405 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3123104jaa; Sun, 13 Jan 2019 17:28:01 -0800 (PST) X-Google-Smtp-Source: ALg8bN5OoX9OKHz0ZvgjqQp843VDi7dqJFAcgNTy7/xp0TC2Hjk0K70Oqs4X5Lw/YKhL+FqrH9Fy X-Received: by 2002:adf:f848:: with SMTP id d8mr23455025wrq.178.1547429281896; Sun, 13 Jan 2019 17:28:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547429281; cv=none; d=google.com; s=arc-20160816; b=vQuDXNfRMiC1+rcONrDVQ71zolQ6YjtxEMX1AhpD2/+p0TRaj62cttKeSJEft8cpp2 WzTevwWXiq7KRwEVrK4cCCBp9JeuFt2Qsi45NrSrDYRWSrxvgmADVEyHXdyr721oN+UT J1tFj7/zbsiV2+PinQQqvJXZvaWeQxjaimQZ8pSD+KN9Am/yu3gAPcM0zPtE0MKJVV2y MN9NqFDzwsV0mEkr9o2uCB/KfXs503jywp0VFTHeuUpygAyUb6SCipBJWKxbao8NtUHD Vfr6i1IDST8J923EwvT5bs9pfTmZe1iY7Jg9aNzo5W0XmVvOcT66+/Ry54TSy1659tbN SAnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=b0Bd53fbJ2LZjbAcwZlwr3sBleKyMI9LmM/ZZ1rSte4=; b=GaGVCABOnOEAgevq7uB+3ulgkPKTrWcfYd4S7kdgAxGZjkn+3GWfrFHbGhzKgeGZml D9thYQwVhCug/CIVNu8WZ9DaZYRNuU/nTRQQhtCsPo3/2MueuwOBbC8X/Bktlnk8Ne7Z vj5I++Q3/8m5D+fXjktfkLjfoKFy5WEkOfoaaSteypR/nKEp2W1WftCLr4f6sZdENaTh Rc3ffpUWaOUrUyWbtUiVRrGzvsMlpQA22fHWg7cnkinM0R0Nuj/SvjGeMrF+yR9wcpYb lTPEdflqUrQYpqmr7xGMmcEHCAS+TPOkjfFBmy6kBBk1+a+4OiPGlWnjI9XsA5MC0cgW 5GOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WCyHgWDA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 15/17] target/arm: Add allocation tag storage for user-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 82 +++++++++++++++++++++++++++++++++++------ 1 file changed, 71 insertions(+), 11 deletions(-) -- 2.17.2 diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index b125f49258..87328c7a9a 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -25,16 +25,72 @@ #include "exec/helper-proto.h" -static int get_allocation_tag(CPUARMState *env, uint64_t ptr) +static int get_allocation_tag(CPUARMState *env, uint64_t ptr, uintptr_t ra) { +#ifdef CONFIG_USER_ONLY + uint64_t clean_ptr = extract64(ptr, 0, 56); + uint8_t *tags = page_get_target_data(clean_ptr); + + if (tags != NULL) { + uintptr_t index = extract64(clean_ptr, LOG2_TAG_GRANULE + 1, + TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); + return extract32(tags[index], (clean_ptr & 1) * 4, 4); + } else { + int flags = page_get_flags(clean_ptr); + + if (flags & PAGE_SHARED) { + /* There may be multiple mappings; pretend not implemented. */ + return -1; + } else if (flags & PAGE_VALID) { + /* Page is good, but no tags have been written: all are 0. */ + return 0; + } else { + /* Page is invalid: SIGSEGV. */ + env->exception.vaddress = ptr; + cpu_restore_state(ENV_GET_CPU(env), ra, true); + raise_exception(env, EXCP_DATA_ABORT, 0, 1); + } + } +#else /* Tag storage not implemented. */ return -1; +#endif } -static bool set_allocation_tag(CPUARMState *env, uint64_t ptr, int tag) +static bool set_allocation_tag(CPUARMState *env, uint64_t ptr, + int tag, uintptr_t ra) { +#ifdef CONFIG_USER_ONLY + uint64_t clean_ptr = extract64(ptr, 0, 56); + uint8_t *tags = page_get_target_data(clean_ptr); + uintptr_t index; + + if (tags == NULL) { + int flags = page_get_flags(clean_ptr); + size_t alloc_size; + + if (flags & PAGE_SHARED) { + /* There may be multiple mappings; pretend not implemented. */ + return false; + } else if (!(flags & PAGE_VALID)) { + /* Page is invalid: SIGSEGV. */ + env->exception.vaddress = ptr; + cpu_restore_state(ENV_GET_CPU(env), ra, true); + raise_exception(env, EXCP_DATA_ABORT, 0, 1); + } + + alloc_size = TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1); + tags = page_alloc_target_data(clean_ptr, alloc_size); + assert(tags != NULL); + } + index = extract64(clean_ptr, LOG2_TAG_GRANULE + 1, + TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); + tags[index] = deposit32(tags[index], (clean_ptr & 1) * 4, 4, tag); + return true; +#else /* Tag storage not implemented. */ return false; +#endif } static int allocation_tag_from_addr(uint64_t ptr) @@ -116,7 +172,7 @@ uint64_t HELPER(mte_check)(CPUARMState *env, uint64_t ptr) * access as unchecked. * This is similar to MemAttr != Tagged, which are also unchecked. */ - mem_tag = get_allocation_tag(env, ptr); + mem_tag = get_allocation_tag(env, ptr, GETPC()); if (mem_tag < 0) { goto pass; } @@ -217,7 +273,7 @@ uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr) int rtag = 0; if (allocation_tag_access_enabled(env, el, sctlr)) { - rtag = get_allocation_tag(env, ptr); + rtag = get_allocation_tag(env, ptr, GETPC()); if (rtag < 0) { rtag = 0; } @@ -232,7 +288,7 @@ uint64_t HELPER(stg)(CPUARMState *env, uint64_t ptr) if (allocation_tag_access_enabled(env, el, sctlr)) { int tag = allocation_tag_from_addr(ptr); - set_allocation_tag(env, ptr, tag); + set_allocation_tag(env, ptr, tag, GETPC()); } /* Clean the pointer for use by stgz. */ @@ -247,8 +303,10 @@ uint64_t HELPER(st2g)(CPUARMState *env, uint64_t ptr) if (allocation_tag_access_enabled(env, el, sctlr)) { int tag = allocation_tag_from_addr(ptr); - if (set_allocation_tag(env, ptr, tag)) { - set_allocation_tag(env, ptr + (1 << LOG2_TAG_GRANULE), tag); + uintptr_t ra = GETPC(); + + if (set_allocation_tag(env, ptr, tag, ra)) { + set_allocation_tag(env, ptr + (1 << LOG2_TAG_GRANULE), tag, ra); } } @@ -261,6 +319,7 @@ uint64_t HELPER(ldgv)(CPUARMState *env, uint64_t ptr) { int el = arm_current_el(env); uint64_t sctlr = arm_sctlr(env, el); + uintptr_t ra = GETPC(); uint64_t ret; int rtag, i; @@ -269,7 +328,7 @@ uint64_t HELPER(ldgv)(CPUARMState *env, uint64_t ptr) } ptr = QEMU_ALIGN_DOWN(ptr, 1 << LOG2_TAG_GRANULE); - rtag = get_allocation_tag(env, ptr); + rtag = get_allocation_tag(env, ptr, ra); if (rtag < 0) { /* The entire page does not have tags. */ return 0; @@ -278,7 +337,7 @@ uint64_t HELPER(ldgv)(CPUARMState *env, uint64_t ptr) i = extract32(ptr, LOG2_TAG_GRANULE, 4); ret = (uint64_t)rtag << i; for (i++; i < 16; i++) { - rtag = get_allocation_tag(env, ptr + (i << LOG2_TAG_GRANULE)); + rtag = get_allocation_tag(env, ptr + (i << LOG2_TAG_GRANULE), ra); ret |= (uint64_t)rtag << i; } @@ -289,6 +348,7 @@ void HELPER(stgv)(CPUARMState *env, uint64_t ptr, uint64_t val) { int el = arm_current_el(env); uint64_t sctlr = arm_sctlr(env, el); + uintptr_t ra = GETPC(); int rtag, i; if (!allocation_tag_access_enabled(env, el, sctlr)) { @@ -297,13 +357,13 @@ void HELPER(stgv)(CPUARMState *env, uint64_t ptr, uint64_t val) rtag = allocation_tag_from_addr(ptr); ptr = QEMU_ALIGN_DOWN(ptr, 1 << LOG2_TAG_GRANULE); - if (!set_allocation_tag(env, ptr, rtag)) { + if (!set_allocation_tag(env, ptr, rtag, ra)) { /* The entire page does not have tags. */ return; } i = extract32(ptr, LOG2_TAG_GRANULE, 4); for (i++; i < 16; i++) { - set_allocation_tag(env, ptr + (i << LOG2_TAG_GRANULE), rtag); + set_allocation_tag(env, ptr + (i << LOG2_TAG_GRANULE), rtag, ra); } } From patchwork Mon Jan 14 01:11:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155403 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3121672jaa; Sun, 13 Jan 2019 17:25:49 -0800 (PST) X-Google-Smtp-Source: ALg8bN4zhjx/QzuxSwHAV0+xXiIrjuIHjJs8kdo8w4UcMZkzTv8Ts9vOXwYbTS8WYpDa7PcxJjij X-Received: by 2002:adf:9c01:: with SMTP id f1mr22891277wrc.286.1547429149026; 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[209.51.188.17]) by mx.google.com with ESMTPS id y13si19644014wrr.124.2019.01.13.17.25.48 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sun, 13 Jan 2019 17:25:49 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=U0blRyQh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:57541 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gir0d-00072c-Qi for patch@linaro.org; Sun, 13 Jan 2019 20:25:47 -0500 Received: from eggs.gnu.org ([209.51.188.92]:37244) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1giqnt-0006GG-Q2 for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1giqnr-0001Et-II for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:37 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:35608) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1giqnr-00019N-8K for qemu-devel@nongnu.org; Sun, 13 Jan 2019 20:12:35 -0500 Received: by mail-pg1-x543.google.com with SMTP id s198so8751217pgs.2 for ; Sun, 13 Jan 2019 17:12:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6RIgZQ3EkiygyRv4b+cnL5vicFb0iiKuZZbxL+UVxSM=; b=U0blRyQhnYNnW7z0eO6Vt6oNYTPRtwgvrl4LL/gUWrKmqYhwjO4ky9GkXLBvPqjZIo KHV6g1JwHL3JCN03K5+Fx+8CXJ4KaITXJHAgqfrL3HPH1aLvcyijLgepvIk5QcE1eD3X fu5lJHedH4il3Q9BQMd9jGQ5GBd//mrhKEmrM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6RIgZQ3EkiygyRv4b+cnL5vicFb0iiKuZZbxL+UVxSM=; b=L4k7fcBdhA7mPoenZM8n2QxCuOccGpK1v0eGVMrKfX6VT0B8Wff9A4j0x+n55GWZa0 w5dvm3pFqt1JXaDUoqo5eJcDi3Wt8lf0s+bOvzBfVmbb57XuVCJJoSXmNEc7qNWMnOas 5hvsHzpuPTtJcgJ8ue5BMVaEMbTBS+qRTkizpfFB54yQD0rC0S5aRa9To2AtBPESem5b HMOl82XeOMKefDECk7vM9TVKFnpHZFbJpTQ6g+mMKxvqz8X4FCy+XpQFBz+ang/zJfYw 51AHreCrTeinFU3cVYT7unFfk4KfZ2Tj9QSKzPl9wSOXPjko/WqvXoCf6cXmre43Oqys Owmg== X-Gm-Message-State: AJcUukfQErd5yMiX7my74pCsy2ZTElcuRpP478GO+K49sPQUp7maC7ZD txplxUx93wXlJ59jX0QI27g5fmnRbGmySg== X-Received: by 2002:a63:9256:: with SMTP id s22mr20519846pgn.224.1547428342219; Sun, 13 Jan 2019 17:12:22 -0800 (PST) Received: from cloudburst.twiddle.net ([2001:8000:1064:7600:4085:6ae6:1bde:1c45]) by smtp.gmail.com with ESMTPSA id 5sm159602229pfz.149.2019.01.13.17.12.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 13 Jan 2019 17:12:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 14 Jan 2019 12:11:21 +1100 Message-Id: <20190114011122.5995-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190114011122.5995-1-richard.henderson@linaro.org> References: <20190114011122.5995-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 16/17] target/arm: Enable MTE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" ??? It does not yet work for system mode. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 10 ++++++++++ target/arm/cpu64.c | 1 + 2 files changed, 11 insertions(+) -- 2.17.2 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5eff6995ee..aae30207b9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -180,6 +180,16 @@ static void arm_cpu_reset(CPUState *s) * make no difference to the user-level emulation. */ env->cp15.tcr_el[1].raw_tcr = (3ULL << 37); + /* Enable MTE allocation tags. */ + env->cp15.hcr_el2 |= HCR_ATA; + env->cp15.scr_el3 |= SCR_ATA; + env->cp15.sctlr_el[1] |= SCTLR_ATA0; + /* Enable synchronous tag check failures. */ + env->cp15.sctlr_el[1] |= 1ull << 38; +#ifdef TARGET_AARCH64 + /* Set MTE seed to non-zero value, otherwise RandomTag fails. */ + env->cp15.rgsr_el1 = 0x123400; +#endif #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 64fbe75eca..49fdad69ce 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -374,6 +374,7 @@ static void aarch64_max_initfn(Object *obj) t = cpu->isar.id_aa64pfr1; t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); + t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2); cpu->isar.id_aa64pfr1 = t; t = cpu->isar.id_aa64mmfr1; From patchwork Mon Jan 14 01:11:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 155404 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3122811jaa; Sun, 13 Jan 2019 17:27:36 -0800 (PST) X-Google-Smtp-Source: ALg8bN7JY/foSr4B9CLD/G1EtFI1qW+vVoyY+IwSOLsIeIXG7VRfVECpv9RiKwAASS727eii4/13 X-Received: by 2002:a1c:87cc:: with SMTP id j195mr9660480wmd.2.1547429256581; Sun, 13 Jan 2019 17:27:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1547429256; cv=none; d=google.com; s=arc-20160816; b=WyBd5xHon23sZrMOtq+mc6c3tHfoJWinIc0yUKixTvpfVoV3YfAa3MPAAS48th9s05 MuQ6ofwmWLgG11GpnnG6x5mmR+kLTKd8lIgHF7t4cFRVX8vK7tMLIuUMaqY4+j2BXgIk EsPo2JZmrPAnOr7KXH6E7Hi2gsbc3Pq9Le2EMYgXmSphQWeQnmhoMFY+H8GzqUmgjSR9 LvEnWJRjX464LZX5cCiwhNCm7iC/foE9C9+6Jiagub57TT13HRnKRT5XP97lME9yfxBx FmlSQJ+Fer2iQ+i94uD7yGdTGnSwO4PGmaf/hQhCE6N7LJ40k7GJLuMKJpad3QrvR42N BecQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=RF1blEfpbrvZ+eBn0f+rgZeNzRwB/ONHSYLlKUEqtWI=; b=qTufZJnDzG480DYleBUbBvsrkayYaA9OB/FOHSqSLvlfn1TUO9kCA90XdbNzU3fdCP AyCWO1c+f4Xjkm6jHjgO2HU1mMH3ThUHwhmRm0aq/QvS/5SEOdCcJU1OSamZc0F4m4Co phTWPGRoxtUZX7bW2PrrPt16/13ONZnEqKXuKzm4015Rtr+aU3XOaQQkI1Vb0Tr5zt+w WdIt4SywW+C9zMUwS3A42+4oEavbX6xtNDoCYS7eQAlDv+zWLgC1gub0XF6IOTvwe0LK 1Rk1PUR1lczjLCNMA0TFESicUlV4mDfwRgCT61oGLMhLo8SOk22A4jeIwN5rwJNulZPl Bj9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=TER98Q5N; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH 17/17] tests/tcg/aarch64: Add mte smoke tests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" ??? Requires a quite recent aarch64 assembler. Use .inst instead? Signed-off-by: Richard Henderson --- tests/tcg/aarch64/mte-1.c | 27 +++++++++++++++++++++ tests/tcg/aarch64/mte-2.c | 39 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 4 ++++ 3 files changed, 70 insertions(+) create mode 100644 tests/tcg/aarch64/mte-1.c create mode 100644 tests/tcg/aarch64/mte-2.c -- 2.17.2 diff --git a/tests/tcg/aarch64/mte-1.c b/tests/tcg/aarch64/mte-1.c new file mode 100644 index 0000000000..740bf506f1 --- /dev/null +++ b/tests/tcg/aarch64/mte-1.c @@ -0,0 +1,27 @@ +/* + * Memory tagging, basic pass cases. + */ + +#include + +asm(".arch armv8.5-a+memtag"); + +int data[16 / sizeof(int)] __attribute__((aligned(16))); + +int main(int ac, char **av) +{ + int *p0 = data; + int *p1, *p2; + long c; + + asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(1)); + assert(p1 != p0); + asm("subp %0,%1,%2" : "=r"(c) : "r"(p0), "r"(p1)); + assert(c == 0); + + asm("stg [%0]" : : "r"(p1)); + asm("ldg %0, [%1]" : "=r"(p2) : "r"(p0)); + assert(p1 == p2); + + return 0; +} diff --git a/tests/tcg/aarch64/mte-2.c b/tests/tcg/aarch64/mte-2.c new file mode 100644 index 0000000000..4d2004ab41 --- /dev/null +++ b/tests/tcg/aarch64/mte-2.c @@ -0,0 +1,39 @@ +/* + * Memory tagging, basic fail cases. + */ + +#include +#include +#include + +asm(".arch armv8.5-a+memtag"); + +int data[16 / sizeof(int)] __attribute__((aligned(16))); + +void pass(int sig) +{ + exit(0); +} + +int main(int ac, char **av) +{ + int *p0 = data; + int *p1, *p2; + long excl = 1; + + /* Create two differently tagged pointers. */ + asm("irg %0,%1,%2" : "=r"(p1) : "r"(p0), "r"(excl)); + asm("gmi %0,%1,%0" : "+r"(excl) : "r" (p1)); + assert(excl != 1); + asm("irg %0,%1,%2" : "=r"(p2) : "r"(p0), "r"(excl)); + assert(p1 != p2); + + /* Store the tag from the first pointer. */ + asm("stg [%0]" : : "r"(p1)); + + *p1 = 0; + signal(SIGSEGV, pass); + *p2 = 0; + + assert(0); +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 3d56e7c6ea..1c4ebe894c 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -19,4 +19,8 @@ AARCH64_TESTS += bti-1 bti-1: LDFLAGS += -nostartfiles -nodefaultlibs -nostdlib run-bti-1: QEMU += -cpu max,guarded_pages=on +AARCH64_TESTS += mte-1 mte-2 +mte-%: CFLAGS += -O -g +run-mte-%: QEMU += -cpu max + TESTS:=$(AARCH64_TESTS)