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([2602:ae:1547:e101:3fb8:a3e1:bf34:75a2]) by smtp.gmail.com with ESMTPSA id q133-20020a632a8b000000b003c14af505fesm8932165pgq.22.2022.06.05.09.10.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Jun 2022 09:10:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 1/2] target/arm: SCR_EL3 bits 4,5 are always res0 Date: Sun, 5 Jun 2022 09:10:55 -0700 Message-Id: <20220605161056.293920-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220605161056.293920-1-richard.henderson@linaro.org> References: <20220605161056.293920-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These bits do not depend on whether or not el1 supports aa32. Signed-off-by: Richard Henderson --- target/arm/helper.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 40da63913c..c262b00c3c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1752,11 +1752,8 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) ARMCPU *cpu = env_archcpu(env); if (ri->state == ARM_CP_STATE_AA64) { - if (arm_feature(env, ARM_FEATURE_AARCH64) && - !cpu_isar_feature(aa64_aa32_el1, cpu)) { - value |= SCR_FW | SCR_AW; /* these two bits are RES1. */ - } - valid_mask &= ~SCR_NET; + value |= SCR_FW | SCR_AW; /* RES1 */ + valid_mask &= ~SCR_NET; /* RES0 */ if (cpu_isar_feature(aa64_ras, cpu)) { valid_mask |= SCR_TERR; From patchwork Sun Jun 5 16:10:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 578873 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp3318309max; Sun, 5 Jun 2022 09:17:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyxnXsJiuSnW0UTZXWiczgRSeUsfICRkWcymQh8dAXG7AvjEkJ1jh26Uh1h6R7+LR5ukcnC X-Received: by 2002:a05:6214:1c84:b0:461:e0e0:2baf with SMTP id ib4-20020a0562141c8400b00461e0e02bafmr70385899qvb.59.1654445859451; Sun, 05 Jun 2022 09:17:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654445859; cv=none; d=google.com; s=arc-20160816; b=wQTgqsqGU0fcam/UYKdJnSwIVsQ3dTxavhJkDFthcEHEm2wxzd+JiicBEPQGAnCWeK /sIUYLIKRVtrwylN3LeZrz/BrDmXKMeMpb4BkG5B7V81VS+JXHYiLGskoOpJLezGejeV OPzgmEYNexzySFTKNFm+vGIYBaEwWqB87HN/deHN0hYvILmCM3LKavMXQ1igHh7ZsK0/ /pLwTebW1NqwsEgLVzpvXxdPYeGNMhVPtQv8bKGhBvjV0EjnGok/9Jp44FPNOr2fVEFJ Y0jA87RuDj0fFqvYBfEqKxJWsXBZfX8hX5SdeL3NzcPvQMFJ7OA5xMNDS/lgPRb+dpfJ sDdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=BiCy+cPE5Fp9O9R0zWpEP/6dC1PqcMNp2AcNLHCUCp0=; b=QR/mcLmPk9WnQWpyYlBJJpu8lc+3/6fYcrzC/Eld0ymMS7oTouJtUZp4TLhEncIcA8 PJFoLVnaDNxFeDhHwTGujs1YTEmPi+VdvKB0n4dTAF+vMzuXAAj4MufK02IBkWMbl/FO 7mbrRhLs0RH5mo9EJx0k5FvL7vJXxrRLNOH7I8SNr/Dry77AwRse3vyxR/w9+fFRp8/n vi5J/JbseaDDX+XFGN8fJr8F6Df9D/FvZUYOVBribFmjw+J526u1i2MWM0trySN3LIS8 Eoft0UiBExz7ezvu3u/J4NexxQMGxKiqyr98o4i/ILdcjtVgdYzklp4MzkJ2P/HGDVp6 3WsA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=d1L4lCEg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:3fb8:a3e1:bf34:75a2]) by smtp.gmail.com with ESMTPSA id q133-20020a632a8b000000b003c14af505fesm8932165pgq.22.2022.06.05.09.11.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Jun 2022 09:11:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 2/2] target/arm: SCR_EL3.RW is RAO/WI without AArch32 EL[12] Date: Sun, 5 Jun 2022 09:10:56 -0700 Message-Id: <20220605161056.293920-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220605161056.293920-1-richard.henderson@linaro.org> References: <20220605161056.293920-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since DDI0487F.a, the RW bit is RAO/WI. When specifically targeting such a cpu, e.g. cortex-a76, it is legitimate to ignore the bit within the secure monitor. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1062 Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 +++++ target/arm/helper.c | 4 ++++ 2 files changed, 9 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c1865ad5da..a7c45d0d66 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3947,6 +3947,11 @@ static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2; } +static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2; +} + static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index c262b00c3c..84232a6437 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1755,6 +1755,10 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) value |= SCR_FW | SCR_AW; /* RES1 */ valid_mask &= ~SCR_NET; /* RES0 */ + if (!cpu_isar_feature(aa64_aa32_el1, cpu) && + !cpu_isar_feature(aa64_aa32_el2, cpu)) { + value |= SCR_RW; /* RAO/WI*/ + } if (cpu_isar_feature(aa64_ras, cpu)) { valid_mask |= SCR_TERR; }