From patchwork Fri Jun 3 13:57:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 578824 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5141C3F2D4 for ; Fri, 3 Jun 2022 13:56:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243109AbiFCN4p (ORCPT ); Fri, 3 Jun 2022 09:56:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244889AbiFCN4m (ORCPT ); Fri, 3 Jun 2022 09:56:42 -0400 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F1DE381BB; Fri, 3 Jun 2022 06:56:40 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id n124-20020a1c2782000000b003972dfca96cso4378143wmn.4; Fri, 03 Jun 2022 06:56:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cx/gp/Zf/QVveVxqbkMsGI/KUlqkSV+vcSUZPyo3kCI=; b=qXerizvOA8TIf75essVIOe5kIDsQgJljHoxAdQ6GXgfCz02Nlq590sXYdsIuX3aj48 XEmkYXi33q3Q12V/x1MXN1v2I1om6nkk9ADN880tSaa+USVy4opnTfXO/lmRi06xgNFf W7y7mq+8gsRdLdoVn683ldRY2m+dPPM5/6mpOFQ3dsWaEl9LwtPx9TI3sBJiFcRw5/qU /C7clgzt64udQ9zsdX7RN1dWCkIPx6yFYTY8p6Plv61LXcgfJ2uW6pq3AG7xbsH7Td+V HDqlunMTxMkm1/rM2M2QOriZiFvOp3jW2S7UgN3o3+VsyZlNE4arvt8ORVVdgNdUEYf4 q4UA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cx/gp/Zf/QVveVxqbkMsGI/KUlqkSV+vcSUZPyo3kCI=; b=3fyUStSRFWy91LReTBUx+lDKQGG94hpUSUZJg6oREcAEn+N9IpAIBVdmm+RuMoNlAO 46zY5GK9m73NIV0O4JyrCtrWH+wPJYMHRsuaxAv9QbZdsipRiSFOQ4knGYyPzi8N/5FI gwmzWZXOtFGom0Gd/z+nm8p/C1JfCp5rfwKjDuUl8q+JWEMt3bhC8PQRsXoBSWdrzHyY 4AWMEuei30i67+VEtrYzt09thE9WHzFgSJxz9wu79xqzxEEl9DdyGo/RBjRAyMTYpfB0 5FGg25zgEwsASx6V39vyNjWhM7xQ51B8TUz7BzEDw8gpMVsqaIEE4c3ANMkuVkwJ9mbb v9mA== X-Gm-Message-State: AOAM533K832LwGzdEZtIMxPBJ/gS7hJF4hOWIEgtGTV5gZ0XmBM2uqSC BrZgGbadShYKxNdJQmcCQTg= X-Google-Smtp-Source: ABdhPJwEGnIUPcLW1uipz+weCaHwWbqgYbvBQB1MMtjgwcETbCj7tNXCCG1TdwRsKBlMGw8R5PfJ+g== X-Received: by 2002:a05:600c:1d20:b0:397:5a8b:a30a with SMTP id l32-20020a05600c1d2000b003975a8ba30amr8922975wms.89.1654264598832; Fri, 03 Jun 2022 06:56:38 -0700 (PDT) Received: from localhost (92.40.203.126.threembb.co.uk. [92.40.203.126]) by smtp.gmail.com with ESMTPSA id h11-20020a5d688b000000b0020e63ab5d78sm7334245wru.26.2022.06.03.06.56.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jun 2022 06:56:38 -0700 (PDT) From: Aidan MacDonald To: linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, wens@csie.org, jic23@kernel.org, lee.jones@linaro.org, sre@kernel.org, broonie@kernel.org, gregkh@linuxfoundation.org, lgirdwood@gmail.com Cc: lars@metafoo.de, rafael@kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/10] regmap-irq: Add get_irq_reg to support unusual register layouts Date: Fri, 3 Jun 2022 14:57:05 +0100 Message-Id: <20220603135714.12007-2-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220603135714.12007-1-aidanmacdonald.0x0@gmail.com> References: <20220603135714.12007-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add a new callback, get_irq_reg, for regmap IRQ chips, to support devices with unusual register layouts. This is required in the rare cases where the offset of an IRQ register is not constant with respect to the base register. This is probably best illustrated with an example: mask status IRQ0 0x40 0x44 IRQ1 0x41 0x45 IRQ2 0x42 0x46 IRQ3 0x43 0x47 IRQ4 0x4a 0x4d If we set mask_base = 0x40 and status_base = 0x44, the offsets of each register relative to the base are: mask status IRQ0 0 0 IRQ1 1 1 IRQ2 2 2 IRQ3 3 3 IRQ4 10 9 The existing mapping mechanisms can't include IRQ4 in the same irqchip as IRQ0-3 because the offset of IRQ4's register depends on which type of register we're asking for, ie. which base register is used. The get_irq_reg callback allows drivers to specify an arbitrary mapping of (base register, register index) pairs to register addresses, instead of the default linear mapping "base_register + register_index". This allows unusual layouts, like the one above, to be handled using a single regmap IRQ chip. The drawback is that when get_irq_reg is used, it's impossible to use bulk reads for status registers even if some of them are contiguous, because the mapping is opaque to regmap-irq. This should be acceptable for the case of a few infrequently-polled status registers. Signed-off-by: Aidan MacDonald --- drivers/base/regmap/regmap-irq.c | 19 +++++++++---------- include/linux/regmap.h | 5 +++++ 2 files changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c index 400c7412a7dc..e50437b18284 100644 --- a/drivers/base/regmap/regmap-irq.c +++ b/drivers/base/regmap/regmap-irq.c @@ -55,7 +55,9 @@ static int sub_irq_reg(struct regmap_irq_chip_data *data, unsigned int offset; int reg = 0; - if (!chip->sub_reg_offsets || !chip->not_fixed_stride) { + if (chip->get_irq_reg) { + reg = chip->get_irq_reg(base_reg, i); + } else if (!chip->sub_reg_offsets || !chip->not_fixed_stride) { /* Assume linear mapping */ reg = base_reg + (i * map->reg_stride * data->irq_reg_stride); } else { @@ -97,7 +99,6 @@ static void regmap_irq_sync_unlock(struct irq_data *data) struct regmap *map = d->map; int i, j, ret; u32 reg; - u32 unmask_offset; u32 val; if (d->chip->runtime_pm) { @@ -141,11 +142,11 @@ static void regmap_irq_sync_unlock(struct irq_data *data) dev_err(d->map->dev, "Failed to sync unmasks in %x\n", reg); - unmask_offset = d->chip->unmask_base - - d->chip->mask_base; + /* clear mask with unmask_base register */ + reg = sub_irq_reg(d, d->chip->unmask_base, i); ret = regmap_irq_update_bits(d, - reg + unmask_offset, + reg, d->mask_buf_def[i], d->mask_buf[i]); } else { @@ -480,7 +481,7 @@ static irqreturn_t regmap_irq_thread(int irq, void *d) } } else if (!map->use_single_read && map->reg_stride == 1 && - data->irq_reg_stride == 1) { + data->irq_reg_stride == 1 && !chip->get_irq_reg) { u8 *buf8 = data->status_reg_buf; u16 *buf16 = data->status_reg_buf; @@ -632,7 +633,6 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, int ret = -ENOMEM; int num_type_reg; u32 reg; - u32 unmask_offset; if (chip->num_regs <= 0) return -EINVAL; @@ -773,10 +773,9 @@ int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, ret = regmap_irq_update_bits(d, reg, d->mask_buf[i], ~d->mask_buf[i]); else if (d->chip->unmask_base) { - unmask_offset = d->chip->unmask_base - - d->chip->mask_base; + reg = sub_irq_reg(d, d->chip->unmask_base, i); ret = regmap_irq_update_bits(d, - reg + unmask_offset, + reg, d->mask_buf[i], d->mask_buf[i]); } else diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 8952fa3d0d59..4828021ab9e8 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -1495,6 +1495,10 @@ struct regmap_irq_sub_irq_map { * after handling the interrupts in regmap_irq_handler(). * @set_type_virt: Driver specific callback to extend regmap_irq_set_type() * and configure virt regs. + * @get_irq_reg: Callback to map a register index in range [0, num_regs[ + * to a register, relative to a specific base register. This + * is mainly useful for devices where the register offsets + * change depending on the base register. * @irq_drv_data: Driver specific IRQ data which is passed as parameter when * driver specific pre/post interrupt handler is called. * @@ -1545,6 +1549,7 @@ struct regmap_irq_chip { int (*handle_post_irq)(void *irq_drv_data); int (*set_type_virt)(unsigned int **buf, unsigned int type, unsigned long hwirq, int reg); + int (*get_irq_reg)(unsigned int base_reg, int i); void *irq_drv_data; }; From patchwork Fri Jun 3 13:57:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 578595 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BBCFFCCA47D for ; Fri, 3 Jun 2022 13:56:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244883AbiFCN4p (ORCPT ); Fri, 3 Jun 2022 09:56:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48688 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244891AbiFCN4n (ORCPT ); Fri, 3 Jun 2022 09:56:43 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DBEB2393F4; Fri, 3 Jun 2022 06:56:41 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id o29-20020a05600c511d00b00397697f172dso5080983wms.0; Fri, 03 Jun 2022 06:56:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JN5xhLwiBOldWzvgregOvN11Mr2QiqXZtW0+iAWNzDU=; b=M99BJuI3qILh6Lg0wKaIAW9efXlTmypyZJUDLQg5Vsgk4jgB2A8gOnv5vTIWeO3QtO G5AiCMZfQM3bJ3IOBB0JXrtDk4gcLHTrYuKedh0wOwW0HgFFyr0Fjy0djdxznKBc57/H wsuEktCi/Q3VWgAlx8P8oUsJicA8NNbn47nry032P1rRiyYnZWCWsTnF78wryq9Dp5WP kqcTIW5STPyHzK1dIPoYVD/QEhSx5Wl9UgtdS/tMghcwN8Q5pu6XInN/27uOAe9qV1ok t5gxqHFgWgojG/JDz5vPBiBQFmLn0kikjnbdXXr18+mzKrWfrovnGpOckTjD3rNpGNhq P/ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JN5xhLwiBOldWzvgregOvN11Mr2QiqXZtW0+iAWNzDU=; b=3kYi3qVSzsRtwz+fSGbGl58HgHvDLn+fjLCK7gvhuYM7OzNfzyTOIQUcrjJXDsXOeX ML2yu4PJuBmHrdIKH6jKwttzJ5F9nipss3fzo++xGfMr8IJW3UyYhsDDezqhIC15i1Ik 9/orkmzQkW6CGbcnfJ5hIzFfDbBXcKFeIxM3PZoOHs8IdDbtJyagALEOnSJIPtqWozn9 J0rv09ssw/ySP3GPBgnA0RB8Zn2O5yyQCLROJSfsmX2uwNwFYuIDN25w9NSFGse6uBlo 0Py3ebXD7ONJFwQEaJcynr7LYkXJ4m0Td7YR2DKlk0YnkAiAOf9gxPQZaNwFHBP24ex+ zLJg== X-Gm-Message-State: AOAM532fZJmZsUFoBiiTcIjObYdW8x5ITDFLaWaXRC2nBezUNOMXp1MY sITny91MpIDPUYenFbqMWN8= X-Google-Smtp-Source: ABdhPJzDNTjUPY+X2P0sqlRa/bRCrUxtmWpjrfKYF0/AkrnzCNnW+A2QMZr3TrFEBmf82EseSuM1JQ== X-Received: by 2002:a05:600c:1d2a:b0:39c:4215:7305 with SMTP id l42-20020a05600c1d2a00b0039c42157305mr1557747wms.136.1654264600536; Fri, 03 Jun 2022 06:56:40 -0700 (PDT) Received: from localhost (92.40.203.126.threembb.co.uk. [92.40.203.126]) by smtp.gmail.com with ESMTPSA id f12-20020a5d4dcc000000b002100316b126sm7618765wru.6.2022.06.03.06.56.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jun 2022 06:56:40 -0700 (PDT) From: Aidan MacDonald To: linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, wens@csie.org, jic23@kernel.org, lee.jones@linaro.org, sre@kernel.org, broonie@kernel.org, gregkh@linuxfoundation.org, lgirdwood@gmail.com Cc: lars@metafoo.de, rafael@kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/10] dt-bindings: mfd: add bindings for AXP192 MFD device Date: Fri, 3 Jun 2022 14:57:06 +0100 Message-Id: <20220603135714.12007-3-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220603135714.12007-1-aidanmacdonald.0x0@gmail.com> References: <20220603135714.12007-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The AXP192 is another X-Powers PMIC similar to the existing ones. Signed-off-by: Aidan MacDonald Acked-by: Rob Herring --- Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml b/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml index 3a53bae611bc..33c9b1b3cc04 100644 --- a/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml +++ b/Documentation/devicetree/bindings/mfd/x-powers,axp152.yaml @@ -84,6 +84,7 @@ properties: oneOf: - enum: - x-powers,axp152 + - x-powers,axp192 - x-powers,axp202 - x-powers,axp209 - x-powers,axp221 From patchwork Fri Jun 3 13:57:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 578594 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F27FAC43334 for ; Fri, 3 Jun 2022 13:56:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244903AbiFCN4q (ORCPT ); Fri, 3 Jun 2022 09:56:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48702 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244880AbiFCN4o (ORCPT ); Fri, 3 Jun 2022 09:56:44 -0400 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6731939821; Fri, 3 Jun 2022 06:56:43 -0700 (PDT) Received: by mail-wm1-x330.google.com with SMTP id z17so4142417wmf.1; Fri, 03 Jun 2022 06:56:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=I3/ArNj3Gx6ysweu6QmWCkRaXZNp/b8pZqhl3nfQBWw=; b=ZVsQkdWZwki7857RR0N7O8162fv72qfm+dNqCFCFfzBjAeracnkR3fl6ejkCmmikaG JLW0xmoFyX0dds5TZt0BkWXSsoH3gXUqJuSwVcJQ75aO1xVP17MErHY0hNrKmpaRCYMc dROl2/1Yw1XLLCEvZ3wSTS2WxgtxNspljGSOmPIAE84ahPukfNsym/pRIOfd6ynt+2ME xWMsNG3dhZ3sI0iVN0xpeDUivu1BVsuffwDSo8MkP3QPGBcOEqGLnqu++SPM0XDQypVr HPmEJrZNhtrZakZyj65/NnkI3Xtgj6HKfuFbSFcgce2BV18muIsqyRv1MxUVnM3aA/NH ZKhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=I3/ArNj3Gx6ysweu6QmWCkRaXZNp/b8pZqhl3nfQBWw=; b=SlhuY4DtW+I2cYEUD3XD20nPNQBZTrCO5K6Z+80BTdeGzZCByHN9y97P8p3dI7Lr8i 0McXwb07kXL21VpML3XMpHybjyZM9T82Zt2qxsoAO5snTGyE/1Yv91TqW3Q5Sj7eXE+C dDBg5925Co2jodpUuK/EZg8t3GCVBlU8hmiZjxqXaGBXpl00i/lFzj/9w093y3PtSrKL Z3IjqFZA3s+uqAM3txywHq+Trn/kZW5kR5H6N4n3OTPwrqSVGgtrx4ymfm/gtONeYcZ6 nyM6FEOTc5bHZZHU17DnKViA3AaYTWgCh7YaV3YsDJcE3NqV7d9sqhFnE2g0nzBmQaKR w9yA== X-Gm-Message-State: AOAM5314bMKawy8GZrhTrBpg0flgBbIGYgl8WnpjzRWY6ApTM2pN8Cq5 4c1SmIDjAndFa7kG0CjuMaE= X-Google-Smtp-Source: ABdhPJymrL5pMssSod52/digpr5OcG2Is93Lvg1T53T3bk0ng83WgaxLscbYytTDi8SHmV0gTydOSA== X-Received: by 2002:a1c:f604:0:b0:399:c7a6:44c1 with SMTP id w4-20020a1cf604000000b00399c7a644c1mr9018967wmc.54.1654264602021; Fri, 03 Jun 2022 06:56:42 -0700 (PDT) Received: from localhost (92.40.203.126.threembb.co.uk. [92.40.203.126]) by smtp.gmail.com with ESMTPSA id l13-20020a5d560d000000b0020fe35aec4bsm7606516wrv.70.2022.06.03.06.56.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jun 2022 06:56:41 -0700 (PDT) From: Aidan MacDonald To: linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, wens@csie.org, jic23@kernel.org, lee.jones@linaro.org, sre@kernel.org, broonie@kernel.org, gregkh@linuxfoundation.org, lgirdwood@gmail.com Cc: lars@metafoo.de, rafael@kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/10] dt-bindings: iio: adc: axp209: Add AXP192 compatible Date: Fri, 3 Jun 2022 14:57:07 +0100 Message-Id: <20220603135714.12007-4-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220603135714.12007-1-aidanmacdonald.0x0@gmail.com> References: <20220603135714.12007-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The AXP192 is identical to the AXP20x, except for two additional GPIO ADC channels. Signed-off-by: Aidan MacDonald Acked-by: Rob Herring --- .../bindings/iio/adc/x-powers,axp209-adc.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml b/Documentation/devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml index d6d3d8590171..1a68e650ac7d 100644 --- a/Documentation/devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml @@ -14,6 +14,23 @@ description: | Device is a child of an axp209 multifunction device ADC channels and their indexes per variant: + AXP192 + ------ + 0 | acin_v + 1 | acin_i + 2 | vbus_v + 3 | vbus_i + 4 | pmic_temp + 5 | gpio0_v + 6 | gpio1_v + 7 | gpio2_v + 8 | gpio3_v + 9 | ipsout_v + 10 | batt_v + 11 | batt_chrg_i + 12 | batt_dischrg_i + 13 | ts_v + AXP209 ------ 0 | acin_v @@ -50,6 +67,7 @@ description: | properties: compatible: oneOf: + - const: x-powers,axp192-adc - const: x-powers,axp209-adc - const: x-powers,axp221-adc - const: x-powers,axp813-adc From patchwork Fri Jun 3 13:57:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 578823 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B14F3C433EF for ; Fri, 3 Jun 2022 13:56:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244911AbiFCN4t (ORCPT ); Fri, 3 Jun 2022 09:56:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244899AbiFCN4q (ORCPT ); Fri, 3 Jun 2022 09:56:46 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F01E381BB; Fri, 3 Jun 2022 06:56:45 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id q7so10517515wrg.5; Fri, 03 Jun 2022 06:56:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wzgvlhk4U9BqT2nWRr42a6fdV0TBkWb1ZUnx7kKgOIY=; b=pOeBBazR97DypyM6LTiK8U40Ar4dflOf6Q9S9ZXiC4YFHvmeZ3EfCTlEmFNfiTkdgM 0ezllszEUWwdkzSnfk/+WREnKppZPMhm5y60JvruIX9q0L46SnKE16/KWjzCfoKcOnqP Y7kA+q9E040mvz2ScWokPTlA0Pb4C/hgm5nGOYB1tTW4IrfbDlrZthcVenITfslN4Byj C0SMRkdkB+zz2lXiIJLs673qcL7oTZv9FiiLlDqmwBSVTsG4/BdV81oSYiCypaU6RqUR cDTbdjLeShPuDm5EWdq1sxQA5XHxZF3J+tIGs9xESP0+Idp3wrFlsKo8LJLTys2n6SRU TavA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wzgvlhk4U9BqT2nWRr42a6fdV0TBkWb1ZUnx7kKgOIY=; b=mVPSzVJhQRhLy7aF5j725QeZAoJUEmKQAOL6zROzEFRY08lrv4Vp/lzWw2rMN+YcYb aWl2/IItlCfdqYl69pItgX/8aIEHtX/ZxOCS7KG2gA87RJY+QtJSRY0DS0hKyTpvf4R9 lesiksFGzikJznwQOyMeG6I1H2QLFPkDdZWvTxB/6EkpGpadYDC38ogqYZPXtm2vXZ0R oHiqlX2AVxKs34VM/MzMnDJplBsoVX/Z8hcv1F/v1bXKWOLQFZvSGJplkLg6hPD3ls25 BxRblK4E13DQ//emt+o+lydcV/9fXjzcMsKuI7gQiJRLGtiGghFrn6ntW+zCPe17ZvrV eFMw== X-Gm-Message-State: AOAM530GdJDLQy/q0KDvM61HbCKn9Q8FAvyVqoj/CrYXjA6M/cAceoB3 yEWnsiN0dghTYgTZeLKY5CM= X-Google-Smtp-Source: ABdhPJxWk27J7hnrwlpGkUoyXJSu5Gy7XQue8d6i2hkYd4tc9wmtAPWITUWiUyH9svhg3F5vANmfKw== X-Received: by 2002:adf:e8cd:0:b0:210:2b10:ab22 with SMTP id k13-20020adfe8cd000000b002102b10ab22mr8138830wrn.476.1654264603682; Fri, 03 Jun 2022 06:56:43 -0700 (PDT) Received: from localhost (92.40.203.126.threembb.co.uk. [92.40.203.126]) by smtp.gmail.com with ESMTPSA id be5-20020a05600c1e8500b003942a244ee6sm9041515wmb.43.2022.06.03.06.56.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jun 2022 06:56:43 -0700 (PDT) From: Aidan MacDonald To: linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, wens@csie.org, jic23@kernel.org, lee.jones@linaro.org, sre@kernel.org, broonie@kernel.org, gregkh@linuxfoundation.org, lgirdwood@gmail.com Cc: lars@metafoo.de, rafael@kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/10] dt-bindings: power: supply: axp20x: Add AXP192 compatible Date: Fri, 3 Jun 2022 14:57:08 +0100 Message-Id: <20220603135714.12007-5-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220603135714.12007-1-aidanmacdonald.0x0@gmail.com> References: <20220603135714.12007-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The AXP192's USB power supply is similar to the AXP202 but it has different USB current limits. Signed-off-by: Aidan MacDonald Acked-by: Rob Herring --- .../bindings/power/supply/x-powers,axp20x-usb-power-supply.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/supply/x-powers,axp20x-usb-power-supply.yaml b/Documentation/devicetree/bindings/power/supply/x-powers,axp20x-usb-power-supply.yaml index 0c371b55c9e1..e800b3b97f0d 100644 --- a/Documentation/devicetree/bindings/power/supply/x-powers,axp20x-usb-power-supply.yaml +++ b/Documentation/devicetree/bindings/power/supply/x-powers,axp20x-usb-power-supply.yaml @@ -22,6 +22,7 @@ properties: compatible: oneOf: - enum: + - x-powers,axp192-usb-power-supply - x-powers,axp202-usb-power-supply - x-powers,axp221-usb-power-supply - x-powers,axp223-usb-power-supply From patchwork Fri Jun 3 13:57:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 578593 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1202CCA47E for ; Fri, 3 Jun 2022 13:57:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244921AbiFCN5G (ORCPT ); Fri, 3 Jun 2022 09:57:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48930 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244915AbiFCN5A (ORCPT ); Fri, 3 Jun 2022 09:57:00 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C11971E0; Fri, 3 Jun 2022 06:56:46 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id p10so10500641wrg.12; Fri, 03 Jun 2022 06:56:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kgON9aED3Gy7Z9BeMM0BVK1opvH/pPoHogRzCESmP4k=; b=lJSK31jZz67cqgJQwIdAG8zb/6R45WFBk4YCPKv2LGif+gquIcDj6UeFHE09crKJYB bheiVblG7niOyyVjb/xVZbEUNP8V24fnh3MDps53nT6vJwjZ6G59ZZxz+EciSVgovpw8 UyJnwqbeOzcVOyWyVRLBWptps+lar5dXefrsTgArqvCoZeff5XFtlsfZ5QX0/M1nq8IO dY/C9uUKzu5pVUfkoNjjggtDG9c91cLFsnzUFbDgDZEoMOaxYllFIRw8cOqEjJOteN7p SPOHxa3M/xiU4uSLDSjMg3EX40BXgeTkagxCPpGiCsrmlqsIxfPkMyQzZWGuLYlURICw iSLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kgON9aED3Gy7Z9BeMM0BVK1opvH/pPoHogRzCESmP4k=; b=LyJe/M1TEk07QL3X9epn0PQWHZHm1hjCOprShocUCe1Whtnj2Gmy5KVt4LnEFISxlX U+miZb84pPDjQuJMTTaffRz17JyxCg16T7pkJFrbKXqcVX4c0IAN+Ncog+S/xJK+oI21 lF/cuWYevuDhCENAH4n+eAWhyu7J+s11jAdOqAMF3rEVt75ZbGdw62CGjroE54BqRgrs krMKjl8GZumH8FCqlb17qbRWqm3gB1C1CqEALa/Rq77nsIetxIw+8xRjeHsy4028yLiP Ig2bVV9ERAzTeqpHRi566z4+V/oYrCRzfSBDAxLsw9FUaBQOrL6Ulqx/dIvGJBExbSwp c8cA== X-Gm-Message-State: AOAM530WB0YsUVdKVvubKxWqcvxJSWuNoy2B/XkFbKaeBhrTn1kSSA7W UxgxRXo2poxvuasNGMBNOAw= X-Google-Smtp-Source: ABdhPJzCj58zHMX2wl+BEPG23yCwqpfPUMlsxAE2402WtIxoMq6Sr6hkyecZ972h4OyVJkPcIWfzaA== X-Received: by 2002:adf:f610:0:b0:213:b4e1:7276 with SMTP id t16-20020adff610000000b00213b4e17276mr5488075wrp.712.1654264605312; Fri, 03 Jun 2022 06:56:45 -0700 (PDT) Received: from localhost (92.40.203.126.threembb.co.uk. [92.40.203.126]) by smtp.gmail.com with ESMTPSA id n7-20020a05600c3b8700b0039456fb80b3sm13944284wms.43.2022.06.03.06.56.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jun 2022 06:56:44 -0700 (PDT) From: Aidan MacDonald To: linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, wens@csie.org, jic23@kernel.org, lee.jones@linaro.org, sre@kernel.org, broonie@kernel.org, gregkh@linuxfoundation.org, lgirdwood@gmail.com Cc: lars@metafoo.de, rafael@kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 05/10] dt-bindings: gpio: Add AXP192 GPIO bindings Date: Fri, 3 Jun 2022 14:57:09 +0100 Message-Id: <20220603135714.12007-6-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220603135714.12007-1-aidanmacdonald.0x0@gmail.com> References: <20220603135714.12007-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The AXP192 PMIC is different enough from the PMICs supported by the AXP20x GPIO driver to warrant a separate driver. The AXP192 driver also supports interrupts and pinconf settings. Signed-off-by: Aidan MacDonald --- .../bindings/gpio/x-powers,axp192-gpio.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/x-powers,axp192-gpio.yaml diff --git a/Documentation/devicetree/bindings/gpio/x-powers,axp192-gpio.yaml b/Documentation/devicetree/bindings/gpio/x-powers,axp192-gpio.yaml new file mode 100644 index 000000000000..7a985640ade8 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/x-powers,axp192-gpio.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/gpio/x-powers,axp192-gpio.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: X-Powers AXP192 GPIO Device Tree Bindings + +maintainers: + - Chen-Yu Tsai + +properties: + "#gpio-cells": + const: 2 + description: > + The first cell is the pin number and the second is the GPIO flags. + + compatible: + oneOf: + - enum: + - x-powers,axp192-gpio + + gpio-controller: true + +patternProperties: + "^.*-pins?$": + $ref: /schemas/pinctrl/pinmux-node.yaml# + + properties: + pins: + items: + enum: + - GPIO0 + - GPIO1 + - GPIO2 + - GPIO3 + - GPIO4 + - N_RSTO + + function: + enum: + - output + - input + - ldo + - pwm + - adc + - low_output + - floating + - ext_chg_ctl + - ldo_status + +required: + - compatible + - "#gpio-cells" + - gpio-controller + +additionalProperties: false + +... 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[92.40.203.126]) by smtp.gmail.com with ESMTPSA id l10-20020a5d410a000000b0020fc6590a12sm7185468wrp.41.2022.06.03.06.56.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jun 2022 06:56:46 -0700 (PDT) From: Aidan MacDonald To: linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, wens@csie.org, jic23@kernel.org, lee.jones@linaro.org, sre@kernel.org, broonie@kernel.org, gregkh@linuxfoundation.org, lgirdwood@gmail.com Cc: lars@metafoo.de, rafael@kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/10] mfd: axp20x: Add support for AXP192 Date: Fri, 3 Jun 2022 14:57:10 +0100 Message-Id: <20220603135714.12007-7-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220603135714.12007-1-aidanmacdonald.0x0@gmail.com> References: <20220603135714.12007-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The AXP192 PMIC is similar to the AXP202/AXP209, but with different regulators, additional GPIOs, and a different IRQ register layout. Signed-off-by: Aidan MacDonald --- drivers/mfd/axp20x-i2c.c | 2 + drivers/mfd/axp20x.c | 150 +++++++++++++++++++++++++++++++++++++ include/linux/mfd/axp20x.h | 84 +++++++++++++++++++++ 3 files changed, 236 insertions(+) diff --git a/drivers/mfd/axp20x-i2c.c b/drivers/mfd/axp20x-i2c.c index 00ab48018d8d..9ada58fad77f 100644 --- a/drivers/mfd/axp20x-i2c.c +++ b/drivers/mfd/axp20x-i2c.c @@ -62,6 +62,7 @@ static int axp20x_i2c_remove(struct i2c_client *i2c) #ifdef CONFIG_OF static const struct of_device_id axp20x_i2c_of_match[] = { { .compatible = "x-powers,axp152", .data = (void *)AXP152_ID }, + { .compatible = "x-powers,axp192", .data = (void *)AXP192_ID }, { .compatible = "x-powers,axp202", .data = (void *)AXP202_ID }, { .compatible = "x-powers,axp209", .data = (void *)AXP209_ID }, { .compatible = "x-powers,axp221", .data = (void *)AXP221_ID }, @@ -75,6 +76,7 @@ MODULE_DEVICE_TABLE(of, axp20x_i2c_of_match); static const struct i2c_device_id axp20x_i2c_id[] = { { "axp152", 0 }, + { "axp192", 0 }, { "axp202", 0 }, { "axp209", 0 }, { "axp221", 0 }, diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c index 8161a5dc68e8..7f64e5c83fe2 100644 --- a/drivers/mfd/axp20x.c +++ b/drivers/mfd/axp20x.c @@ -34,6 +34,7 @@ static const char * const axp20x_model_names[] = { "AXP152", + "AXP192", "AXP202", "AXP209", "AXP221", @@ -92,6 +93,35 @@ static const struct regmap_access_table axp20x_volatile_table = { .n_yes_ranges = ARRAY_SIZE(axp20x_volatile_ranges), }; +static const struct regmap_range axp192_writeable_ranges[] = { + regmap_reg_range(AXP192_DATACACHE(0), AXP192_DATACACHE(5)), + regmap_reg_range(AXP192_PWR_OUT_CTRL, AXP192_IRQ5_STATE), + regmap_reg_range(AXP20X_DCDC_MODE, AXP192_N_RSTO_CTRL), + regmap_reg_range(AXP20X_CC_CTRL, AXP20X_CC_CTRL), +}; + +static const struct regmap_range axp192_volatile_ranges[] = { + regmap_reg_range(AXP20X_PWR_INPUT_STATUS, AXP192_USB_OTG_STATUS), + regmap_reg_range(AXP192_IRQ1_STATE, AXP192_IRQ4_STATE), + regmap_reg_range(AXP192_IRQ5_STATE, AXP192_IRQ5_STATE), + regmap_reg_range(AXP20X_ACIN_V_ADC_H, AXP20X_IPSOUT_V_HIGH_L), + regmap_reg_range(AXP20X_TIMER_CTRL, AXP20X_TIMER_CTRL), + regmap_reg_range(AXP192_GPIO2_0_STATE, AXP192_GPIO2_0_STATE), + regmap_reg_range(AXP192_GPIO4_3_STATE, AXP192_GPIO4_3_STATE), + regmap_reg_range(AXP192_N_RSTO_CTRL, AXP192_N_RSTO_CTRL), + regmap_reg_range(AXP20X_CHRG_CC_31_24, AXP20X_CC_CTRL), +}; + +static const struct regmap_access_table axp192_writeable_table = { + .yes_ranges = axp192_writeable_ranges, + .n_yes_ranges = ARRAY_SIZE(axp192_writeable_ranges), +}; + +static const struct regmap_access_table axp192_volatile_table = { + .yes_ranges = axp192_volatile_ranges, + .n_yes_ranges = ARRAY_SIZE(axp192_volatile_ranges), +}; + /* AXP22x ranges are shared with the AXP809, as they cover the same range */ static const struct regmap_range axp22x_writeable_ranges[] = { regmap_reg_range(AXP20X_DATACACHE(0), AXP20X_IRQ5_STATE), @@ -173,6 +203,25 @@ static const struct resource axp152_pek_resources[] = { DEFINE_RES_IRQ_NAMED(AXP152_IRQ_PEK_FAL_EDGE, "PEK_DBF"), }; +static const struct resource axp192_gpio_resources[] = { + DEFINE_RES_IRQ_NAMED(AXP192_IRQ_GPIO0_INPUT, "GPIO0"), + DEFINE_RES_IRQ_NAMED(AXP192_IRQ_GPIO1_INPUT, "GPIO1"), + DEFINE_RES_IRQ_NAMED(AXP192_IRQ_GPIO2_INPUT, "GPIO2"), +}; + +static const struct resource axp192_ac_power_supply_resources[] = { + DEFINE_RES_IRQ_NAMED(AXP192_IRQ_ACIN_PLUGIN, "ACIN_PLUGIN"), + DEFINE_RES_IRQ_NAMED(AXP192_IRQ_ACIN_REMOVAL, "ACIN_REMOVAL"), + DEFINE_RES_IRQ_NAMED(AXP192_IRQ_ACIN_OVER_V, "ACIN_OVER_V"), +}; + +static const struct resource axp192_usb_power_supply_resources[] = { + DEFINE_RES_IRQ_NAMED(AXP192_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"), + DEFINE_RES_IRQ_NAMED(AXP192_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"), + DEFINE_RES_IRQ_NAMED(AXP192_IRQ_VBUS_VALID, "VBUS_VALID"), + DEFINE_RES_IRQ_NAMED(AXP192_IRQ_VBUS_NOT_VALID, "VBUS_NOT_VALID"), +}; + static const struct resource axp20x_ac_power_supply_resources[] = { DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_PLUGIN, "ACIN_PLUGIN"), DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_REMOVAL, "ACIN_REMOVAL"), @@ -245,6 +294,15 @@ static const struct regmap_config axp152_regmap_config = { .cache_type = REGCACHE_RBTREE, }; +static const struct regmap_config axp192_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .wr_table = &axp192_writeable_table, + .volatile_table = &axp192_volatile_table, + .max_register = AXP20X_CC_CTRL, + .cache_type = REGCACHE_RBTREE, +}; + static const struct regmap_config axp20x_regmap_config = { .reg_bits = 8, .val_bits = 8, @@ -304,6 +362,55 @@ static const struct regmap_irq axp152_regmap_irqs[] = { INIT_REGMAP_IRQ(AXP152, GPIO0_INPUT, 2, 0), }; +static const struct regmap_irq axp192_regmap_irqs[] = { + INIT_REGMAP_IRQ(AXP192, ACIN_OVER_V, 0, 7), + INIT_REGMAP_IRQ(AXP192, ACIN_PLUGIN, 0, 6), + INIT_REGMAP_IRQ(AXP192, ACIN_REMOVAL, 0, 5), + INIT_REGMAP_IRQ(AXP192, VBUS_OVER_V, 0, 4), + INIT_REGMAP_IRQ(AXP192, VBUS_PLUGIN, 0, 3), + INIT_REGMAP_IRQ(AXP192, VBUS_REMOVAL, 0, 2), + INIT_REGMAP_IRQ(AXP192, VBUS_V_LOW, 0, 1), + INIT_REGMAP_IRQ(AXP192, BATT_PLUGIN, 1, 7), + INIT_REGMAP_IRQ(AXP192, BATT_REMOVAL, 1, 6), + INIT_REGMAP_IRQ(AXP192, BATT_ENT_ACT_MODE, 1, 5), + INIT_REGMAP_IRQ(AXP192, BATT_EXIT_ACT_MODE, 1, 4), + INIT_REGMAP_IRQ(AXP192, CHARG, 1, 3), + INIT_REGMAP_IRQ(AXP192, CHARG_DONE, 1, 2), + INIT_REGMAP_IRQ(AXP192, BATT_TEMP_HIGH, 1, 1), + INIT_REGMAP_IRQ(AXP192, BATT_TEMP_LOW, 1, 0), + INIT_REGMAP_IRQ(AXP192, DIE_TEMP_HIGH, 2, 7), + INIT_REGMAP_IRQ(AXP192, CHARG_I_LOW, 2, 6), + INIT_REGMAP_IRQ(AXP192, DCDC1_V_LONG, 2, 5), + INIT_REGMAP_IRQ(AXP192, DCDC2_V_LONG, 2, 4), + INIT_REGMAP_IRQ(AXP192, DCDC3_V_LONG, 2, 3), + INIT_REGMAP_IRQ(AXP192, PEK_SHORT, 2, 1), + INIT_REGMAP_IRQ(AXP192, PEK_LONG, 2, 0), + INIT_REGMAP_IRQ(AXP192, N_OE_PWR_ON, 3, 7), + INIT_REGMAP_IRQ(AXP192, N_OE_PWR_OFF, 3, 6), + INIT_REGMAP_IRQ(AXP192, VBUS_VALID, 3, 5), + INIT_REGMAP_IRQ(AXP192, VBUS_NOT_VALID, 3, 4), + INIT_REGMAP_IRQ(AXP192, VBUS_SESS_VALID, 3, 3), + INIT_REGMAP_IRQ(AXP192, VBUS_SESS_END, 3, 2), + INIT_REGMAP_IRQ(AXP192, LOW_PWR_LVL, 3, 0), + INIT_REGMAP_IRQ(AXP192, TIMER, 4, 7), + INIT_REGMAP_IRQ(AXP192, GPIO2_INPUT, 4, 2), + INIT_REGMAP_IRQ(AXP192, GPIO1_INPUT, 4, 1), + INIT_REGMAP_IRQ(AXP192, GPIO0_INPUT, 4, 0), +}; + +static int axp192_get_irq_reg(unsigned int base_reg, int i) +{ + /* linear mapping for IRQ1 to IRQ4 */ + if (i < 4) + return base_reg + i; + + /* handle IRQ5 separately */ + if (base_reg == AXP192_IRQ1_EN) + return AXP192_IRQ5_EN; + else + return AXP192_IRQ5_STATE; +} + static const struct regmap_irq axp20x_regmap_irqs[] = { INIT_REGMAP_IRQ(AXP20X, ACIN_OVER_V, 0, 7), INIT_REGMAP_IRQ(AXP20X, ACIN_PLUGIN, 0, 6), @@ -514,6 +621,19 @@ static const struct regmap_irq_chip axp152_regmap_irq_chip = { .num_regs = 3, }; +static const struct regmap_irq_chip axp192_regmap_irq_chip = { + .name = "axp192_irq_chip", + .status_base = AXP192_IRQ1_STATE, + .ack_base = AXP192_IRQ1_STATE, + .mask_base = AXP192_IRQ1_EN, + .mask_invert = true, + .init_ack_masked = true, + .irqs = axp192_regmap_irqs, + .num_irqs = ARRAY_SIZE(axp192_regmap_irqs), + .num_regs = 5, + .get_irq_reg = axp192_get_irq_reg, +}; + static const struct regmap_irq_chip axp20x_regmap_irq_chip = { .name = "axp20x_irq_chip", .status_base = AXP20X_IRQ1_STATE, @@ -588,6 +708,30 @@ static const struct regmap_irq_chip axp809_regmap_irq_chip = { .num_regs = 5, }; +static const struct mfd_cell axp192_cells[] = { + { + .name = "axp192-gpio", + .of_compatible = "x-powers,axp192-gpio", + .num_resources = ARRAY_SIZE(axp192_gpio_resources), + .resources = axp192_gpio_resources, + }, { + .name = "axp20x-regulator", + }, { + .name = "axp192-adc", + .of_compatible = "x-powers,axp192-adc", + }, { + .name = "axp20x-ac-power-supply", + .of_compatible = "x-powers,axp202-ac-power-supply", + .num_resources = ARRAY_SIZE(axp192_ac_power_supply_resources), + .resources = axp192_ac_power_supply_resources, + }, { + .name = "axp20x-usb-power-supply", + .of_compatible = "x-powers,axp192-usb-power-supply", + .num_resources = ARRAY_SIZE(axp192_usb_power_supply_resources), + .resources = axp192_usb_power_supply_resources, + } +}; + static const struct mfd_cell axp20x_cells[] = { { .name = "axp20x-gpio", @@ -865,6 +1009,12 @@ int axp20x_match_device(struct axp20x_dev *axp20x) axp20x->regmap_cfg = &axp152_regmap_config; axp20x->regmap_irq_chip = &axp152_regmap_irq_chip; break; + case AXP192_ID: + axp20x->nr_cells = ARRAY_SIZE(axp192_cells); + axp20x->cells = axp192_cells; + axp20x->regmap_cfg = &axp192_regmap_config; + axp20x->regmap_irq_chip = &axp192_regmap_irq_chip; + break; case AXP202_ID: case AXP209_ID: axp20x->nr_cells = ARRAY_SIZE(axp20x_cells); diff --git a/include/linux/mfd/axp20x.h b/include/linux/mfd/axp20x.h index 9ab0e2fca7ea..18546e124919 100644 --- a/include/linux/mfd/axp20x.h +++ b/include/linux/mfd/axp20x.h @@ -12,6 +12,7 @@ enum axp20x_variants { AXP152_ID = 0, + AXP192_ID, AXP202_ID, AXP209_ID, AXP221_ID, @@ -24,6 +25,7 @@ enum axp20x_variants { NR_AXP20X_VARIANTS, }; +#define AXP192_DATACACHE(m) (0x06 + (m)) #define AXP20X_DATACACHE(m) (0x04 + (m)) /* Power supply */ @@ -45,6 +47,13 @@ enum axp20x_variants { #define AXP152_DCDC_FREQ 0x37 #define AXP152_DCDC_MODE 0x80 +#define AXP192_USB_OTG_STATUS 0x04 +#define AXP192_PWR_OUT_CTRL 0x12 +#define AXP192_DCDC2_V_OUT 0x23 +#define AXP192_DCDC1_V_OUT 0x26 +#define AXP192_DCDC3_V_OUT 0x27 +#define AXP192_LDO2_3_V_OUT 0x28 + #define AXP20X_PWR_INPUT_STATUS 0x00 #define AXP20X_PWR_OP_MODE 0x01 #define AXP20X_USB_OTG_STATUS 0x02 @@ -139,6 +148,17 @@ enum axp20x_variants { #define AXP152_IRQ2_STATE 0x49 #define AXP152_IRQ3_STATE 0x4a +#define AXP192_IRQ1_EN 0x40 +#define AXP192_IRQ2_EN 0x41 +#define AXP192_IRQ3_EN 0x42 +#define AXP192_IRQ4_EN 0x43 +#define AXP192_IRQ1_STATE 0x44 +#define AXP192_IRQ2_STATE 0x45 +#define AXP192_IRQ3_STATE 0x46 +#define AXP192_IRQ4_STATE 0x47 +#define AXP192_IRQ5_EN 0x4a +#define AXP192_IRQ5_STATE 0x4d + #define AXP20X_IRQ1_EN 0x40 #define AXP20X_IRQ2_EN 0x41 #define AXP20X_IRQ3_EN 0x42 @@ -153,6 +173,11 @@ enum axp20x_variants { #define AXP20X_IRQ6_STATE 0x4d /* ADC */ +#define AXP192_GPIO2_V_ADC_H 0x68 +#define AXP192_GPIO2_V_ADC_L 0x69 +#define AXP192_GPIO3_V_ADC_H 0x6a +#define AXP192_GPIO3_V_ADC_L 0x6b + #define AXP20X_ACIN_V_ADC_H 0x56 #define AXP20X_ACIN_V_ADC_L 0x57 #define AXP20X_ACIN_I_ADC_H 0x58 @@ -182,6 +207,8 @@ enum axp20x_variants { #define AXP20X_IPSOUT_V_HIGH_L 0x7f /* Power supply */ +#define AXP192_GPIO30_IN_RANGE 0x85 + #define AXP20X_DCDC_MODE 0x80 #define AXP20X_ADC_EN1 0x82 #define AXP20X_ADC_EN2 0x83 @@ -210,6 +237,16 @@ enum axp20x_variants { #define AXP152_PWM1_FREQ_Y 0x9c #define AXP152_PWM1_DUTY_CYCLE 0x9d +#define AXP192_GPIO0_CTRL 0x90 +#define AXP192_LDO_IO0_V_OUT 0x91 +#define AXP192_GPIO1_CTRL 0x92 +#define AXP192_GPIO2_CTRL 0x93 +#define AXP192_GPIO2_0_STATE 0x94 +#define AXP192_GPIO4_3_CTRL 0x95 +#define AXP192_GPIO4_3_STATE 0x96 +#define AXP192_GPIO2_0_PULL 0x97 +#define AXP192_N_RSTO_CTRL 0x9e + #define AXP20X_GPIO0_CTRL 0x90 #define AXP20X_LDO5_V_OUT 0x91 #define AXP20X_GPIO1_CTRL 0x92 @@ -287,6 +324,17 @@ enum axp20x_variants { #define AXP288_FG_TUNE5 0xed /* Regulators IDs */ +enum { + AXP192_DCDC1 = 0, + AXP192_DCDC2, + AXP192_DCDC3, + AXP192_LDO1, + AXP192_LDO2, + AXP192_LDO3, + AXP192_LDO_IO0, + AXP192_REG_ID_MAX, +}; + enum { AXP20X_LDO1 = 0, AXP20X_LDO2, @@ -440,6 +488,42 @@ enum { AXP152_IRQ_GPIO0_INPUT, }; +enum axp192_irqs { + AXP192_IRQ_ACIN_OVER_V = 1, + AXP192_IRQ_ACIN_PLUGIN, + AXP192_IRQ_ACIN_REMOVAL, + AXP192_IRQ_VBUS_OVER_V, + AXP192_IRQ_VBUS_PLUGIN, + AXP192_IRQ_VBUS_REMOVAL, + AXP192_IRQ_VBUS_V_LOW, + AXP192_IRQ_BATT_PLUGIN, + AXP192_IRQ_BATT_REMOVAL, + AXP192_IRQ_BATT_ENT_ACT_MODE, + AXP192_IRQ_BATT_EXIT_ACT_MODE, + AXP192_IRQ_CHARG, + AXP192_IRQ_CHARG_DONE, + AXP192_IRQ_BATT_TEMP_HIGH, + AXP192_IRQ_BATT_TEMP_LOW, + AXP192_IRQ_DIE_TEMP_HIGH, + AXP192_IRQ_CHARG_I_LOW, + AXP192_IRQ_DCDC1_V_LONG, + AXP192_IRQ_DCDC2_V_LONG, + AXP192_IRQ_DCDC3_V_LONG, + AXP192_IRQ_PEK_SHORT = 22, + AXP192_IRQ_PEK_LONG, + AXP192_IRQ_N_OE_PWR_ON, + AXP192_IRQ_N_OE_PWR_OFF, + AXP192_IRQ_VBUS_VALID, + AXP192_IRQ_VBUS_NOT_VALID, + AXP192_IRQ_VBUS_SESS_VALID, + AXP192_IRQ_VBUS_SESS_END, + AXP192_IRQ_LOW_PWR_LVL = 31, + AXP192_IRQ_TIMER, + AXP192_IRQ_GPIO2_INPUT = 37, + AXP192_IRQ_GPIO1_INPUT, + AXP192_IRQ_GPIO0_INPUT, +}; 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[92.40.203.126]) by smtp.gmail.com with ESMTPSA id u14-20020a056000038e00b00213b54d8894sm1475437wrf.17.2022.06.03.06.56.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jun 2022 06:56:48 -0700 (PDT) From: Aidan MacDonald To: linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, wens@csie.org, jic23@kernel.org, lee.jones@linaro.org, sre@kernel.org, broonie@kernel.org, gregkh@linuxfoundation.org, lgirdwood@gmail.com Cc: lars@metafoo.de, rafael@kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/10] regulator: axp20x: Add support for AXP192 Date: Fri, 3 Jun 2022 14:57:11 +0100 Message-Id: <20220603135714.12007-8-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220603135714.12007-1-aidanmacdonald.0x0@gmail.com> References: <20220603135714.12007-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add support for the AXP192 PMIC. Signed-off-by: Aidan MacDonald Acked-by: Mark Brown --- drivers/regulator/axp20x-regulator.c | 101 ++++++++++++++++++++++++--- 1 file changed, 92 insertions(+), 9 deletions(-) diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c index d260c442b788..1edf2bbf1c16 100644 --- a/drivers/regulator/axp20x-regulator.c +++ b/drivers/regulator/axp20x-regulator.c @@ -27,6 +27,29 @@ #include #include +#define AXP192_GPIO0_FUNC_MASK GENMASK(2, 0) + +#define AXP192_IO_ENABLED 0x02 +#define AXP192_IO_DISABLED 0x06 + +#define AXP192_WORKMODE_DCDC1_MASK BIT_MASK(3) +#define AXP192_WORKMODE_DCDC2_MASK BIT_MASK(2) +#define AXP192_WORKMODE_DCDC3_MASK BIT_MASK(1) + +#define AXP192_DCDC1_V_OUT_MASK GENMASK(6, 0) +#define AXP192_DCDC2_V_OUT_MASK GENMASK(5, 0) +#define AXP192_DCDC3_V_OUT_MASK GENMASK(6, 0) +#define AXP192_LDO2_V_OUT_MASK GENMASK(7, 4) +#define AXP192_LDO3_V_OUT_MASK GENMASK(3, 0) +#define AXP192_LDO_IO0_V_OUT_MASK GENMASK(7, 4) + +#define AXP192_PWR_OUT_EXTEN_MASK BIT_MASK(6) +#define AXP192_PWR_OUT_DCDC2_MASK BIT_MASK(4) +#define AXP192_PWR_OUT_LDO3_MASK BIT_MASK(3) +#define AXP192_PWR_OUT_LDO2_MASK BIT_MASK(2) +#define AXP192_PWR_OUT_DCDC3_MASK BIT_MASK(1) +#define AXP192_PWR_OUT_DCDC1_MASK BIT_MASK(0) + #define AXP20X_GPIO0_FUNC_MASK GENMASK(3, 0) #define AXP20X_GPIO1_FUNC_MASK GENMASK(3, 0) @@ -375,25 +398,32 @@ static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp) switch (axp20x->variant) { case AXP209_ID: - if (id == AXP20X_DCDC2) { + if (id == AXP20X_LDO3) { slew_rates = axp209_dcdc2_ldo3_slew_rates; rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates); reg = AXP20X_DCDC2_LDO3_V_RAMP; - mask = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK | - AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK; + mask = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK | + AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK; enable = (ramp > 0) ? - AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN : 0; + AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN : 0; break; } - if (id == AXP20X_LDO3) { + fallthrough; + + case AXP192_ID: + /* + * AXP192 and AXP209 share the same DCDC2 ramp configuration + */ + if ((axp20x->variant == AXP209_ID && id == AXP20X_DCDC2) || + (axp20x->variant == AXP192_ID && id == AXP20X_DCDC2)) { slew_rates = axp209_dcdc2_ldo3_slew_rates; rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates); reg = AXP20X_DCDC2_LDO3_V_RAMP; - mask = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK | - AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK; + mask = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK | + AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK; enable = (ramp > 0) ? - AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN : 0; + AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN : 0; break; } @@ -401,6 +431,7 @@ static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp) break; fallthrough; + default: /* Not supported for this regulator */ return -ENOTSUPP; @@ -415,7 +446,8 @@ static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp) if (ramp > slew_rates[i]) break; - if (id == AXP20X_DCDC2) + if ((axp20x->variant == AXP209_ID && id == AXP20X_DCDC2) || + (axp20x->variant == AXP192_ID && id == AXP192_DCDC2)) cfg = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(i); else cfg = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(i); @@ -511,6 +543,29 @@ static const struct regulator_ops axp20x_ops_sw = { .is_enabled = regulator_is_enabled_regmap, }; +static const struct regulator_desc axp192_regulators[] = { + AXP_DESC(AXP192, DCDC1, "dcdc1", "vin1", 700, 3500, 25, + AXP192_DCDC1_V_OUT, AXP192_DCDC1_V_OUT_MASK, + AXP192_PWR_OUT_CTRL, AXP192_PWR_OUT_DCDC1_MASK), + AXP_DESC(AXP192, DCDC2, "dcdc2", "vin2", 700, 2275, 25, + AXP192_DCDC2_V_OUT, AXP192_DCDC2_V_OUT_MASK, + AXP192_PWR_OUT_CTRL, AXP192_PWR_OUT_DCDC2_MASK), + AXP_DESC(AXP192, DCDC3, "dcdc3", "vin3", 700, 3500, 25, + AXP192_DCDC3_V_OUT, AXP192_DCDC3_V_OUT_MASK, + AXP192_PWR_OUT_CTRL, AXP192_PWR_OUT_DCDC3_MASK), + AXP_DESC_FIXED(AXP192, LDO1, "ldo1", "acin", 1250), + AXP_DESC(AXP192, LDO2, "ldo2", "ldoin", 1800, 3300, 100, + AXP192_LDO2_3_V_OUT, AXP192_LDO2_V_OUT_MASK, + AXP192_PWR_OUT_CTRL, AXP192_PWR_OUT_LDO2_MASK), + AXP_DESC(AXP192, LDO3, "ldo3", "ldoin", 1800, 3300, 100, + AXP192_LDO2_3_V_OUT, AXP192_LDO3_V_OUT_MASK, + AXP192_PWR_OUT_CTRL, AXP192_PWR_OUT_LDO3_MASK), + AXP_DESC_IO(AXP192, LDO_IO0, "ldo_io0", "ips", 700, 3300, 100, + AXP192_LDO_IO0_V_OUT, AXP192_LDO_IO0_V_OUT_MASK, + AXP192_GPIO0_CTRL, AXP192_GPIO0_FUNC_MASK, + AXP192_IO_ENABLED, AXP192_IO_DISABLED), +}; + static const struct linear_range axp20x_ldo4_ranges[] = { REGULATOR_LINEAR_RANGE(1250000, AXP20X_LDO4_V_OUT_1250mV_START, @@ -1008,6 +1063,12 @@ static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq) u32 min, max, def, step; switch (axp20x->variant) { + case AXP192_ID: + min = 900; + max = 2025; + def = 1500; + step = 75; + break; case AXP202_ID: case AXP209_ID: min = 750; @@ -1100,6 +1161,24 @@ static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 work unsigned int mask; switch (axp20x->variant) { + case AXP192_ID: + switch (id) { + case AXP192_DCDC1: + mask = AXP192_WORKMODE_DCDC1_MASK; + break; + case AXP192_DCDC2: + mask = AXP192_WORKMODE_DCDC2_MASK; + break; + case AXP192_DCDC3: + mask = AXP192_WORKMODE_DCDC3_MASK; + break; + default: + return -EINVAL; + } + + workmode <<= ffs(mask) - 1; + break; + case AXP202_ID: case AXP209_ID: if ((id != AXP20X_DCDC2) && (id != AXP20X_DCDC3)) @@ -1220,6 +1299,10 @@ static int axp20x_regulator_probe(struct platform_device *pdev) bool drivevbus = false; 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[92.40.203.126]) by smtp.gmail.com with ESMTPSA id s13-20020a5d6a8d000000b0020c5253d8f7sm7403218wru.67.2022.06.03.06.56.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jun 2022 06:56:50 -0700 (PDT) From: Aidan MacDonald To: linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, wens@csie.org, jic23@kernel.org, lee.jones@linaro.org, sre@kernel.org, broonie@kernel.org, gregkh@linuxfoundation.org, lgirdwood@gmail.com Cc: lars@metafoo.de, rafael@kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/10] iio: adc: axp20x_adc: Add support for AXP192 Date: Fri, 3 Jun 2022 14:57:12 +0100 Message-Id: <20220603135714.12007-9-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220603135714.12007-1-aidanmacdonald.0x0@gmail.com> References: <20220603135714.12007-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The AXP192 is identical to the AXP20x, except for the addition of two more GPIO ADC channels. Signed-off-by: Aidan MacDonald --- drivers/iio/adc/axp20x_adc.c | 289 +++++++++++++++++++++++++++++++++-- 1 file changed, 280 insertions(+), 9 deletions(-) diff --git a/drivers/iio/adc/axp20x_adc.c b/drivers/iio/adc/axp20x_adc.c index 53bf7d4899d2..7d2bf9529420 100644 --- a/drivers/iio/adc/axp20x_adc.c +++ b/drivers/iio/adc/axp20x_adc.c @@ -21,6 +21,9 @@ #include #include +#define AXP192_ADC_EN1_MASK GENMASK(7, 0) +#define AXP192_ADC_EN2_MASK (BIT(7) | GENMASK(3, 0)) + #define AXP20X_ADC_EN1_MASK GENMASK(7, 0) #define AXP20X_ADC_EN2_MASK (GENMASK(3, 2) | BIT(7)) @@ -31,6 +34,15 @@ #define AXP20X_GPIO10_IN_RANGE_GPIO0_VAL(x) ((x) & BIT(0)) #define AXP20X_GPIO10_IN_RANGE_GPIO1_VAL(x) (((x) & BIT(0)) << 1) +#define AXP192_GPIO30_IN_RANGE_GPIO0 BIT(0) +#define AXP192_GPIO30_IN_RANGE_GPIO1 BIT(1) +#define AXP192_GPIO30_IN_RANGE_GPIO2 BIT(2) +#define AXP192_GPIO30_IN_RANGE_GPIO3 BIT(3) +#define AXP192_GPIO30_IN_RANGE_GPIO0_VAL(x) ((x) & BIT(0)) +#define AXP192_GPIO30_IN_RANGE_GPIO1_VAL(x) (((x) & BIT(0)) << 1) +#define AXP192_GPIO30_IN_RANGE_GPIO2_VAL(x) (((x) & BIT(0)) << 2) +#define AXP192_GPIO30_IN_RANGE_GPIO3_VAL(x) (((x) & BIT(0)) << 3) + #define AXP20X_ADC_RATE_MASK GENMASK(7, 6) #define AXP813_V_I_ADC_RATE_MASK GENMASK(5, 4) #define AXP813_ADC_RATE_MASK (AXP20X_ADC_RATE_MASK | AXP813_V_I_ADC_RATE_MASK) @@ -70,6 +82,25 @@ struct axp20x_adc_iio { const struct axp_data *data; }; +enum axp192_adc_channel_v { + AXP192_ACIN_V = 0, + AXP192_VBUS_V, + AXP192_TS_IN, + AXP192_GPIO0_V, + AXP192_GPIO1_V, + AXP192_GPIO2_V, + AXP192_GPIO3_V, + AXP192_IPSOUT_V, + AXP192_BATT_V, +}; + +enum axp192_adc_channel_i { + AXP192_ACIN_I = 0, + AXP192_VBUS_I, + AXP192_BATT_CHRG_I, + AXP192_BATT_DISCHRG_I, +}; + enum axp20x_adc_channel_v { AXP20X_ACIN_V = 0, AXP20X_VBUS_V, @@ -157,6 +188,43 @@ static struct iio_map axp22x_maps[] = { * The only exception is for the battery. batt_v will be in_voltage6_raw and * charge current in_current6_raw and discharge current will be in_current7_raw. */ +static const struct iio_chan_spec axp192_adc_channels[] = { + AXP20X_ADC_CHANNEL(AXP192_ACIN_V, "acin_v", IIO_VOLTAGE, + AXP20X_ACIN_V_ADC_H), + AXP20X_ADC_CHANNEL(AXP192_ACIN_I, "acin_i", IIO_CURRENT, + AXP20X_ACIN_I_ADC_H), + AXP20X_ADC_CHANNEL(AXP192_VBUS_V, "vbus_v", IIO_VOLTAGE, + AXP20X_VBUS_V_ADC_H), + AXP20X_ADC_CHANNEL(AXP192_VBUS_I, "vbus_i", IIO_CURRENT, + AXP20X_VBUS_I_ADC_H), + { + .type = IIO_TEMP, + .address = AXP20X_TEMP_ADC_H, + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | + BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_OFFSET), + .datasheet_name = "pmic_temp", + }, + AXP20X_ADC_CHANNEL_OFFSET(AXP192_GPIO0_V, "gpio0_v", IIO_VOLTAGE, + AXP20X_GPIO0_V_ADC_H), + AXP20X_ADC_CHANNEL_OFFSET(AXP192_GPIO1_V, "gpio1_v", IIO_VOLTAGE, + AXP20X_GPIO1_V_ADC_H), + AXP20X_ADC_CHANNEL_OFFSET(AXP192_GPIO2_V, "gpio2_v", IIO_VOLTAGE, + AXP192_GPIO2_V_ADC_H), + AXP20X_ADC_CHANNEL_OFFSET(AXP192_GPIO3_V, "gpio3_v", IIO_VOLTAGE, + AXP192_GPIO3_V_ADC_H), + AXP20X_ADC_CHANNEL(AXP192_IPSOUT_V, "ipsout_v", IIO_VOLTAGE, + AXP20X_IPSOUT_V_HIGH_H), + AXP20X_ADC_CHANNEL(AXP192_BATT_V, "batt_v", IIO_VOLTAGE, + AXP20X_BATT_V_H), + AXP20X_ADC_CHANNEL(AXP192_BATT_CHRG_I, "batt_chrg_i", IIO_CURRENT, + AXP20X_BATT_CHRG_I_H), + AXP20X_ADC_CHANNEL(AXP192_BATT_DISCHRG_I, "batt_dischrg_i", IIO_CURRENT, + AXP20X_BATT_DISCHRG_I_H), + AXP20X_ADC_CHANNEL(AXP192_TS_IN, "ts_v", IIO_VOLTAGE, + AXP20X_TS_IN_H), +}; + static const struct iio_chan_spec axp20x_adc_channels[] = { AXP20X_ADC_CHANNEL(AXP20X_ACIN_V, "acin_v", IIO_VOLTAGE, AXP20X_ACIN_V_ADC_H), @@ -277,6 +345,44 @@ static int axp813_adc_raw(struct iio_dev *indio_dev, return IIO_VAL_INT; } +static int axp192_adc_scale_voltage(int channel, int *val, int *val2) +{ + switch (channel) { + case AXP192_ACIN_V: + case AXP192_VBUS_V: + *val = 1; + *val2 = 700000; + return IIO_VAL_INT_PLUS_MICRO; + + case AXP192_GPIO0_V: + case AXP192_GPIO1_V: + case AXP192_GPIO2_V: + case AXP192_GPIO3_V: + *val = 0; + *val2 = 500000; + return IIO_VAL_INT_PLUS_MICRO; + + case AXP192_BATT_V: + *val = 1; + *val2 = 100000; + return IIO_VAL_INT_PLUS_MICRO; + + case AXP192_IPSOUT_V: + *val = 1; + *val2 = 400000; + return IIO_VAL_INT_PLUS_MICRO; + + case AXP192_TS_IN: + /* 0.8 mV per LSB */ + *val = 0; + *val2 = 800000; + return IIO_VAL_INT_PLUS_MICRO; + + default: + return -EINVAL; + } +} + static int axp20x_adc_scale_voltage(int channel, int *val, int *val2) { switch (channel) { @@ -380,6 +486,29 @@ static int axp20x_adc_scale_current(int channel, int *val, int *val2) } } +static int axp192_adc_scale(struct iio_chan_spec const *chan, int *val, + int *val2) +{ + switch (chan->type) { + case IIO_VOLTAGE: + return axp192_adc_scale_voltage(chan->channel, val, val2); + + case IIO_CURRENT: + /* + * AXP192 current channels are identical to the AXP20x, + * therefore we can re-use the scaling function. + */ + return axp20x_adc_scale_current(chan->channel, val, val2); + + case IIO_TEMP: + *val = 100; + return IIO_VAL_INT; + + default: + return -EINVAL; + } +} + static int axp20x_adc_scale(struct iio_chan_spec const *chan, int *val, int *val2) { @@ -439,6 +568,42 @@ static int axp813_adc_scale(struct iio_chan_spec const *chan, int *val, } } +static int axp192_adc_offset_voltage(struct iio_dev *indio_dev, int channel, + int *val) +{ + struct axp20x_adc_iio *info = iio_priv(indio_dev); + int ret; + + ret = regmap_read(info->regmap, AXP192_GPIO30_IN_RANGE, val); + if (ret < 0) + return ret; + + switch (channel) { + case AXP192_GPIO0_V: + *val &= AXP192_GPIO30_IN_RANGE_GPIO0; + break; + + case AXP192_GPIO1_V: + *val &= AXP192_GPIO30_IN_RANGE_GPIO1; + break; + + case AXP192_GPIO2_V: + *val &= AXP192_GPIO30_IN_RANGE_GPIO2; + break; + + case AXP192_GPIO3_V: + *val &= AXP192_GPIO30_IN_RANGE_GPIO3; + break; + + default: + return -EINVAL; + } + + *val = *val ? 700000 : 0; + + return IIO_VAL_INT; +} + static int axp20x_adc_offset_voltage(struct iio_dev *indio_dev, int channel, int *val) { @@ -467,6 +632,22 @@ static int axp20x_adc_offset_voltage(struct iio_dev *indio_dev, int channel, return IIO_VAL_INT; } +static int axp192_adc_offset(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val) +{ + switch (chan->type) { + case IIO_VOLTAGE: + return axp192_adc_offset_voltage(indio_dev, chan->channel, val); + + case IIO_TEMP: + *val = -1447; + return IIO_VAL_INT; + + default: + return -EINVAL; + } +} + static int axp20x_adc_offset(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val) { @@ -483,6 +664,25 @@ static int axp20x_adc_offset(struct iio_dev *indio_dev, } } +static int axp192_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int *val, + int *val2, long mask) +{ + switch (mask) { + case IIO_CHAN_INFO_OFFSET: + return axp192_adc_offset(indio_dev, chan, val); + + case IIO_CHAN_INFO_SCALE: + return axp192_adc_scale(chan, val, val2); + + case IIO_CHAN_INFO_RAW: + return axp20x_adc_raw(indio_dev, chan, val); + + default: + return -EINVAL; + } +} + static int axp20x_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) @@ -543,6 +743,54 @@ static int axp813_read_raw(struct iio_dev *indio_dev, } } +static int axp192_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, int val, int val2, + long mask) +{ + struct axp20x_adc_iio *info = iio_priv(indio_dev); + unsigned int reg, regval; + + /* + * The AXP192 PMIC allows the user to choose between 0V and 0.7V offsets + * for (independently) GPIO0-3 when in ADC mode. + */ + if (mask != IIO_CHAN_INFO_OFFSET) + return -EINVAL; + + if (val != 0 && val != 700000) + return -EINVAL; + + val = val ? 1 : 0; + + switch (chan->channel) { + case AXP192_GPIO0_V: + reg = AXP192_GPIO30_IN_RANGE_GPIO0; + regval = AXP192_GPIO30_IN_RANGE_GPIO0_VAL(val); + break; + + case AXP192_GPIO1_V: + reg = AXP192_GPIO30_IN_RANGE_GPIO1; + regval = AXP192_GPIO30_IN_RANGE_GPIO1_VAL(val); + break; + + case AXP192_GPIO2_V: + reg = AXP192_GPIO30_IN_RANGE_GPIO2; + regval = AXP192_GPIO30_IN_RANGE_GPIO2_VAL(val); + break; + + case AXP192_GPIO3_V: + reg = AXP192_GPIO30_IN_RANGE_GPIO3; + regval = AXP192_GPIO30_IN_RANGE_GPIO3_VAL(val); + break; + + default: + return -EINVAL; + } + + return regmap_update_bits(info->regmap, AXP192_GPIO30_IN_RANGE, reg, + regval); +} + static int axp20x_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) @@ -581,6 +829,18 @@ static int axp20x_write_raw(struct iio_dev *indio_dev, regval); } +static int axp192_read_label(struct iio_dev *iio_dev, + const struct iio_chan_spec *chan, char *label) +{ + return snprintf(label, PAGE_SIZE, "%s\n", chan->datasheet_name); +} + +static const struct iio_info axp192_adc_iio_info = { + .read_raw = axp192_read_raw, + .write_raw = axp192_write_raw, + .read_label = axp192_read_label, +}; + static const struct iio_info axp20x_adc_iio_info = { .read_raw = axp20x_read_raw, .write_raw = axp20x_write_raw, @@ -620,19 +880,29 @@ struct axp_data { int num_channels; struct iio_chan_spec const *channels; unsigned long adc_en1_mask; + unsigned long adc_en2_mask; int (*adc_rate)(struct axp20x_adc_iio *info, int rate); - bool adc_en2; struct iio_map *maps; }; +static const struct axp_data axp192_data = { + .iio_info = &axp192_adc_iio_info, + .num_channels = ARRAY_SIZE(axp192_adc_channels), + .channels = axp192_adc_channels, + .adc_en1_mask = AXP192_ADC_EN1_MASK, + .adc_en2_mask = AXP192_ADC_EN2_MASK, + .adc_rate = axp20x_adc_rate, + .maps = axp20x_maps, +}; + static const struct axp_data axp20x_data = { .iio_info = &axp20x_adc_iio_info, .num_channels = ARRAY_SIZE(axp20x_adc_channels), .channels = axp20x_adc_channels, .adc_en1_mask = AXP20X_ADC_EN1_MASK, + .adc_en2_mask = AXP20X_ADC_EN2_MASK, .adc_rate = axp20x_adc_rate, - .adc_en2 = true, .maps = axp20x_maps, }; @@ -642,7 +912,6 @@ static const struct axp_data axp22x_data = { .channels = axp22x_adc_channels, .adc_en1_mask = AXP22X_ADC_EN1_MASK, .adc_rate = axp22x_adc_rate, - .adc_en2 = false, .maps = axp22x_maps, }; @@ -652,11 +921,11 @@ static const struct axp_data axp813_data = { .channels = axp813_adc_channels, .adc_en1_mask = AXP22X_ADC_EN1_MASK, .adc_rate = axp813_adc_rate, - .adc_en2 = false, .maps = axp22x_maps, }; static const struct of_device_id axp20x_adc_of_match[] = { + { .compatible = "x-powers,axp192-adc", .data = (void *)&axp192_data, }, { .compatible = "x-powers,axp209-adc", .data = (void *)&axp20x_data, }, { .compatible = "x-powers,axp221-adc", .data = (void *)&axp22x_data, }, { .compatible = "x-powers,axp813-adc", .data = (void *)&axp813_data, }, @@ -665,6 +934,7 @@ static const struct of_device_id axp20x_adc_of_match[] = { MODULE_DEVICE_TABLE(of, axp20x_adc_of_match); static const struct platform_device_id axp20x_adc_id_match[] = { + { .name = "axp192-adc", .driver_data = (kernel_ulong_t)&axp192_data, }, { .name = "axp20x-adc", .driver_data = (kernel_ulong_t)&axp20x_data, }, { .name = "axp22x-adc", .driver_data = (kernel_ulong_t)&axp22x_data, }, { .name = "axp813-adc", .driver_data = (kernel_ulong_t)&axp813_data, }, @@ -710,10 +980,11 @@ static int axp20x_probe(struct platform_device *pdev) /* Enable the ADCs on IP */ regmap_write(info->regmap, AXP20X_ADC_EN1, info->data->adc_en1_mask); - if (info->data->adc_en2) - /* Enable GPIO0/1 and internal temperature ADCs */ + if (info->data->adc_en2_mask) + /* Enable GPIO and internal temperature ADCs */ regmap_update_bits(info->regmap, AXP20X_ADC_EN2, - AXP20X_ADC_EN2_MASK, AXP20X_ADC_EN2_MASK); + info->data->adc_en2_mask, + info->data->adc_en2_mask); /* Configure ADCs rate */ info->data->adc_rate(info, 100); @@ -738,7 +1009,7 @@ static int axp20x_probe(struct platform_device *pdev) fail_map: regmap_write(info->regmap, AXP20X_ADC_EN1, 0); - if (info->data->adc_en2) + if (info->data->adc_en2_mask) regmap_write(info->regmap, AXP20X_ADC_EN2, 0); return ret; @@ -754,7 +1025,7 @@ static int axp20x_remove(struct platform_device *pdev) regmap_write(info->regmap, AXP20X_ADC_EN1, 0); - if (info->data->adc_en2) + if (info->data->adc_en2_mask) regmap_write(info->regmap, AXP20X_ADC_EN2, 0); return 0; From patchwork Fri Jun 3 13:57:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aidan MacDonald X-Patchwork-Id: 578592 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25FF3CCA47E for ; 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[92.40.203.126]) by smtp.gmail.com with ESMTPSA id h7-20020a05600c414700b0039787538c9csm3670131wmm.20.2022.06.03.06.56.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jun 2022 06:56:51 -0700 (PDT) From: Aidan MacDonald To: linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, wens@csie.org, jic23@kernel.org, lee.jones@linaro.org, sre@kernel.org, broonie@kernel.org, gregkh@linuxfoundation.org, lgirdwood@gmail.com Cc: lars@metafoo.de, rafael@kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/10] power: supply: axp20x_usb_power: Add support for AXP192 Date: Fri, 3 Jun 2022 14:57:13 +0100 Message-Id: <20220603135714.12007-10-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220603135714.12007-1-aidanmacdonald.0x0@gmail.com> References: <20220603135714.12007-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The AXP192 is mostly the same as the AXP202 but has a different current limit. Signed-off-by: Aidan MacDonald Reported-by: kernel test robot --- drivers/power/supply/axp20x_usb_power.c | 75 +++++++++++++++++++++++-- 1 file changed, 70 insertions(+), 5 deletions(-) diff --git a/drivers/power/supply/axp20x_usb_power.c b/drivers/power/supply/axp20x_usb_power.c index a1e6d1d44808..e1266b8265bc 100644 --- a/drivers/power/supply/axp20x_usb_power.c +++ b/drivers/power/supply/axp20x_usb_power.c @@ -48,6 +48,9 @@ #define AXP813_VBUS_CLIMIT_2000mA 2 #define AXP813_VBUS_CLIMIT_2500mA 3 +#define AXP192_VBUS_CLIMIT_EN BIT(1) +#define AXP192_VBUS_CLIMIT_100mA BIT(0) + #define AXP20X_ADC_EN1_VBUS_CURR BIT(2) #define AXP20X_ADC_EN1_VBUS_VOLT BIT(3) @@ -121,6 +124,24 @@ static void axp20x_usb_power_poll_vbus(struct work_struct *work) mod_delayed_work(system_power_efficient_wq, &power->vbus_detect, DEBOUNCE_TIME); } +static int axp192_get_current_max(struct axp20x_usb_power *power, int *val) +{ + unsigned int v; + int ret = regmap_read(power->regmap, AXP20X_VBUS_IPSOUT_MGMT, &v); + + if (ret) + return ret; + + if (!(v & AXP192_VBUS_CLIMIT_EN)) + *val = -1; + else if (v & AXP192_VBUS_CLIMIT_100mA) + *val = 100000; + else + *val = 500000; + + return 0; +} + static int axp20x_get_current_max(struct axp20x_usb_power *power, int *val) { unsigned int v; @@ -179,7 +200,7 @@ static int axp20x_usb_power_get_property(struct power_supply *psy, enum power_supply_property psp, union power_supply_propval *val) { struct axp20x_usb_power *power = power_supply_get_drvdata(psy); - unsigned int input, v; + unsigned int input, v, reg; int ret; switch (psp) { @@ -215,6 +236,8 @@ static int axp20x_usb_power_get_property(struct power_supply *psy, case POWER_SUPPLY_PROP_CURRENT_MAX: if (power->axp20x_id == AXP813_ID) return axp813_get_current_max(power, &val->intval); + else if (power->axp20x_id == AXP192_ID) + return axp192_get_current_max(power, &val->intval); return axp20x_get_current_max(power, &val->intval); case POWER_SUPPLY_PROP_CURRENT_NOW: if (IS_ENABLED(CONFIG_AXP20X_ADC)) { @@ -256,15 +279,26 @@ static int axp20x_usb_power_get_property(struct power_supply *psy, val->intval = POWER_SUPPLY_HEALTH_GOOD; - if (power->axp20x_id == AXP202_ID) { - ret = regmap_read(power->regmap, - AXP20X_USB_OTG_STATUS, &v); + switch (power->axp20x_id) { + case AXP192_ID: + /* Same layout as the AXP202, but different address */ + reg = AXP192_USB_OTG_STATUS; + fallthrough; + + case AXP202_ID: + if (power->axp20x_id == AXP202_ID) + reg = AXP20X_USB_OTG_STATUS; + + ret = regmap_read(power->regmap, reg, &v); if (ret) return ret; if (!(v & AXP20X_USB_STATUS_VBUS_VALID)) val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE; + + default: + break; } break; case POWER_SUPPLY_PROP_PRESENT: @@ -316,6 +350,24 @@ static int axp20x_usb_power_set_voltage_min(struct axp20x_usb_power *power, return -EINVAL; } +static int axp192_usb_power_set_current_max(struct axp20x_usb_power *power, + int intval) +{ + int val = AXP192_VBUS_CLIMIT_EN; + const int mask = AXP192_VBUS_CLIMIT_EN | AXP192_VBUS_CLIMIT_100mA; + + switch (intval) { + case 100000: + val |= AXP192_VBUS_CLIMIT_100mA; + fallthrough; + case 500000: + return regmap_update_bits(power->regmap, + AXP20X_VBUS_IPSOUT_MGMT, mask, val); + default: + return -EINVAL; + } +} + static int axp813_usb_power_set_current_max(struct axp20x_usb_power *power, int intval) { @@ -383,6 +435,9 @@ static int axp20x_usb_power_set_property(struct power_supply *psy, if (power->axp20x_id == AXP813_ID) return axp813_usb_power_set_current_max(power, val->intval); + else if (power->axp20x_id == AXP192_ID) + return axp192_usb_power_set_current_max(power, + val->intval); return axp20x_usb_power_set_current_max(power, val->intval); default: @@ -468,6 +523,13 @@ struct axp_data { enum axp20x_variants axp20x_id; }; +static const struct axp_data axp192_data = { + .power_desc = &axp20x_usb_power_desc, + .irq_names = axp20x_irq_names, + .num_irq_names = ARRAY_SIZE(axp20x_irq_names), + .axp20x_id = AXP192_ID, +}; + static const struct axp_data axp202_data = { .power_desc = &axp20x_usb_power_desc, .irq_names = axp20x_irq_names, @@ -600,7 +662,7 @@ static int axp20x_usb_power_probe(struct platform_device *pdev) if (ret) return ret; - if (power->axp20x_id == AXP202_ID) { + if (power->axp20x_id == AXP192_ID || power->axp20x_id == AXP202_ID) { /* Enable vbus valid checking */ ret = regmap_update_bits(power->regmap, AXP20X_VBUS_MON, AXP20X_VBUS_MON_VBUS_VALID, @@ -659,6 +721,9 @@ static int axp20x_usb_power_probe(struct platform_device *pdev) static const struct of_device_id axp20x_usb_power_match[] = { { + .compatible = "x-powers,axp192-usb-power-supply", + .data = &axp192_data, + }, { .compatible = "x-powers,axp202-usb-power-supply", .data = &axp202_data, }, { From patchwork Fri Jun 3 13:57:14 2022 Content-Type: text/plain; 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[92.40.203.126]) by smtp.gmail.com with ESMTPSA id bg16-20020a05600c3c9000b0039763d41a48sm9597710wmb.25.2022.06.03.06.56.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jun 2022 06:56:53 -0700 (PDT) From: Aidan MacDonald To: linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, wens@csie.org, jic23@kernel.org, lee.jones@linaro.org, sre@kernel.org, broonie@kernel.org, gregkh@linuxfoundation.org, lgirdwood@gmail.com Cc: lars@metafoo.de, rafael@kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-iio@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/10] pinctrl: Add AXP192 pin control driver Date: Fri, 3 Jun 2022 14:57:14 +0100 Message-Id: <20220603135714.12007-11-aidanmacdonald.0x0@gmail.com> In-Reply-To: <20220603135714.12007-1-aidanmacdonald.0x0@gmail.com> References: <20220603135714.12007-1-aidanmacdonald.0x0@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The AXP192 PMIC's GPIO registers are much different from the GPIO registers of the AXP20x and AXP813 PMICs supported by the existing pinctrl-axp209 driver. It makes more sense to add a new driver for the AXP192, rather than add support in the existing axp20x driver. The pinctrl-axp192 driver is considerably more flexible in terms of register layout and should be able to support other X-Powers PMICs. Interrupts and pull down resistor configuration are supported too. Signed-off-by: Aidan MacDonald --- drivers/pinctrl/Kconfig | 14 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-axp192.c | 589 +++++++++++++++++++++++++++++++ 3 files changed, 604 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-axp192.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index f52960d2dfbe..a71e35de333d 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -113,6 +113,20 @@ config PINCTRL_AT91PIO4 Say Y here to enable the at91 pinctrl/gpio driver for Atmel PIO4 controller available on sama5d2 SoC. +config PINCTRL_AXP192 + tristate "X-Powers AXP192 PMIC pinctrl and GPIO Support" + depends on MFD_AXP20X + depends on OF + select PINMUX + select GENERIC_PINCONF + select GPIOLIB + help + AXP PMICs provides multiple GPIOs that can be muxed for different + functions. This driver bundles a pinctrl driver to select the function + muxing and a GPIO driver to handle the GPIO when the GPIO function is + selected. + Say Y to enable pinctrl and GPIO support for the AXP192 PMIC. + config PINCTRL_AXP209 tristate "X-Powers AXP209 PMIC pinctrl and GPIO Support" depends on MFD_AXP20X diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index e76f5cdc64b0..9d2b6420c5dd 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PINCTRL_ARTPEC6) += pinctrl-artpec6.o obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o +obj-$(CONFIG_PINCTRL_AXP192) += pinctrl-axp192.o obj-$(CONFIG_PINCTRL_AXP209) += pinctrl-axp209.o obj-$(CONFIG_PINCTRL_BM1880) += pinctrl-bm1880.o obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o diff --git a/drivers/pinctrl/pinctrl-axp192.c b/drivers/pinctrl/pinctrl-axp192.c new file mode 100644 index 000000000000..0ff2d0b84978 --- /dev/null +++ b/drivers/pinctrl/pinctrl-axp192.c @@ -0,0 +1,589 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * AXP192 pinctrl and GPIO driver + * + * Copyright (C) 2022 Aidan MacDonald + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +enum { + AXP192_FUNC_OUTPUT = 0, + AXP192_FUNC_INPUT, + AXP192_FUNC_LDO, + AXP192_FUNC_PWM, + AXP192_FUNC_ADC, + AXP192_FUNC_LOW_OUTPUT, + AXP192_FUNC_FLOATING, + AXP192_FUNC_EXT_CHG_CTL, + AXP192_FUNC_LDO_STATUS, + AXP192_FUNCS_NB, +}; + +struct axp192_pctl_function { + const char *name; + /* Mux value written to the control register to select the function (-1 if unsupported) */ + const u8 *muxvals; + const char * const *groups; + unsigned int ngroups; +}; + +struct axp192_pctl_reg_info { + u8 reg; + u8 mask; +}; + +struct axp192_pctl_desc { + unsigned int npins; + const struct pinctrl_pin_desc *pins; + /* Description of the function control register for each pin */ + const struct axp192_pctl_reg_info *ctrl_regs; + /* Description of the output signal register for each pin */ + const struct axp192_pctl_reg_info *out_regs; + /* Description of the input signal register for each pin */ + const struct axp192_pctl_reg_info *in_regs; + /* Description of the pull down resistor config register for each pin */ + const struct axp192_pctl_reg_info *pull_down_regs; + + unsigned int nfunctions; + const struct axp192_pctl_function *functions; +}; + +static const struct pinctrl_pin_desc axp192_pins[] = { + PINCTRL_PIN(0, "GPIO0"), + PINCTRL_PIN(1, "GPIO1"), + PINCTRL_PIN(2, "GPIO2"), + PINCTRL_PIN(3, "GPIO3"), + PINCTRL_PIN(4, "GPIO4"), + PINCTRL_PIN(5, "N_RSTO"), +}; + +static const char * const axp192_io_groups[] = { "GPIO0", "GPIO1", "GPIO2", + "GPIO3", "GPIO4", "N_RSTO" }; +static const char * const axp192_ldo_groups[] = { "GPIO0" }; +static const char * const axp192_pwm_groups[] = { "GPIO1", "GPIO2" }; +static const char * const axp192_adc_groups[] = { "GPIO0", "GPIO1", "GPIO2", "GPIO3" }; +static const char * const axp192_extended_io_groups[] = { "GPIO0", "GPIO1", "GPIO2" }; +static const char * const axp192_ext_chg_ctl_groups[] = { "GPIO3", "GPIO4" }; +static const char * const axp192_ldo_status_groups[] = { "N_RSTO" }; + +static const u8 axp192_output_muxvals[] = { 0, 0, 0, 1, 1, 2 }; +static const u8 axp192_input_muxvals[] = { 1, 1, 1, 2, 2, 3 }; +static const u8 axp192_ldo_muxvals[] = { 2, -1, -1, -1, -1, -1 }; +static const u8 axp192_pwm_muxvals[] = { -1, 2, 2, -1, -1, -1 }; +static const u8 axp192_adc_muxvals[] = { 4, 4, 4, 3, -1, -1 }; +static const u8 axp192_low_output_muxvals[] = { 5, 5, 5, -1, -1, -1 }; +static const u8 axp192_floating_muxvals[] = { 6, 6, 6, -1, -1, -1 }; +static const u8 axp192_ext_chg_ctl_muxvals[] = { -1, -1, -1, 0, 0, -1 }; +static const u8 axp192_ldo_status_muxvals[] = { -1, -1, -1, -1, -1, 0 }; + +static const struct axp192_pctl_function axp192_functions[AXP192_FUNCS_NB] = { + [AXP192_FUNC_OUTPUT] = { + .name = "output", + .muxvals = axp192_output_muxvals, + .groups = axp192_io_groups, + .ngroups = ARRAY_SIZE(axp192_io_groups), + }, + [AXP192_FUNC_INPUT] = { + .name = "input", + .muxvals = axp192_input_muxvals, + .groups = axp192_io_groups, + .ngroups = ARRAY_SIZE(axp192_io_groups), + }, + [AXP192_FUNC_LDO] = { + .name = "ldo", + .muxvals = axp192_ldo_muxvals, + .groups = axp192_ldo_groups, + .ngroups = ARRAY_SIZE(axp192_ldo_groups), + }, + [AXP192_FUNC_PWM] = { + .name = "pwm", + .muxvals = axp192_pwm_muxvals, + .groups = axp192_pwm_groups, + .ngroups = ARRAY_SIZE(axp192_pwm_groups), + }, + [AXP192_FUNC_ADC] = { + .name = "adc", + .muxvals = axp192_adc_muxvals, + .groups = axp192_adc_groups, + .ngroups = ARRAY_SIZE(axp192_adc_groups), + }, + [AXP192_FUNC_LOW_OUTPUT] = { + .name = "low_output", + .muxvals = axp192_low_output_muxvals, + .groups = axp192_extended_io_groups, + .ngroups = ARRAY_SIZE(axp192_extended_io_groups), + }, + [AXP192_FUNC_FLOATING] = { + .name = "floating", + .muxvals = axp192_floating_muxvals, + .groups = axp192_extended_io_groups, + .ngroups = ARRAY_SIZE(axp192_extended_io_groups), + }, + [AXP192_FUNC_EXT_CHG_CTL] = { + .name = "ext_chg_ctl", + .muxvals = axp192_ext_chg_ctl_muxvals, + .groups = axp192_ext_chg_ctl_groups, + .ngroups = ARRAY_SIZE(axp192_ext_chg_ctl_groups), + }, + [AXP192_FUNC_LDO_STATUS] = { + .name = "ldo_status", + .muxvals = axp192_ldo_status_muxvals, + .groups = axp192_ldo_groups, + .ngroups = ARRAY_SIZE(axp192_ldo_status_groups), + }, +}; + +static const struct axp192_pctl_reg_info axp192_pin_ctrl_regs[] = { + { .reg = AXP192_GPIO0_CTRL, .mask = 0x07 }, + { .reg = AXP192_GPIO1_CTRL, .mask = 0x07 }, + { .reg = AXP192_GPIO2_CTRL, .mask = 0x07 }, + { .reg = AXP192_GPIO4_3_CTRL, .mask = 0x03 }, + { .reg = AXP192_GPIO4_3_CTRL, .mask = 0x0c }, + { .reg = AXP192_N_RSTO_CTRL, .mask = 0xc0 }, +}; + +static const struct axp192_pctl_reg_info axp192_pin_in_regs[] = { + { .reg = AXP192_GPIO2_0_STATE, .mask = BIT(4) }, + { .reg = AXP192_GPIO2_0_STATE, .mask = BIT(5) }, + { .reg = AXP192_GPIO2_0_STATE, .mask = BIT(6) }, + { .reg = AXP192_GPIO4_3_STATE, .mask = BIT(4) }, + { .reg = AXP192_GPIO4_3_STATE, .mask = BIT(5) }, + { .reg = AXP192_N_RSTO_CTRL, .mask = BIT(4) }, +}; + +static const struct axp192_pctl_reg_info axp192_pin_out_regs[] = { + { .reg = AXP192_GPIO2_0_STATE, .mask = BIT(0) }, + { .reg = AXP192_GPIO2_0_STATE, .mask = BIT(1) }, + { .reg = AXP192_GPIO2_0_STATE, .mask = BIT(2) }, + { .reg = AXP192_GPIO4_3_STATE, .mask = BIT(0) }, + { .reg = AXP192_GPIO4_3_STATE, .mask = BIT(1) }, + { .reg = AXP192_N_RSTO_CTRL, .mask = BIT(5) }, +}; + +static const struct axp192_pctl_reg_info axp192_pull_down_regs[] = { + { .reg = AXP192_GPIO2_0_PULL, .mask = BIT(0) }, + { .reg = AXP192_GPIO2_0_PULL, .mask = BIT(1) }, + { .reg = AXP192_GPIO2_0_PULL, .mask = BIT(2) }, + { .reg = 0, .mask = 0 /* unsupported */ }, + { .reg = 0, .mask = 0 /* unsupported */ }, + { .reg = 0, .mask = 0 /* unsupported */ }, +}; + +static const struct axp192_pctl_desc axp192_data = { + .npins = ARRAY_SIZE(axp192_pins), + .pins = axp192_pins, + .ctrl_regs = axp192_pin_ctrl_regs, + .out_regs = axp192_pin_out_regs, + .in_regs = axp192_pin_in_regs, + .pull_down_regs = axp192_pull_down_regs, + + .nfunctions = ARRAY_SIZE(axp192_functions), + .functions = axp192_functions, +}; + + +struct axp192_pctl { + struct gpio_chip chip; + struct regmap *regmap; + struct pinctrl_dev *pctl_dev; + struct device *dev; + const struct axp192_pctl_desc *desc; + int *irqs; +}; + +static int axp192_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct axp192_pctl *pctl = gpiochip_get_data(chip); + const struct axp192_pctl_reg_info *reginfo = &pctl->desc->in_regs[offset]; + unsigned int val; + int ret; + + ret = regmap_read(pctl->regmap, reginfo->reg, &val); + if (ret) + return ret; + + return !!(val & reginfo->mask); +} + +static int axp192_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + struct axp192_pctl *pctl = gpiochip_get_data(chip); + const struct axp192_pctl_reg_info *reginfo = &pctl->desc->ctrl_regs[offset]; + const u8 *input_muxvals = pctl->desc->functions[AXP192_FUNC_INPUT].muxvals; + unsigned int val; + int ret; + + ret = regmap_read(pctl->regmap, reginfo->reg, &val); + if (ret) + return ret; + + if ((val & reginfo->mask) == (input_muxvals[offset] << (ffs(reginfo->mask) - 1))) + return GPIO_LINE_DIRECTION_IN; + else + return GPIO_LINE_DIRECTION_OUT; +} + +static void axp192_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + struct axp192_pctl *pctl = gpiochip_get_data(chip); + const struct axp192_pctl_reg_info *reginfo = &pctl->desc->out_regs[offset]; + + regmap_update_bits(pctl->regmap, reginfo->reg, reginfo->mask, value ? reginfo->mask : 0); +} + +static int axp192_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + return pinctrl_gpio_direction_input(chip->base + offset); +} + +static int axp192_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value) +{ + chip->set(chip, offset, value); + return 0; +} + +static int axp192_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) +{ + struct axp192_pctl *pctl = gpiochip_get_data(chip); + + return pctl->irqs[offset]; +} + +static int axp192_pinconf_get_pull_down(struct pinctrl_dev *pctldev, unsigned int pin) +{ + struct axp192_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); + const struct axp192_pctl_reg_info *reginfo = &pctl->desc->pull_down_regs[pin]; + unsigned int val; + int ret; + + if (!reginfo->mask) + return -EOPNOTSUPP; + + ret = regmap_read(pctl->regmap, reginfo->reg, &val); + if (ret) + return ret; + + return !!(val & reginfo->mask); +} + +static int axp192_pinconf_set_pull_down(struct pinctrl_dev *pctldev, unsigned int pin, int value) +{ + struct axp192_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); + const struct axp192_pctl_reg_info *reginfo = &pctl->desc->pull_down_regs[pin]; + + if (!reginfo->mask) + return -EOPNOTSUPP; + + return regmap_update_bits(pctl->regmap, reginfo->reg, reginfo->mask, + value ? reginfo->mask : 0); +} + +static int axp192_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) +{ + enum pin_config_param param = pinconf_to_config_param(*config); + unsigned int arg = 1; + int ret; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + ret = axp192_pinconf_get_pull_down(pctldev, pin); + if (ret < 0) + return ret; + else if (ret != 0) + return -EINVAL; + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + ret = axp192_pinconf_get_pull_down(pctldev, pin); + if (ret < 0) + return ret; + else if (ret == 0) + return -EINVAL; + break; + + default: + return -EOPNOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + return 0; +} + +static int axp192_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + int ret; + unsigned int cfg; + + for (cfg = 0; cfg < num_configs; ++cfg) { + switch (pinconf_to_config_param(configs[cfg])) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_DOWN: + continue; + default: + return -EOPNOTSUPP; + } + } + + for (cfg = 0; cfg < num_configs; ++cfg) { + switch (pinconf_to_config_param(configs[cfg])) { + case PIN_CONFIG_BIAS_DISABLE: + ret = axp192_pinconf_set_pull_down(pctldev, pin, 0); + if (ret) + return ret; + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + ret = axp192_pinconf_set_pull_down(pctldev, pin, 1); + if (ret) + return ret; + break; + + default: + /* unreachable */ + break; + } + } + + return 0; +} + +static const struct pinconf_ops axp192_conf_ops = { + .is_generic = true, + .pin_config_get = axp192_pinconf_get, + .pin_config_set = axp192_pinconf_set, + .pin_config_group_get = axp192_pinconf_get, + .pin_config_group_set = axp192_pinconf_set, +}; + +static int axp192_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset, u8 config) +{ + struct axp192_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); + const struct axp192_pctl_reg_info *reginfo = &pctl->desc->ctrl_regs[offset]; + unsigned int regval = config << (ffs(reginfo->mask) - 1); + + return regmap_update_bits(pctl->regmap, reginfo->reg, reginfo->mask, regval); +} + +static int axp192_pmx_func_cnt(struct pinctrl_dev *pctldev) +{ + struct axp192_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->desc->nfunctions; +} + +static const char *axp192_pmx_func_name(struct pinctrl_dev *pctldev, unsigned int selector) +{ + struct axp192_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->desc->functions[selector].name; +} + +static int axp192_pmx_func_groups(struct pinctrl_dev *pctldev, unsigned int selector, + const char * const **groups, unsigned int *num_groups) +{ + struct axp192_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *groups = pctl->desc->functions[selector].groups; + *num_groups = pctl->desc->functions[selector].ngroups; + + return 0; +} + +static int axp192_pmx_set_mux(struct pinctrl_dev *pctldev, + unsigned int function, unsigned int group) +{ + struct axp192_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); + const u8 *muxvals = pctl->desc->functions[function].muxvals; + + if (muxvals[group] == (u8)-1) + return -EINVAL; + + /* + * Switching to LDO or PWM function will enable LDO/PWM output, so it's + * better to ignore these requests and let the regulator or PWM drivers + * handle muxing to avoid interfering with them. + */ + if (function == AXP192_FUNC_LDO || function == AXP192_FUNC_PWM) + return 0; + + return axp192_pmx_set(pctldev, group, muxvals[group]); +} + +static int axp192_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset, bool input) +{ + struct axp192_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); + const u8 *muxvals = input ? pctl->desc->functions[AXP192_FUNC_INPUT].muxvals + : pctl->desc->functions[AXP192_FUNC_OUTPUT].muxvals; + + return axp192_pmx_set(pctldev, offset, muxvals[offset]); +} + +static const struct pinmux_ops axp192_pmx_ops = { + .get_functions_count = axp192_pmx_func_cnt, + .get_function_name = axp192_pmx_func_name, + .get_function_groups = axp192_pmx_func_groups, + .set_mux = axp192_pmx_set_mux, + .gpio_set_direction = axp192_pmx_gpio_set_direction, + .strict = true, +}; + +static int axp192_groups_cnt(struct pinctrl_dev *pctldev) +{ + struct axp192_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->desc->npins; +} + +static const char *axp192_group_name(struct pinctrl_dev *pctldev, unsigned int selector) +{ + struct axp192_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); + + return pctl->desc->pins[selector].name; +} + +static int axp192_group_pins(struct pinctrl_dev *pctldev, unsigned int selector, + const unsigned int **pins, unsigned int *num_pins) +{ + struct axp192_pctl *pctl = pinctrl_dev_get_drvdata(pctldev); + + *pins = &pctl->desc->pins[selector].number; + *num_pins = 1; + + return 0; +} + +static const struct pinctrl_ops axp192_pctrl_ops = { + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinconf_generic_dt_free_map, + .get_groups_count = axp192_groups_cnt, + .get_group_name = axp192_group_name, + .get_group_pins = axp192_group_pins, +}; + +static int axp192_pctl_probe(struct platform_device *pdev) +{ + struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent); + struct axp192_pctl *pctl; + struct pinctrl_desc *pctrl_desc; + int ret, i; + + if (!of_device_is_available(pdev->dev.of_node)) + return -ENODEV; + + if (!axp20x) { + dev_err(&pdev->dev, "Parent drvdata not set\n"); + return -EINVAL; + } + + pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); + if (!pctl) + return -ENOMEM; + + pctl->desc = of_device_get_match_data(&pdev->dev); + pctl->regmap = axp20x->regmap; + pctl->dev = &pdev->dev; + + pctl->chip.base = -1; + pctl->chip.can_sleep = true; + pctl->chip.request = gpiochip_generic_request; + pctl->chip.free = gpiochip_generic_free; + pctl->chip.parent = &pdev->dev; + pctl->chip.label = dev_name(&pdev->dev); + pctl->chip.owner = THIS_MODULE; + pctl->chip.get = axp192_gpio_get; + pctl->chip.get_direction = axp192_gpio_get_direction; + pctl->chip.set = axp192_gpio_set; + pctl->chip.direction_input = axp192_gpio_direction_input; + pctl->chip.direction_output = axp192_gpio_direction_output; + pctl->chip.to_irq = axp192_gpio_to_irq; + pctl->chip.ngpio = pctl->desc->npins; + + pctl->irqs = devm_kcalloc(&pdev->dev, pctl->desc->npins, sizeof(int), GFP_KERNEL); + if (!pctl->irqs) + return -ENOMEM; + + for (i = 0; i < pctl->desc->npins; ++i) { + ret = platform_get_irq_byname_optional(pdev, pctl->desc->pins[i].name); + if (ret > 0) + pctl->irqs[i] = regmap_irq_get_virq(axp20x->regmap_irqc, ret); + } + + platform_set_drvdata(pdev, pctl); + + pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL); + if (!pctrl_desc) + return -ENOMEM; + + pctrl_desc->name = dev_name(&pdev->dev); + pctrl_desc->owner = THIS_MODULE; + pctrl_desc->pins = pctl->desc->pins; + pctrl_desc->npins = pctl->desc->npins; + pctrl_desc->pctlops = &axp192_pctrl_ops; + pctrl_desc->pmxops = &axp192_pmx_ops; + pctrl_desc->confops = &axp192_conf_ops; + + pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl); + if (IS_ERR(pctl->pctl_dev)) { + dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); + return PTR_ERR(pctl->pctl_dev); + } + + ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl); + if (ret) { + dev_err(&pdev->dev, "Failed to register GPIO chip\n"); + return ret; + } + + ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev), + pctl->desc->pins->number, + pctl->desc->pins->number, + pctl->desc->npins); + if (ret) { + dev_err(&pdev->dev, "failed to add pin range\n"); + return ret; + } + + dev_info(&pdev->dev, "AXP192 pinctrl and GPIO driver loaded\n"); + + return 0; +} + +static const struct of_device_id axp192_pctl_match[] = { + { .compatible = "x-powers,axp192-gpio", .data = &axp192_data, }, + { } +}; +MODULE_DEVICE_TABLE(of, axp192_pctl_match); + +static struct platform_driver axp192_pctl_driver = { + .probe = axp192_pctl_probe, + .driver = { + .name = "axp192-gpio", + .of_match_table = axp192_pctl_match, + }, +}; + +module_platform_driver(axp192_pctl_driver); + +MODULE_AUTHOR("Aidan MacDonald "); +MODULE_DESCRIPTION("AXP192 PMIC pinctrl and GPIO driver"); +MODULE_LICENSE("GPL");