From patchwork Thu Jun 2 01:33:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 578076 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp103904max; Wed, 1 Jun 2022 18:36:14 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyBcHbIL9PNvIS355lbF8piAxl6E58Xk+1uOzWZ+TRfFLHJJxL/8D5s0cMV01FFb8VwiUyx X-Received: by 2002:a05:622a:1895:b0:304:8024:332d with SMTP id v21-20020a05622a189500b003048024332dmr2085242qtc.682.1654133774368; Wed, 01 Jun 2022 18:36:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654133774; cv=none; d=google.com; s=arc-20160816; b=HXOjryNQcdzae/rQ/qMPDOIeV6qfefVBv66b0jgmFTiG+8lODt2pSaTO1hx3hdAZVI osOvGlgTQM/0TR3/iRBtftpfoJ4ZaduCTIW9FH+IIXeR+wpv7Vi7QxRy9nG5r5xwkg7C ieS1UOalyOTS705ShwinGsTBDGqKc7+mq/awNaLWPvEriT0Am2WS3bjrYpNcpVAqQ1b7 Ejjkx3duvL7bfbDNh4X8N0bW+ir6pPu8ThLwk21zAPw3kXg31VavQjTwugSBGQ3pD6mr y4xt2fWO5ulsuD3Tmuz0/g++VPHMUKm3wdFq/ggsbN4QQ8KFaiPCF7A9meNm/A7Y7apn 2WEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=v6GsMd9l2dAfQx+Uj+qJ1gCQp2pHPy4DQInBPdc5TCM=; b=JHXKVtFjaRn2tc3HYpC7bygGRn4dagj5vNWSYtdZHSMrT6hRyHHALDGLWb5YOp/nM1 lb/216wNDyMPPV+HlU8nVEeHRUaQiJdVlhqcLkpyuFVNMJxSPhOzaMyvmLjilN3e5iUP tx4DIW7qcaLqQ7yaBu11AGmndaVI0ern2MLujqI+RLzHIJoKXsSkG+dKrv9FAUCeIXYN MzW4eNOHVvQUq0H90Laxm9H64ybXgamvk+tFMj9wheCGtglx0TccYCQ5H8IWwX38rHDc SRvLFZ0B1V3c8JxVPFO51T5SEFakaM0Px28mkibTOSiJw1VYlzU1NUth9a5+gfFaSODB Q7cw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Qg8/PLu8"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:1eca:8ee3:9269:e00c]) by smtp.gmail.com with ESMTPSA id l191-20020a6391c8000000b003fc5b1db26fsm1962875pge.52.2022.06.01.18.34.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 18:34:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH v6 01/17] target/m68k: Raise the TRAPn exception with the correct pc Date: Wed, 1 Jun 2022 18:33:45 -0700 Message-Id: <20220602013401.303699-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602013401.303699-1-richard.henderson@linaro.org> References: <20220602013401.303699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rather than adjust the PC in all of the consumers, raise the exception with the correct PC in the first place. Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- linux-user/m68k/cpu_loop.c | 1 - target/m68k/op_helper.c | 9 --------- target/m68k/translate.c | 2 +- 3 files changed, 1 insertion(+), 11 deletions(-) diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index d1bf8548b7..56417f7401 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -56,7 +56,6 @@ void cpu_loop(CPUM68KState *env) { abi_long ret; n = env->dregs[0]; - env->pc += 2; ret = do_syscall(env, n, env->dregs[1], diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 8decc61240..d30f988ae0 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -217,11 +217,6 @@ static void cf_interrupt_all(CPUM68KState *env, int is_hw) cpu_loop_exit(cs); return; } - if (cs->exception_index >= EXCP_TRAP0 - && cs->exception_index <= EXCP_TRAP15) { - /* Move the PC after the trap instruction. */ - retaddr += 2; - } } vector = cs->exception_index << 2; @@ -304,10 +299,6 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) /* Return from an exception. */ m68k_rte(env); return; - case EXCP_TRAP0 ... EXCP_TRAP15: - /* Move the PC after the trap instruction. */ - retaddr += 2; - break; } } diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 4026572ed8..6d6d026e3c 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4860,7 +4860,7 @@ DISAS_INSN(wdebug) DISAS_INSN(trap) { - gen_exception(s, s->base.pc_next, EXCP_TRAP0 + (insn & 0xf)); + gen_exception(s, s->pc, EXCP_TRAP0 + (insn & 0xf)); } static void gen_load_fcr(DisasContext *s, TCGv res, int reg) From patchwork Thu Jun 2 01:33:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 578078 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp104679max; Wed, 1 Jun 2022 18:37:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwmHAis0NlszmGygxrLsYOoxNhyQjIZ6ewhrBQM2VQSDEdhg88WVnS4Xyn84TCWDlJGsZCA X-Received: by 2002:ac8:6ed0:0:b0:2f9:4564:97b5 with SMTP id f16-20020ac86ed0000000b002f9456497b5mr1982858qtv.669.1654133872414; Wed, 01 Jun 2022 18:37:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654133872; cv=none; d=google.com; s=arc-20160816; b=yEcOTPnQ92vdfXSTw0RdGs1lKpG6rNaZDRTnzmlZIVx6ApG9CIf8ScVfnC2QySq4rG 0GRpzqjgPapUVOYrt/cltoNf6F/fEVSkN3Zzs6gIEMfGW30Ta7tZf4wPj0xU2LeCTS7d yHCX5jMcni9DeDjYEQI+hY8bsLPq0lytNonrw2SsecffZgI8Q9RMSbFKKNaCvcp8lxhK nPey1urYFFKd3mKNdTAKvKuYTXKgTJqsQXvtD1xUt+6+8eUeCU/Hs1ua47EeZxbPXlJD Nxkni6yV6s5Q8CskrNVV7HXpBpN5klcwxrNZqwqjJeoEXR1/ahbDU0ejGBgvnSPlFhZF IM7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hV+IA21ry8VojR25e1IAEE42j7p287jopA93G1Fi9U8=; b=Oe6TBic5WQjMtGSDJMorMnnbMuy/fuYPz4zWDb0114ll/Ra6Hhr/fqQQToUmgqywuu wYqETjBEnifVskFVF8hdoquKPzgad0BwfMgNuJdoPnNp7lToW5K+fqPntTVX4Z+YWPhJ wfMWIfQKTtjxuQbWy2sSTgbHFr6FD0ViYAfqAt0vwctP2/4xFo9cIzRdbZiwGF03dJcJ usMak/VkZU+I68gX30ybB/DCOIzPQjKFvrLD2njog3VS3NEKBv2Kw72GpjFbRYmwpj9F IhhzsBiQHWBppQiTZpyM7mqQlhZsHQgWgCw/2gzjgkkptLufj6eBQscrKBKC0D1bEI5Y ZQnA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ovgoZ/5L"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:1eca:8ee3:9269:e00c]) by smtp.gmail.com with ESMTPSA id l191-20020a6391c8000000b003fc5b1db26fsm1962875pge.52.2022.06.01.18.34.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 18:34:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v6 02/17] target/m68k: Switch over exception type in m68k_interrupt_all Date: Wed, 1 Jun 2022 18:33:46 -0700 Message-Id: <20220602013401.303699-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602013401.303699-1-richard.henderson@linaro.org> References: <20220602013401.303699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Replace an if ladder with a switch for clarity. Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/m68k/op_helper.c | 49 +++++++++++++++++++++++++---------------- 1 file changed, 30 insertions(+), 19 deletions(-) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index d30f988ae0..2b94a6ec84 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -333,7 +333,8 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) sp &= ~1; } - if (cs->exception_index == EXCP_ACCESS) { + switch (cs->exception_index) { + case EXCP_ACCESS: if (env->mmu.fault) { cpu_abort(cs, "DOUBLE MMU FAULT\n"); } @@ -391,29 +392,39 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) "ssw: %08x ea: %08x sfc: %d dfc: %d\n", env->mmu.ssw, env->mmu.ar, env->sfc, env->dfc); } - } else if (cs->exception_index == EXCP_ADDRESS) { + break; + + case EXCP_ADDRESS: do_stack_frame(env, &sp, 2, oldsr, 0, retaddr); - } else if (cs->exception_index == EXCP_ILLEGAL || - cs->exception_index == EXCP_DIV0 || - cs->exception_index == EXCP_CHK || - cs->exception_index == EXCP_TRAPCC || - cs->exception_index == EXCP_TRACE) { + break; + + case EXCP_ILLEGAL: + case EXCP_DIV0: + case EXCP_CHK: + case EXCP_TRAPCC: + case EXCP_TRACE: /* FIXME: addr is not only env->pc */ do_stack_frame(env, &sp, 2, oldsr, env->pc, retaddr); - } else if (is_hw && oldsr & SR_M && - cs->exception_index >= EXCP_SPURIOUS && - cs->exception_index <= EXCP_INT_LEVEL_7) { - do_stack_frame(env, &sp, 0, oldsr, 0, retaddr); - oldsr = sr; - env->aregs[7] = sp; - cpu_m68k_set_sr(env, sr &= ~SR_M); - sp = env->aregs[7]; - if (!m68k_feature(env, M68K_FEATURE_UNALIGNED_DATA)) { - sp &= ~1; + break; + + case EXCP_SPURIOUS ... EXCP_INT_LEVEL_7: + if (is_hw && oldsr & SR_M) { + do_stack_frame(env, &sp, 0, oldsr, 0, retaddr); + oldsr = sr; + env->aregs[7] = sp; + cpu_m68k_set_sr(env, sr &= ~SR_M); + sp = env->aregs[7]; + if (!m68k_feature(env, M68K_FEATURE_UNALIGNED_DATA)) { + sp &= ~1; + } + do_stack_frame(env, &sp, 1, oldsr, 0, retaddr); + break; } - do_stack_frame(env, &sp, 1, oldsr, 0, retaddr); - } else { + /* fall through */ + + default: do_stack_frame(env, &sp, 0, oldsr, 0, retaddr); + break; } env->aregs[7] = sp; From patchwork Thu Jun 2 01:33:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 578079 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp106459max; Wed, 1 Jun 2022 18:40:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy2g0nIELsMq0IIqZkQnGg2Ld2Rrfkea/NQVdBO3Z8lgjahmDKthPbwVY6S/DN3mpNt1i64 X-Received: by 2002:a05:620a:40d1:b0:6a5:b4a3:dfbe with SMTP id g17-20020a05620a40d100b006a5b4a3dfbemr2025654qko.340.1654134053223; Wed, 01 Jun 2022 18:40:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654134053; cv=none; d=google.com; s=arc-20160816; b=icm2s/3hOyMP2YTXz4a+FtsQ1MOrYBdDtZpOJGApEl3J/5wgfb3GA2d975zQ9BxIKz 51LcyPX7WuaVyYMPlgkjTKegtSQlGAGKMLQyK9D9T8PC13Y+TmIakvWDXQW7l0nnuK3i LwlPC4BNNXMOE+DNKO2vVrmZRU6jj2uqucVOEwLp2dfR+7uAysQlY/hCCt6zlWd1ATSh 6BHWCQorGQEE1wjQEjQzIuzHzHnE6naQQaQJCWddvU7Yeuhy3Lh+OuYImiRzTN54R4yx pxXmBwqmp9ZONArZLjgf8oMDdH2EYnBzG8uMlxefMt27D3q4WBQbEVJCI8TbWl+E1Glg N7iQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=mCzaU+JrOI2uB5gjGXQ6lDaHwnlMpGfIPzqc07MdKqM=; b=NAhGMWWmRCm9Jh7GA8iZUJvXhqMJsC7Suzrgj8qVw6+nx3djJzY7hG0N5G9E/3OAd1 eHxVFby5qr4f1U2mxJJdEoS4Mzqtk+ZFB/E7E7mMcQteb7h52/aG5+s+0qDcB9keqAvL adMU6Z1jSX4b8fukmmvpEAy4z07bPoTHFRrO4xMd98cRmYHE5FqoY0CJZ6CVLDJD+I75 TFtE2eA0RvtvVUIxd8jQfVSt/XUb9VmEgny+lrYREbyumAv+c21PF55pejPvDnreRmem gHQdktaoeY5l71ctauYEL5i+HUWH48JJNi4r+ALBMxIUVoMMTbcOUJqoC8nlWtsI1PLt 24PA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eJrzavF7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:1eca:8ee3:9269:e00c]) by smtp.gmail.com with ESMTPSA id l191-20020a6391c8000000b003fc5b1db26fsm1962875pge.52.2022.06.01.18.34.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 18:34:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v6 03/17] target/m68k: Fix coding style in m68k_interrupt_all Date: Wed, 1 Jun 2022 18:33:47 -0700 Message-Id: <20220602013401.303699-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602013401.303699-1-richard.henderson@linaro.org> References: <20220602013401.303699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add parenthesis around & vs &&. Remove assignment to sr in function call argument -- note that sr is unused after the call, so the assignment was never needed, only the result of the & expression. Suggested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/op_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 2b94a6ec84..0f41c2dce3 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -408,11 +408,11 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) break; case EXCP_SPURIOUS ... EXCP_INT_LEVEL_7: - if (is_hw && oldsr & SR_M) { + if (is_hw && (oldsr & SR_M)) { do_stack_frame(env, &sp, 0, oldsr, 0, retaddr); oldsr = sr; env->aregs[7] = sp; - cpu_m68k_set_sr(env, sr &= ~SR_M); + cpu_m68k_set_sr(env, sr & ~SR_M); sp = env->aregs[7]; if (!m68k_feature(env, M68K_FEATURE_UNALIGNED_DATA)) { sp &= ~1; From patchwork Thu Jun 2 01:33:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 578082 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp106952max; Wed, 1 Jun 2022 18:41:57 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyET6o6mrPU9CCql/GcbiwQE+8D/WAqx3TJZEb3VdTlgjIGfqQdALPKWZ/q4WoONBvaK3MN X-Received: by 2002:a05:620a:404b:b0:6a4:8244:1b62 with SMTP id i11-20020a05620a404b00b006a482441b62mr1741895qko.484.1654134117625; Wed, 01 Jun 2022 18:41:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654134117; cv=none; d=google.com; s=arc-20160816; b=fM8btkgfp3blYNbi5wxvV+Reixv1N++Ja+CotHYB2DvGMfMXxj6mYqfc9T+VhYJtrr 58VIbCQmKbuhQJdbdtlAnoifuCBf37m7Ap1taLuHo/vAmZiqBD0uqsmTm7yYWCs+mPH5 mAVkDV8lxkIcA3RqqVq7E/nCGbi1tltrQfcocgKko6VdjYXh1wusazDz6rUbZM0IrMtH Xpu+gAbUa60mrpMDSgqf/5058y8XOI5ssYi6asJFG3HdQxW8rWX46TsxHQswSvWT32qf jBw6Yrd5IySEebQoAj6WIo7vVYXShCKjyqnKgqYiHtJgHUzSmqhjF/sK7t9L1celkBVZ 52Eg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=P8QVHsssV/N9S00mQXjYBPgFpjBb96NXM+kaVdZ/lRE=; b=J4zSKbRSZBikejwmF35G/K9fgc/QVqT0U8dLhuVX+Ha87EiklShxeUedcPrYnIZnSx ZDzfT+QQ4XnA1BeJxb3kP0qacQ8sOwmmtMgquQBfctU/DuRDfI7nek/T1Cdd/Z6olWQf xOqTFJY9c2HIHnemeERih1chJO3T+Bxg1XzDbXihGxCngXENugHxM+jhuxb2aELDBMT2 AvAAnMDaD+2kydCZhBSIacpQ2Q9A7QOOpGyVZMpCrMziWr8TPSC29e0TVLvWhOrRH+JT W20uwks2Xaxt5diZMQRgflD9egaAg6/GlQDsxS65RJ1WhmGylEmjmH5ygQw78qFBemEx QP0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Hlsxl02a; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:1eca:8ee3:9269:e00c]) by smtp.gmail.com with ESMTPSA id l191-20020a6391c8000000b003fc5b1db26fsm1962875pge.52.2022.06.01.18.34.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 18:34:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH v6 04/17] linux-user/m68k: Handle EXCP_TRAP1 through EXCP_TRAP15 Date: Wed, 1 Jun 2022 18:33:48 -0700 Message-Id: <20220602013401.303699-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602013401.303699-1-richard.henderson@linaro.org> References: <20220602013401.303699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These are raised by guest instructions, and should not fall through into the default abort case. Signed-off-by: Richard Henderson --- linux-user/m68k/cpu_loop.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index 56417f7401..12e5d9cd53 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -75,7 +75,11 @@ void cpu_loop(CPUM68KState *env) case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; + case EXCP_TRAP0 + 1 ... EXCP_TRAP0 + 14: + force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLTRP, env->pc); + break; case EXCP_DEBUG: + case EXCP_TRAP15: force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc); break; case EXCP_ATOMIC: From patchwork Thu Jun 2 01:33:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 578083 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp108097max; Wed, 1 Jun 2022 18:44:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwGXef+tWPKn/QsP3kJaAYoEtjO7Gc9iWZm4TAq1gm1ieQXlazsHLykHSp72yqvTbUIwNlf X-Received: by 2002:a05:620a:191e:b0:6a5:88e5:2020 with SMTP id bj30-20020a05620a191e00b006a588e52020mr1705657qkb.65.1654134278348; Wed, 01 Jun 2022 18:44:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654134278; cv=none; d=google.com; s=arc-20160816; b=mMuX5kCRgtU6zHkcD1Nh1eE7ZfUuijshUboRckaK0k65GK2b7zVEZOiFTGVQEVtC2q 3ZGKsizX7lehb9OyUhj2MZwr/IcqQ1bdPALMsrx79GvY6Lwktj1EtMT6NR8k6s1pOdzS sDUeqoynsZ/QZ1rzIEPBBS91DJSY0vx2gYA2ATm+xbKE3S/Zj5xDcZ5j39zyddgDskZ0 t+caKU+/TDcwU0NI6SNszVfw4oQ7a3xfW2ZKNZPQiVY3axUuJsRNYlRrfK1o0kz3XiLK ys/o4scEOCR2dMm1k2gFKovMAPi8Bf8j9rlkr3q82jT6cuzU/aBGCxI0xMCvL0frEX6J 7PyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=dBQmcYvQNWemNoz94qCXnnbynO5dcM+A32yDVQduyko=; b=aOnu4ZBiUujY9tRGUik+wFlg9ZCmRULb499nBj9uMqUn3B1DisnbP9IsCxU0N2YGcY BrzoJVAhHmfrsQSbNCzeWevmw6WcEZsqTO+XWQIe44pR+kopnqtmZ9zRfo1p1gAbQyPq PO4ZnLBazWfFI6cIXdRgji9nqWozGgPTL5kW7sVqQJHXsFHCCnN75JDDMTniqbDsyOdL dLuUpFFD9B2DQchEDDO3SydsfEjso7Qm6W4/nmKBTw142lYyueNfc44lmkngK83DlKyy j9/JFpzTTCgQLLCLhqPk4pVKQ77NsEZ71uyhmiCctINUl8rakERLRfKmKrO51nxCYXWR Xm7Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Yk3723jL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:1eca:8ee3:9269:e00c]) by smtp.gmail.com with ESMTPSA id l191-20020a6391c8000000b003fc5b1db26fsm1962875pge.52.2022.06.01.18.34.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 18:34:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v6 05/17] target/m68k: Remove retaddr in m68k_interrupt_all Date: Wed, 1 Jun 2022 18:33:49 -0700 Message-Id: <20220602013401.303699-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602013401.303699-1-richard.henderson@linaro.org> References: <20220602013401.303699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The only value this variable holds is now env->pc. Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/m68k/op_helper.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 0f41c2dce3..777869790b 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -287,12 +287,9 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) { CPUState *cs = env_cpu(env); uint32_t sp; - uint32_t retaddr; uint32_t vector; uint16_t sr, oldsr; - retaddr = env->pc; - if (!is_hw) { switch (cs->exception_index) { case EXCP_RTE: @@ -385,7 +382,7 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) sp -= 4; cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0); - do_stack_frame(env, &sp, 7, oldsr, 0, retaddr); + do_stack_frame(env, &sp, 7, oldsr, 0, env->pc); env->mmu.fault = false; if (qemu_loglevel_mask(CPU_LOG_INT)) { qemu_log(" " @@ -395,7 +392,7 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) break; case EXCP_ADDRESS: - do_stack_frame(env, &sp, 2, oldsr, 0, retaddr); + do_stack_frame(env, &sp, 2, oldsr, 0, env->pc); break; case EXCP_ILLEGAL: @@ -404,12 +401,12 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) case EXCP_TRAPCC: case EXCP_TRACE: /* FIXME: addr is not only env->pc */ - do_stack_frame(env, &sp, 2, oldsr, env->pc, retaddr); + do_stack_frame(env, &sp, 2, oldsr, env->pc, env->pc); break; case EXCP_SPURIOUS ... EXCP_INT_LEVEL_7: if (is_hw && (oldsr & SR_M)) { - do_stack_frame(env, &sp, 0, oldsr, 0, retaddr); + do_stack_frame(env, &sp, 0, oldsr, 0, env->pc); oldsr = sr; env->aregs[7] = sp; cpu_m68k_set_sr(env, sr & ~SR_M); @@ -417,13 +414,13 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) if (!m68k_feature(env, M68K_FEATURE_UNALIGNED_DATA)) { sp &= ~1; } - do_stack_frame(env, &sp, 1, oldsr, 0, retaddr); + do_stack_frame(env, &sp, 1, oldsr, 0, env->pc); break; } /* fall through */ default: - do_stack_frame(env, &sp, 0, oldsr, 0, retaddr); + do_stack_frame(env, &sp, 0, oldsr, 0, env->pc); break; } From patchwork Thu Jun 2 01:33:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 578086 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp110405max; Wed, 1 Jun 2022 18:49:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxOxktC5QDiXMio9VG9wnblZ0N2wesDEIAINVei1+zg0o+OZf0brLdbr1KKe9VBWSdfIVuH X-Received: by 2002:ac8:58ce:0:b0:304:b4e1:a892 with SMTP id u14-20020ac858ce000000b00304b4e1a892mr2043317qta.507.1654134581905; Wed, 01 Jun 2022 18:49:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654134581; cv=none; d=google.com; s=arc-20160816; b=ddF6hmhfsvOfCSVowf6gaiT7pWqxVeJ3Top75CuWCXRDLRp34fhUYuUtCBq3OLlwps Ur9P6XVU0MVe4c3yA0v0BAg1xDV47iOR0h9l9aKRFUftITwMpIVaIRn4g/I4IhCT4X9L mPocwK00q9zNYjCzVBflzbvULqYEA7juQub9msSEosASfXsavnTelqa0uc5qh+d8GtpV 3sdEtf3uwUJrx7jIwHrqz/+0wCVZQRk2dqRtak4SBJyc2mSffXvBjluiXhl2FBEevfP0 jlZikwo9VSmQtbxcs17hiys2Xuwgz8AW5w/XYQ6ZNSsSeVdEmW1cA3m9pVhLUU1oJgzy 31CQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=lTUaM+lqbn8KxvXwj+n9JX47C53ZG33aTbTDGh5Ahv4=; b=ef6SF4Dgfbkqb/7+eJyCqFd/nAX2DqXXxJwMSqvqAF3a8hK3NyrQS3z7gWxAjRPMkQ SLX+pSZ5fjpMW9BVhmUDGVI1aIm06pqprfiv9TXPJbWbbu08Aqr2pPj2Jnr+wtHmt3kQ MViFl2n2JCd1qBIcp4fYHYnsPTE3v/sSR9fgy+IcAdBHSFHR7kh4zT+/2wmUARnVSRe3 mtxkP2cMoVZb+bOn5YgQfLPRjvdTDrODouYV25J8KAWyZfAGV7nv+Rle1O5ErHf/SPUX VAMaBWAzIMaSkShunOKpj9E+zQHklx9o0TpXY3yEDr6aiJpCgAML7F46ZAX0kqo1S3kY iD/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TMupXwDw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:1eca:8ee3:9269:e00c]) by smtp.gmail.com with ESMTPSA id l191-20020a6391c8000000b003fc5b1db26fsm1962875pge.52.2022.06.01.18.34.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 18:34:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH v6 06/17] target/m68k: Fix address argument for EXCP_CHK Date: Wed, 1 Jun 2022 18:33:50 -0700 Message-Id: <20220602013401.303699-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602013401.303699-1-richard.henderson@linaro.org> References: <20220602013401.303699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" According to the M68040 Users Manual, section 8.4.3, Six word stack frame (format 2), CHK, CHK2 (and others) are supposed to record the next insn in PC and the address of the trapping instruction in ADDRESS. Create a raise_exception_format2 function to centralize recording of the trapping pc in mmu.ar, plus advancing to the next insn. Update m68k_interrupt_all to pass mmu.ar to do_stack_frame. Update cpu_loop to pass mmu.ar to siginfo.si_addr, as the kernel does in trap_c(). Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/cpu.h | 6 +++++ linux-user/m68k/cpu_loop.c | 2 +- target/m68k/op_helper.c | 54 ++++++++++++++++++++------------------ 3 files changed, 36 insertions(+), 26 deletions(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 9b3bf7a448..558c3c67d6 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -122,6 +122,12 @@ typedef struct CPUArchState { /* MMU status. */ struct { + /* + * Holds the "address" value in between raising an exception + * and creation of the exception stack frame. + * Used for both Format 7 exceptions (Access, i.e. mmu) + * and Format 2 exceptions (chk, div0, trapcc, etc). + */ uint32_t ar; uint32_t ssw; /* 68040 */ diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index 12e5d9cd53..e24d17e180 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -47,7 +47,7 @@ void cpu_loop(CPUM68KState *env) force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc); break; case EXCP_CHK: - force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, env->pc); + force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, env->mmu.ar); break; case EXCP_DIV0: force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->pc); diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 777869790b..750d65576f 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -397,13 +397,16 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) case EXCP_ILLEGAL: case EXCP_DIV0: - case EXCP_CHK: case EXCP_TRAPCC: case EXCP_TRACE: /* FIXME: addr is not only env->pc */ do_stack_frame(env, &sp, 2, oldsr, env->pc, env->pc); break; + case EXCP_CHK: + do_stack_frame(env, &sp, 2, oldsr, env->mmu.ar, env->pc); + break; + case EXCP_SPURIOUS ... EXCP_INT_LEVEL_7: if (is_hw && (oldsr & SR_M)) { do_stack_frame(env, &sp, 0, oldsr, 0, env->pc); @@ -548,6 +551,29 @@ void HELPER(raise_exception)(CPUM68KState *env, uint32_t tt) raise_exception(env, tt); } +G_NORETURN static void +raise_exception_format2(CPUM68KState *env, int tt, int ilen, uintptr_t raddr) +{ + CPUState *cs = env_cpu(env); + + cs->exception_index = tt; + + /* Recover PC and CC_OP for the beginning of the insn. */ + cpu_restore_state(cs, raddr, true); + + /* Flags are current in env->cc_*, or are undefined. */ + env->cc_op = CC_OP_FLAGS; + + /* + * Remember original pc in mmu.ar, for the Format 2 stack frame. + * Adjust PC to end of the insn. + */ + env->mmu.ar = env->pc; + env->pc += ilen; + + cpu_loop_exit(cs); +} + void HELPER(divuw)(CPUM68KState *env, int destr, uint32_t den) { uint32_t num = env->dregs[destr]; @@ -1065,18 +1091,7 @@ void HELPER(chk)(CPUM68KState *env, int32_t val, int32_t ub) env->cc_c = 0 <= ub ? val < 0 || val > ub : val > ub && val < 0; if (val < 0 || val > ub) { - CPUState *cs = env_cpu(env); - - /* Recover PC and CC_OP for the beginning of the insn. */ - cpu_restore_state(cs, GETPC(), true); - - /* flags have been modified by gen_flush_flags() */ - env->cc_op = CC_OP_FLAGS; - /* Adjust PC to end of the insn. */ - env->pc += 2; - - cs->exception_index = EXCP_CHK; - cpu_loop_exit(cs); + raise_exception_format2(env, EXCP_CHK, 2, GETPC()); } } @@ -1097,17 +1112,6 @@ void HELPER(chk2)(CPUM68KState *env, int32_t val, int32_t lb, int32_t ub) env->cc_c = lb <= ub ? val < lb || val > ub : val > ub && val < lb; if (env->cc_c) { - CPUState *cs = env_cpu(env); - - /* Recover PC and CC_OP for the beginning of the insn. */ - cpu_restore_state(cs, GETPC(), true); - - /* flags have been modified by gen_flush_flags() */ - env->cc_op = CC_OP_FLAGS; - /* Adjust PC to end of the insn. */ - env->pc += 4; - - cs->exception_index = EXCP_CHK; - cpu_loop_exit(cs); + raise_exception_format2(env, EXCP_CHK, 4, GETPC()); } } From patchwork Thu Jun 2 01:33:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 578080 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp106463max; Wed, 1 Jun 2022 18:40:53 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx32Ezd0wbRP+0nyjRsSsn7xC3vVtcMp16hsrr6YOwBHP5pZ9SnLec7AIEFt3X6XYcUP6od X-Received: by 2002:a37:9b55:0:b0:6a3:4ac4:1594 with SMTP id d82-20020a379b55000000b006a34ac41594mr1938145qke.164.1654134053492; Wed, 01 Jun 2022 18:40:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654134053; cv=none; d=google.com; s=arc-20160816; b=DP3Oi2ihokWLzgyFOecqoOIa9nw5p8cxHbeWhJmV/LzQGWz03iV5zk4OmhyNgGFuBb jFn49RRRiYu46HBduTRCJNUhRz7wj2J7AL6l/h9OjrljSi8cXohkKLdD+rn0FOfj67dF WzwlaiWF9CfIRw4UOOg+WMRZej1QI7glTNuL+hu05Z7Zqy1eKCJzRic6ZrR/vkN9oivh ztEF0LkvcuNDpfmQ+fdiaD44o+WegLsUctWKLvC2Y9A7HgfJ+uyfOWpZprs33CW8x6x2 nVsRII3r1vrvcy3jpfHZXjjIcUlNV8fjFY+LYCbXN+LZ0QDE/xqA5vMV5T/7bKAbnaGv UC6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9h8O/PKdXL0KvuNK2v2gIq3YV3vKmkNQsNhTF8q3vR8=; b=lFiJkPGAOCq6yI2ibSxNGSJVd9E0+lAcI/DBAI2teeiC4Q15w4tp7LHZN8aRfOOKC/ +CZSfiUGkBK1m+GuilbIujo05tTXPrkoGmqpNH+RsC4RRS9qnsKvwL1NzaUh3suznoSj SpXly+JDWXZwStx5GrpvJKpe2ASzSH4RaT7rx/AsPDJNLhM5+IWbUjL2B7l6NiWAaZ8w EJfqobcNEt8U5EWmSKuoLxQJtRC04QtYYl0Sg7qbkZMiAybIbcmMlMOpA/VnlMG3Zie7 mcFeVcwwCOhnvqJgl7HbtssroL1HdPVtVvf8VjLxSaQ5RaNKseEQ4R8gSAAiDG16bHV3 rQqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M27HBWjA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:1eca:8ee3:9269:e00c]) by smtp.gmail.com with ESMTPSA id l191-20020a6391c8000000b003fc5b1db26fsm1962875pge.52.2022.06.01.18.34.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 18:34:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH v6 07/17] target/m68k: Fix pc, c flag, and address argument for EXCP_DIV0 Date: Wed, 1 Jun 2022 18:33:51 -0700 Message-Id: <20220602013401.303699-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602013401.303699-1-richard.henderson@linaro.org> References: <20220602013401.303699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" According to the M68040 Users Manual, section 8.4.3, Six word stack frame (format 2), Zero Div (and others) is supposed to record the next insn in PC and the address of the trapping instruction in ADDRESS. While the N, Z and V flags are documented to be undefine on DIV0, the C flag is documented as always cleared. Update helper_div* to take the instruction length as an argument and use raise_exception_format2. Hoist the reset of the C flag above the division by zero check. Update m68k_interrupt_all to pass mmu.ar to do_stack_frame. Update cpu_loop to pass mmu.ar to siginfo.si_addr, as the kernel does in trap_c(). Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/helper.h | 12 +++++----- linux-user/m68k/cpu_loop.c | 2 +- target/m68k/op_helper.c | 48 +++++++++++++++++++++++--------------- target/m68k/translate.c | 33 +++++++++++++------------- 4 files changed, 52 insertions(+), 43 deletions(-) diff --git a/target/m68k/helper.h b/target/m68k/helper.h index 0a6b4146f6..f016c4c1c2 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -1,12 +1,12 @@ DEF_HELPER_1(bitrev, i32, i32) DEF_HELPER_1(ff1, i32, i32) DEF_HELPER_FLAGS_2(sats, TCG_CALL_NO_RWG_SE, i32, i32, i32) -DEF_HELPER_3(divuw, void, env, int, i32) -DEF_HELPER_3(divsw, void, env, int, s32) -DEF_HELPER_4(divul, void, env, int, int, i32) -DEF_HELPER_4(divsl, void, env, int, int, s32) -DEF_HELPER_4(divull, void, env, int, int, i32) -DEF_HELPER_4(divsll, void, env, int, int, s32) +DEF_HELPER_4(divuw, void, env, int, i32, int) +DEF_HELPER_4(divsw, void, env, int, s32, int) +DEF_HELPER_5(divul, void, env, int, int, i32, int) +DEF_HELPER_5(divsl, void, env, int, int, s32, int) +DEF_HELPER_5(divull, void, env, int, int, i32, int) +DEF_HELPER_5(divsll, void, env, int, int, s32, int) DEF_HELPER_2(set_sr, void, env, i32) DEF_HELPER_3(cf_movec_to, void, env, i32, i32) DEF_HELPER_3(m68k_movec_to, void, env, i32, i32) diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index e24d17e180..6598bce3c4 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -50,7 +50,7 @@ void cpu_loop(CPUM68KState *env) force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, env->mmu.ar); break; case EXCP_DIV0: - force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->pc); + force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->mmu.ar); break; case EXCP_TRAP0: { diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 750d65576f..729ee0e934 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -396,7 +396,6 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) break; case EXCP_ILLEGAL: - case EXCP_DIV0: case EXCP_TRAPCC: case EXCP_TRACE: /* FIXME: addr is not only env->pc */ @@ -404,6 +403,7 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) break; case EXCP_CHK: + case EXCP_DIV0: do_stack_frame(env, &sp, 2, oldsr, env->mmu.ar, env->pc); break; @@ -574,18 +574,19 @@ raise_exception_format2(CPUM68KState *env, int tt, int ilen, uintptr_t raddr) cpu_loop_exit(cs); } -void HELPER(divuw)(CPUM68KState *env, int destr, uint32_t den) +void HELPER(divuw)(CPUM68KState *env, int destr, uint32_t den, int ilen) { uint32_t num = env->dregs[destr]; uint32_t quot, rem; + env->cc_c = 0; /* always cleared, even if div0 */ + if (den == 0) { - raise_exception_ra(env, EXCP_DIV0, GETPC()); + raise_exception_format2(env, EXCP_DIV0, ilen, GETPC()); } quot = num / den; rem = num % den; - env->cc_c = 0; /* always cleared, even if overflow */ if (quot > 0xffff) { env->cc_v = -1; /* @@ -601,18 +602,19 @@ void HELPER(divuw)(CPUM68KState *env, int destr, uint32_t den) env->cc_v = 0; } -void HELPER(divsw)(CPUM68KState *env, int destr, int32_t den) +void HELPER(divsw)(CPUM68KState *env, int destr, int32_t den, int ilen) { int32_t num = env->dregs[destr]; uint32_t quot, rem; + env->cc_c = 0; /* always cleared, even if overflow/div0 */ + if (den == 0) { - raise_exception_ra(env, EXCP_DIV0, GETPC()); + raise_exception_format2(env, EXCP_DIV0, ilen, GETPC()); } quot = num / den; rem = num % den; - env->cc_c = 0; /* always cleared, even if overflow */ if (quot != (int16_t)quot) { env->cc_v = -1; /* nothing else is modified */ @@ -629,18 +631,20 @@ void HELPER(divsw)(CPUM68KState *env, int destr, int32_t den) env->cc_v = 0; } -void HELPER(divul)(CPUM68KState *env, int numr, int regr, uint32_t den) +void HELPER(divul)(CPUM68KState *env, int numr, int regr, + uint32_t den, int ilen) { uint32_t num = env->dregs[numr]; uint32_t quot, rem; + env->cc_c = 0; /* always cleared, even if div0 */ + if (den == 0) { - raise_exception_ra(env, EXCP_DIV0, GETPC()); + raise_exception_format2(env, EXCP_DIV0, ilen, GETPC()); } quot = num / den; rem = num % den; - env->cc_c = 0; env->cc_z = quot; env->cc_n = quot; env->cc_v = 0; @@ -657,18 +661,20 @@ void HELPER(divul)(CPUM68KState *env, int numr, int regr, uint32_t den) } } -void HELPER(divsl)(CPUM68KState *env, int numr, int regr, int32_t den) +void HELPER(divsl)(CPUM68KState *env, int numr, int regr, + int32_t den, int ilen) { int32_t num = env->dregs[numr]; int32_t quot, rem; + env->cc_c = 0; /* always cleared, even if overflow/div0 */ + if (den == 0) { - raise_exception_ra(env, EXCP_DIV0, GETPC()); + raise_exception_format2(env, EXCP_DIV0, ilen, GETPC()); } quot = num / den; rem = num % den; - env->cc_c = 0; env->cc_z = quot; env->cc_n = quot; env->cc_v = 0; @@ -685,19 +691,21 @@ void HELPER(divsl)(CPUM68KState *env, int numr, int regr, int32_t den) } } -void HELPER(divull)(CPUM68KState *env, int numr, int regr, uint32_t den) +void HELPER(divull)(CPUM68KState *env, int numr, int regr, + uint32_t den, int ilen) { uint64_t num = deposit64(env->dregs[numr], 32, 32, env->dregs[regr]); uint64_t quot; uint32_t rem; + env->cc_c = 0; /* always cleared, even if overflow/div0 */ + if (den == 0) { - raise_exception_ra(env, EXCP_DIV0, GETPC()); + raise_exception_format2(env, EXCP_DIV0, ilen, GETPC()); } quot = num / den; rem = num % den; - env->cc_c = 0; /* always cleared, even if overflow */ if (quot > 0xffffffffULL) { env->cc_v = -1; /* @@ -720,19 +728,21 @@ void HELPER(divull)(CPUM68KState *env, int numr, int regr, uint32_t den) env->dregs[numr] = quot; } -void HELPER(divsll)(CPUM68KState *env, int numr, int regr, int32_t den) +void HELPER(divsll)(CPUM68KState *env, int numr, int regr, + int32_t den, int ilen) { int64_t num = deposit64(env->dregs[numr], 32, 32, env->dregs[regr]); int64_t quot; int32_t rem; + env->cc_c = 0; /* always cleared, even if overflow/div0 */ + if (den == 0) { - raise_exception_ra(env, EXCP_DIV0, GETPC()); + raise_exception_format2(env, EXCP_DIV0, ilen, GETPC()); } quot = num / den; rem = num % den; - env->cc_c = 0; /* always cleared, even if overflow */ if (quot != (int32_t)quot) { env->cc_v = -1; /* diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 6d6d026e3c..d775345bfa 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -1601,6 +1601,7 @@ DISAS_INSN(divw) int sign; TCGv src; TCGv destr; + TCGv ilen; /* divX.w ,Dn 32/16 -> 16r:16q */ @@ -1609,20 +1610,20 @@ DISAS_INSN(divw) /* dest.l / src.w */ SRC_EA(env, src, OS_WORD, sign, NULL); - destr = tcg_const_i32(REG(insn, 9)); + destr = tcg_constant_i32(REG(insn, 9)); + ilen = tcg_constant_i32(s->pc - s->base.pc_next); if (sign) { - gen_helper_divsw(cpu_env, destr, src); + gen_helper_divsw(cpu_env, destr, src, ilen); } else { - gen_helper_divuw(cpu_env, destr, src); + gen_helper_divuw(cpu_env, destr, src, ilen); } - tcg_temp_free(destr); set_cc_op(s, CC_OP_FLAGS); } DISAS_INSN(divl) { - TCGv num, reg, den; + TCGv num, reg, den, ilen; int sign; uint16_t ext; @@ -1639,15 +1640,14 @@ DISAS_INSN(divl) /* divX.l , Dr:Dq 64/32 -> 32r:32q */ SRC_EA(env, den, OS_LONG, 0, NULL); - num = tcg_const_i32(REG(ext, 12)); - reg = tcg_const_i32(REG(ext, 0)); + num = tcg_constant_i32(REG(ext, 12)); + reg = tcg_constant_i32(REG(ext, 0)); + ilen = tcg_constant_i32(s->pc - s->base.pc_next); if (sign) { - gen_helper_divsll(cpu_env, num, reg, den); + gen_helper_divsll(cpu_env, num, reg, den, ilen); } else { - gen_helper_divull(cpu_env, num, reg, den); + gen_helper_divull(cpu_env, num, reg, den, ilen); } - tcg_temp_free(reg); - tcg_temp_free(num); set_cc_op(s, CC_OP_FLAGS); return; } @@ -1656,15 +1656,14 @@ DISAS_INSN(divl) /* divXl.l , Dr:Dq 32/32 -> 32r:32q */ SRC_EA(env, den, OS_LONG, 0, NULL); - num = tcg_const_i32(REG(ext, 12)); - reg = tcg_const_i32(REG(ext, 0)); + num = tcg_constant_i32(REG(ext, 12)); + reg = tcg_constant_i32(REG(ext, 0)); + ilen = tcg_constant_i32(s->pc - s->base.pc_next); if (sign) { - gen_helper_divsl(cpu_env, num, reg, den); + gen_helper_divsl(cpu_env, num, reg, den, ilen); } else { - gen_helper_divul(cpu_env, num, reg, den); + gen_helper_divul(cpu_env, num, reg, den, ilen); } - tcg_temp_free(reg); - tcg_temp_free(num); set_cc_op(s, CC_OP_FLAGS); } From patchwork Thu Jun 2 01:33:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 578084 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp108148max; Wed, 1 Jun 2022 18:44:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzUmujw2L7m+lCgGbV1HwcSCsx8zJBZ0JI0Fu1BV4kyNzFAxmhgw/GfYSSyfR6BUX2AUpID X-Received: by 2002:a05:6214:3016:b0:466:426a:5fbe with SMTP id ke22-20020a056214301600b00466426a5fbemr3095097qvb.90.1654134282743; Wed, 01 Jun 2022 18:44:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; 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([2602:ae:1547:e101:1eca:8ee3:9269:e00c]) by smtp.gmail.com with ESMTPSA id l191-20020a6391c8000000b003fc5b1db26fsm1962875pge.52.2022.06.01.18.34.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 18:34:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH v6 08/17] target/m68k: Fix address argument for EXCP_TRACE Date: Wed, 1 Jun 2022 18:33:52 -0700 Message-Id: <20220602013401.303699-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602013401.303699-1-richard.henderson@linaro.org> References: <20220602013401.303699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" According to the M68040 Users Manual, section 8.4.3, Six word stack frame (format 2), Trace (and others) is supposed to record the next insn in PC and the address of the trapping instruction in ADDRESS. Create gen_raise_exception_format2 to record the trapping pc in env->mmu.ar. Update m68k_interrupt_all to pass the value to do_stack_frame. Update cpu_loop to handle EXCP_TRACE. Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- linux-user/m68k/cpu_loop.c | 3 +++ target/m68k/op_helper.c | 2 +- target/m68k/translate.c | 49 +++++++++++++++++++++++++------------- 3 files changed, 36 insertions(+), 18 deletions(-) diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index 6598bce3c4..fcf9220552 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -52,6 +52,9 @@ void cpu_loop(CPUM68KState *env) case EXCP_DIV0: force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->mmu.ar); break; + case EXCP_TRACE: + force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_TRACE, env->mmu.ar); + break; case EXCP_TRAP0: { abi_long ret; diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 729ee0e934..3cb71c9140 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -397,13 +397,13 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) case EXCP_ILLEGAL: case EXCP_TRAPCC: - case EXCP_TRACE: /* FIXME: addr is not only env->pc */ do_stack_frame(env, &sp, 2, oldsr, env->pc, env->pc); break; case EXCP_CHK: case EXCP_DIV0: + case EXCP_TRACE: do_stack_frame(env, &sp, 2, oldsr, env->mmu.ar, env->pc); break; diff --git a/target/m68k/translate.c b/target/m68k/translate.c index d775345bfa..399d9232e4 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -114,6 +114,7 @@ typedef struct DisasContext { DisasContextBase base; CPUM68KState *env; target_ulong pc; + target_ulong pc_prev; CCOp cc_op; /* Current CC operation */ int cc_op_synced; TCGv_i64 mactmp; @@ -298,6 +299,21 @@ static void gen_raise_exception(int nr) tcg_temp_free_i32(tmp); } +static void gen_raise_exception_format2(DisasContext *s, int nr, + target_ulong this_pc) +{ + /* + * Pass the address of the insn to the exception handler, + * for recording in the Format $2 (6-word) stack frame. + * Re-use mmu.ar for the purpose, since that's only valid + * after tlb_fill. + */ + tcg_gen_st_i32(tcg_constant_i32(this_pc), cpu_env, + offsetof(CPUM68KState, mmu.ar)); + gen_raise_exception(nr); + s->base.is_jmp = DISAS_NORETURN; +} + static void gen_exception(DisasContext *s, uint32_t dest, int nr) { update_cc_op(s); @@ -1494,12 +1510,13 @@ static void gen_exit_tb(DisasContext *s) } while (0) /* Generate a jump to an immediate address. */ -static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest) +static void gen_jmp_tb(DisasContext *s, int n, target_ulong dest, + target_ulong src) { if (unlikely(s->ss_active)) { update_cc_op(s); tcg_gen_movi_i32(QREG_PC, dest); - gen_raise_exception(EXCP_TRACE); + gen_raise_exception_format2(s, EXCP_TRACE, src); } else if (translator_use_goto_tb(&s->base, dest)) { tcg_gen_goto_tb(n); tcg_gen_movi_i32(QREG_PC, dest); @@ -1548,9 +1565,9 @@ DISAS_INSN(dbcc) tcg_gen_addi_i32(tmp, tmp, -1); gen_partset_reg(OS_WORD, reg, tmp); tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, -1, l1); - gen_jmp_tb(s, 1, base + offset); + gen_jmp_tb(s, 1, base + offset, s->base.pc_next); gen_set_label(l1); - gen_jmp_tb(s, 0, s->pc); + gen_jmp_tb(s, 0, s->pc, s->base.pc_next); } DISAS_INSN(undef_mac) @@ -3096,13 +3113,13 @@ DISAS_INSN(branch) /* Bcc */ TCGLabel *l1 = gen_new_label(); gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1); - gen_jmp_tb(s, 1, base + offset); + gen_jmp_tb(s, 1, base + offset, s->base.pc_next); gen_set_label(l1); - gen_jmp_tb(s, 0, s->pc); + gen_jmp_tb(s, 0, s->pc, s->base.pc_next); } else { /* Unconditional branch. */ update_cc_op(s); - gen_jmp_tb(s, 0, base + offset); + gen_jmp_tb(s, 0, base + offset, s->base.pc_next); } } @@ -5485,9 +5502,9 @@ DISAS_INSN(fbcc) l1 = gen_new_label(); update_cc_op(s); gen_fjmpcc(s, insn & 0x3f, l1); - gen_jmp_tb(s, 0, s->pc); + gen_jmp_tb(s, 0, s->pc, s->base.pc_next); gen_set_label(l1); - gen_jmp_tb(s, 1, base + offset); + gen_jmp_tb(s, 1, base + offset, s->base.pc_next); } DISAS_INSN(fscc) @@ -6158,6 +6175,8 @@ static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) dc->env = env; dc->pc = dc->base.pc_first; + /* This value will always be filled in properly before m68k_tr_tb_stop. */ + dc->pc_prev = 0xdeadbeef; dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_synced = 1; dc->done_mac = 0; @@ -6191,6 +6210,7 @@ static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) do_writebacks(dc); do_release(dc); + dc->pc_prev = dc->base.pc_next; dc->base.pc_next = dc->pc; if (dc->base.is_jmp == DISAS_NEXT) { @@ -6225,17 +6245,12 @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) break; case DISAS_TOO_MANY: update_cc_op(dc); - if (dc->ss_active) { - tcg_gen_movi_i32(QREG_PC, dc->pc); - gen_raise_exception(EXCP_TRACE); - } else { - gen_jmp_tb(dc, 0, dc->pc); - } + gen_jmp_tb(dc, 0, dc->pc, dc->pc_prev); break; case DISAS_JUMP: /* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */ if (dc->ss_active) { - gen_raise_exception(EXCP_TRACE); + gen_raise_exception_format2(dc, EXCP_TRACE, dc->pc_prev); } else { tcg_gen_lookup_and_goto_ptr(); } @@ -6246,7 +6261,7 @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) * other state that may require returning to the main loop. */ if (dc->ss_active) { - gen_raise_exception(EXCP_TRACE); + gen_raise_exception_format2(dc, EXCP_TRACE, dc->pc_prev); } else { tcg_gen_exit_tb(NULL, 0); } From patchwork Thu Jun 2 01:33:53 2022 Content-Type: text/plain; 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([2602:ae:1547:e101:1eca:8ee3:9269:e00c]) by smtp.gmail.com with ESMTPSA id l191-20020a6391c8000000b003fc5b1db26fsm1962875pge.52.2022.06.01.18.34.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 18:34:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH v6 09/17] target/m68k: Fix stack frame for EXCP_ILLEGAL Date: Wed, 1 Jun 2022 18:33:53 -0700 Message-Id: <20220602013401.303699-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602013401.303699-1-richard.henderson@linaro.org> References: <20220602013401.303699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" According to the M68040 Users Manual, section 8.4.1, Four word stack frame (format 0), includes Illegal Instruction. Use the correct frame format, which does not use the ADDR argument. Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/op_helper.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 3cb71c9140..aa62158eb9 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -391,11 +391,14 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) } break; + case EXCP_ILLEGAL: + do_stack_frame(env, &sp, 0, oldsr, 0, env->pc); + break; + case EXCP_ADDRESS: do_stack_frame(env, &sp, 2, oldsr, 0, env->pc); break; - case EXCP_ILLEGAL: case EXCP_TRAPCC: /* FIXME: addr is not only env->pc */ do_stack_frame(env, &sp, 2, oldsr, env->pc, env->pc); From patchwork Thu Jun 2 01:33:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 578087 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp110430max; Wed, 1 Jun 2022 18:49:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxsLc6q8CoCg0L8XSASSaPrqIkbhX+ZbZOS8hLghxnSB9yjfjpjUk2AeuZJ406sXVKPs+G7 X-Received: by 2002:a05:6214:21e2:b0:464:4f59:e546 with SMTP id p2-20020a05621421e200b004644f59e546mr15695210qvj.93.1654134585831; Wed, 01 Jun 2022 18:49:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654134585; cv=none; d=google.com; s=arc-20160816; b=MTeb0Ub2uH32onorNaiINU6ICV25cGMMit1n7st0qJ2hjYscgscAU8YBt6GK44iKLg MibGHNCjSsxShJmTuh46I+wDu/yVwR5KQx9NmuZEukBSSkQtRE5mTLx2/B4o0R5X/Si0 ftI5ZyIhcaA/Ra89R3nFMob9zutsFt4Y/KWWpcrZp1aINqNFav0xLwWXwnfi4tOfHJYp yQopoGCnFN6rGTDMcLpiib/Yk6SlTLNobJWRSPFSen5SQvnk6DxrLztYYiDEdOe1b8cQ nwI5t4ODoGB70vDnB78vFP+ywGMc634SPZ+WGmi22fITt3OZSx7mKr2gVnx0veuy2FrB fouw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Ga6M5TFkkaYF0mj3zd4e3fWL1GckLYt0gBCWZ8vZfkU=; b=AyY6ItcSAugAjl9yMz1WQC1xh+quNCLrQVgbySNZDo2Rt3fBnZ+KIMgtMWKnocmOco WryJddTg/I3cnlFwgYAxbb0j1ub+k2dgF1mkmiJTbhzmb3wXtKTW4LLVMOWsABuKWDO9 +SAnrxSxmquyU8W65ynbYmwQnAQIdPbPxQCnJrVASrLB6OstLu9RRly7YHvPXRZ3Zej7 apGGC5X2b9mAVlULmJmKGE1atpuFUBNccmemD+q0jyWrp3IlC829oe5Hwly0hbEtc8j6 EV52LM7WpqPR9BOEaV7euZBKbhQefbRGF8d6Zd8U1uQY59nqgSM3S3qlLXqD/ZndPE1v Qp+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zYAViKlr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:1eca:8ee3:9269:e00c]) by smtp.gmail.com with ESMTPSA id l191-20020a6391c8000000b003fc5b1db26fsm1962875pge.52.2022.06.01.18.34.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 18:34:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH v6 10/17] target/m68k: Implement TRAPcc Date: Wed, 1 Jun 2022 18:33:54 -0700 Message-Id: <20220602013401.303699-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602013401.303699-1-richard.henderson@linaro.org> References: <20220602013401.303699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Resolves: https://gitlab.com/qemu-project/qemu/-/issues/754 Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- v6: Use more exact masks for trapcc, to fix overlap with scc. --- target/m68k/cpu.h | 2 ++ linux-user/m68k/cpu_loop.c | 1 + target/m68k/cpu.c | 1 + target/m68k/op_helper.c | 6 +---- target/m68k/translate.c | 49 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 54 insertions(+), 5 deletions(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 558c3c67d6..4d8f48e8c7 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -534,6 +534,8 @@ enum m68k_features { M68K_FEATURE_MOVEC, /* Unaligned data accesses (680[2346]0) */ M68K_FEATURE_UNALIGNED_DATA, + /* TRAPcc insn. (680[2346]0, and CPU32) */ + M68K_FEATURE_TRAPCC, }; static inline int m68k_feature(CPUM68KState *env, int feature) diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index fcf9220552..3d3033155f 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -47,6 +47,7 @@ void cpu_loop(CPUM68KState *env) force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc); break; case EXCP_CHK: + case EXCP_TRAPCC: force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, env->mmu.ar); break; case EXCP_DIV0: diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index c7aeb7da9c..5f778773d1 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -162,6 +162,7 @@ static void m68020_cpu_initfn(Object *obj) m68k_set_feature(env, M68K_FEATURE_CHK2); m68k_set_feature(env, M68K_FEATURE_MSP); m68k_set_feature(env, M68K_FEATURE_UNALIGNED_DATA); + m68k_set_feature(env, M68K_FEATURE_TRAPCC); } /* diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index aa62158eb9..61948d92bb 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -399,14 +399,10 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) do_stack_frame(env, &sp, 2, oldsr, 0, env->pc); break; - case EXCP_TRAPCC: - /* FIXME: addr is not only env->pc */ - do_stack_frame(env, &sp, 2, oldsr, env->pc, env->pc); - break; - case EXCP_CHK: case EXCP_DIV0: case EXCP_TRACE: + case EXCP_TRAPCC: do_stack_frame(env, &sp, 2, oldsr, env->mmu.ar, env->pc); break; diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 399d9232e4..61b624b3a1 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4879,6 +4879,53 @@ DISAS_INSN(trap) gen_exception(s, s->pc, EXCP_TRAP0 + (insn & 0xf)); } +static void do_trapcc(DisasContext *s, DisasCompare *c) +{ + if (c->tcond != TCG_COND_NEVER) { + TCGLabel *over = NULL; + + update_cc_op(s); + + if (c->tcond != TCG_COND_ALWAYS) { + /* Jump over if !c. */ + over = gen_new_label(); + tcg_gen_brcond_i32(tcg_invert_cond(c->tcond), c->v1, c->v2, over); + } + + tcg_gen_movi_i32(QREG_PC, s->pc); + gen_raise_exception_format2(s, EXCP_TRAPCC, s->base.pc_next); + + if (over != NULL) { + gen_set_label(over); + s->base.is_jmp = DISAS_NEXT; + } + } + free_cond(c); +} + +DISAS_INSN(trapcc) +{ + DisasCompare c; + + /* Consume and discard the immediate operand. */ + switch (extract32(insn, 0, 3)) { + case 2: /* trapcc.w */ + (void)read_im16(env, s); + break; + case 3: /* trapcc.l */ + (void)read_im32(env, s); + break; + case 4: /* trapcc (no operand) */ + break; + default: + /* trapcc registered with only valid opmodes */ + g_assert_not_reached(); + } + + gen_cc_cond(&c, s, extract32(insn, 8, 4)); + do_trapcc(s, &c); +} + static void gen_load_fcr(DisasContext *s, TCGv res, int reg) { switch (reg) { @@ -6050,6 +6097,8 @@ void register_m68k_insns (CPUM68KState *env) INSN(scc, 50c0, f0f8, CF_ISA_A); /* Scc.B Dx */ INSN(scc, 50c0, f0c0, M68000); /* Scc.B */ INSN(dbcc, 50c8, f0f8, M68000); + INSN(trapcc, 50fa, f0fe, TRAPCC); /* opmode 010, 011 */ + INSN(trapcc, 50fc, f0ff, TRAPCC); /* opmode 100 */ INSN(tpf, 51f8, fff8, CF_ISA_A); /* Branch instructions. */ From patchwork Thu Jun 2 01:33:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 578088 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp110977max; 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([2602:ae:1547:e101:1eca:8ee3:9269:e00c]) by smtp.gmail.com with ESMTPSA id l191-20020a6391c8000000b003fc5b1db26fsm1962875pge.52.2022.06.01.18.34.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 18:34:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v6 11/17] target/m68k: Implement TPF in terms of TRAPcc Date: Wed, 1 Jun 2022 18:33:55 -0700 Message-Id: <20220602013401.303699-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602013401.303699-1-richard.henderson@linaro.org> References: <20220602013401.303699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" TPF stands for "trap false", and is a long-form nop for ColdFire. Re-use the immediate consumption code from trapcc; the insn will already expand to a nop because of the TCG_COND_NEVER test within do_trapcc. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/translate.c | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 61b624b3a1..83c2f73063 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -3075,22 +3075,6 @@ DISAS_INSN(addsubq) tcg_temp_free(dest); } -DISAS_INSN(tpf) -{ - switch (insn & 7) { - case 2: /* One extension word. */ - s->pc += 2; - break; - case 3: /* Two extension words. */ - s->pc += 4; - break; - case 4: /* No extension words. */ - break; - default: - disas_undef(env, s, insn); - } -} - DISAS_INSN(branch) { int32_t offset; @@ -6099,7 +6083,8 @@ void register_m68k_insns (CPUM68KState *env) INSN(dbcc, 50c8, f0f8, M68000); INSN(trapcc, 50fa, f0fe, TRAPCC); /* opmode 010, 011 */ INSN(trapcc, 50fc, f0ff, TRAPCC); /* opmode 100 */ - INSN(tpf, 51f8, fff8, CF_ISA_A); + INSN(trapcc, 51fa, fffe, CF_ISA_A); /* TPF (trapf) opmode 010, 011 */ + INSN(trapcc, 51fc, ffff, CF_ISA_A); /* TPF (trapf) opmode 100 */ /* Branch instructions. */ BASE(branch, 6000, f000); From patchwork Thu Jun 2 01:33:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 578090 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp112512max; Wed, 1 Jun 2022 18:54:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxzb37YdDZUXzIJqm9qsmINS6M7t3ZwSbnolNO/3tGxxqhKi94WF88vYiCKoKdsKpTpfQdU X-Received: by 2002:a05:6214:76e:b0:467:cf81:7f3e with SMTP id f14-20020a056214076e00b00467cf817f3emr238782qvz.89.1654134840546; Wed, 01 Jun 2022 18:54:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654134840; cv=none; d=google.com; s=arc-20160816; b=dSLdOHzaLnCPs+lRSZqeNUrTp8Dl/jxfJYO1hlT6yJ6r9+2IHcrL0Iud//XZmyllsJ HbyflXO/bjMsHiYccAMc61RNvcpI52Z7cQ/kSA+3u7PpaN0H4+dhZw3sQntkrrer5cMo ueWKfGbbtEcSfgEXyY2ItsDola9NDTJwV0XIBz+Eu4okIN2sLlDFRTXtB7BxxLpEceSl I4xhc0rjaImJP0vIl1QwJRrD8NwvUfbmgSvo9H9ex8z16zqcvs9ShpIUpoC8kqEDNO9Z jyXZvtruwvLrP4QaZlMjrQMWp10Pm/qUIclZbLPraFF39IcurUrqMsqKl3dqUODRtUSA ItcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=L/s5DB9oA5m3J3r5mnRcmLEGwctJwKQaqGAa+nl3EZs=; b=gobBNvHB2h7jmWxEsLM7MqIWn4fqqM1f5xv0aOIUiNC8N9Lcw5HBD04I4otGbzK+uQ VokbLLwAWt0rokm9u1GUDHMzIdlicEnjF99bRlQE7WzUR12X+pUQNUcmXk+7yStgKdY2 xi/rTbUiY84gNh64tKrofWGItwuOoDTWgY0YC3XQDzclmvHHJi+KSZaFQ7wbLqFOyI4e bPSZ9HuxFnKUPQYr0DYMG41Z5RK8K0AUiP2Xfl0F6ioaetfbzEkLcGqZL3KFy8DPV8iB wOCAUCZNbb7tNMUF7mWSZ2ijj1lrHvgU/+OXZ9BXwp/t8a3pG183v1Jk1j+reHFqHeAz i4Wg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xwtzXLAh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:1eca:8ee3:9269:e00c]) by smtp.gmail.com with ESMTPSA id l191-20020a6391c8000000b003fc5b1db26fsm1962875pge.52.2022.06.01.18.34.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 18:34:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH v6 12/17] target/m68k: Implement TRAPV Date: Wed, 1 Jun 2022 18:33:56 -0700 Message-Id: <20220602013401.303699-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602013401.303699-1-richard.henderson@linaro.org> References: <20220602013401.303699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/translate.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 83c2f73063..fa704e0c25 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4910,6 +4910,14 @@ DISAS_INSN(trapcc) do_trapcc(s, &c); } +DISAS_INSN(trapv) +{ + DisasCompare c; + + gen_cc_cond(&c, s, 9); /* V set */ + do_trapcc(s, &c); +} + static void gen_load_fcr(DisasContext *s, TCGv res, int reg) { switch (reg) { @@ -6073,6 +6081,7 @@ void register_m68k_insns (CPUM68KState *env) BASE(nop, 4e71, ffff); INSN(rtd, 4e74, ffff, RTD); BASE(rts, 4e75, ffff); + INSN(trapv, 4e76, ffff, M68000); INSN(rtr, 4e77, ffff, M68000); BASE(jump, 4e80, ffc0); BASE(jump, 4ec0, ffc0); From patchwork Thu Jun 2 01:33:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 578089 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp112501max; Wed, 1 Jun 2022 18:53:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwTnsiC3z6YumNe0mwZNs1WyfOYOXzOmygdVZcdDpJzH8PgTgRS7/hQG1Rm8k+5hHfgfxDR X-Received: by 2002:a37:b085:0:b0:6a5:faff:65ec with SMTP id z127-20020a37b085000000b006a5faff65ecmr2016030qke.112.1654134839260; Wed, 01 Jun 2022 18:53:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654134839; cv=none; d=google.com; s=arc-20160816; b=LrUaErmy+F6Nk5Fa6tqCyNFOsaOxTwkSFsYg0XOrttLDUqvCg41cnHUC/KYbs0ccKP 3Z3mLQQNxK85e/GBrmCJoWqD5e/1dnFr3OX7vXAlS1GqLgTHOGPh3Lmd5JH/wZapKgSx C/B/HSc75PPgA7Qw725M93zP1dmX6xyxDOY+0GC67iKRbbza1Kow1O7a8LA9+Bt5+JaP nZnZD8m7/IhZQFJRdeAC/K0dd/RafPSgVAbmt6efhzgP09vsuMcDqUEhup/t03A/UOXk X8z0Agac9H1bKnx6JKdwPc+owApdRavnQgB9PQ61sF3xfuW/N2ocomF/CitzxrgiHsAa TE8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=IhaQ71DRJcMZN5BIZLMGgAqxrNC/+qcBfUUjhN0p2Oc=; b=MyxmGn1BMbrs1vZHpPi4bjdV1YTlxvCWkQsAyJYbncPEpljySGZnOd+pzWRySUZwDG MwOR1Fgs0HeNY2cKVOC4KybN+OUzSgPwzlaYI+FyjxD5UIeC7XOqThCOI0+bICO8ikTg vfSgZF3jQ9l3eprFuRPte52bg37jZ3djvKcu7N3o5A9IKTljkEasZmFLpaRt3nU2wYxx GacytZE2kxkNaNA1uFQguwkjLU/+vu4e7RkKTN/GGqnvCwoPt/zcSvb2INstg52/95OV ofGIF5cMkAaq2S8YWK3qY+XxH8w3Jl/+PNrSzhWD5u3JLuvVdCNSkR/ki/IUpPrVNTUa m8xQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MLxIj7UC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:1eca:8ee3:9269:e00c]) by smtp.gmail.com with ESMTPSA id l191-20020a6391c8000000b003fc5b1db26fsm1962875pge.52.2022.06.01.18.34.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 18:34:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH v6 13/17] target/m68k: Implement FTRAPcc Date: Wed, 1 Jun 2022 18:33:57 -0700 Message-Id: <20220602013401.303699-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602013401.303699-1-richard.henderson@linaro.org> References: <20220602013401.303699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/translate.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index fa704e0c25..cc3bd4dd2b 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -5566,6 +5566,34 @@ DISAS_INSN(fscc) tcg_temp_free(tmp); } +DISAS_INSN(ftrapcc) +{ + DisasCompare c; + uint16_t ext; + int cond; + + ext = read_im16(env, s); + cond = ext & 0x3f; + + /* Consume and discard the immediate operand. */ + switch (extract32(insn, 0, 3)) { + case 2: /* ftrapcc.w */ + (void)read_im16(env, s); + break; + case 3: /* ftrapcc.l */ + (void)read_im32(env, s); + break; + case 4: /* ftrapcc (no operand) */ + break; + default: + /* ftrapcc registered with only valid opmodes */ + g_assert_not_reached(); + } + + gen_fcc_cond(&c, s, cond); + do_trapcc(s, &c); +} + #if defined(CONFIG_SOFTMMU) DISAS_INSN(frestore) { @@ -6191,6 +6219,8 @@ void register_m68k_insns (CPUM68KState *env) INSN(fbcc, f280, ffc0, CF_FPU); INSN(fpu, f200, ffc0, FPU); INSN(fscc, f240, ffc0, FPU); + INSN(ftrapcc, f27a, fffe, FPU); /* opmode 010, 011 */ + INSN(ftrapcc, f27c, ffff, FPU); /* opmode 100 */ INSN(fbcc, f280, ff80, FPU); #if defined(CONFIG_SOFTMMU) INSN(frestore, f340, ffc0, CF_FPU); From patchwork Thu Jun 2 01:33:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 578081 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp106664max; Wed, 1 Jun 2022 18:41:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxKr2l5djjnv86M49BTdFvwad8TrBt3gaD7f6odfBKHXrh3u0607eTxeKl+cN98i6trCwAH X-Received: by 2002:a05:622a:1747:b0:304:b5c7:887f with SMTP id l7-20020a05622a174700b00304b5c7887fmr2138084qtk.628.1654134076097; Wed, 01 Jun 2022 18:41:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654134076; cv=none; d=google.com; s=arc-20160816; b=ps89Wp+eHz2eFR1WFz8phfysTq3Pduc0ew3lWAK3lTrEM5vyIHPwurTe0prhD2geSS KC9ky+z6vkpsdKLxVQH5ZDsq0F+rZWioZtUP8nH2U7AF367mfMHJ6DAw5lA9qYSkcL3z Jt1Xg9FhVF8MC8nSoHu3Q0vp1m2Kk2aT975/3rquSj21FlLLO+CGZd2nzw0lbngcc3q0 ly978Jcc/NG7CuSJnA71Q2VJ6xOOFJTD29bQWqaIVXGsPh93as6SuNPID0pI8H026l1T HPJlMu+h5ienZf8X/jvLJuwiXorFX94g/ShHJCqedzIi3b+tJq+GSJVhO+tJvvF7DhDU WZDw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Ec0dbY3Lo89Y5jy2prv7uGoDI+hJWJ+BkmpUFqfWdho=; b=GvOGoHdCX/7CjNUvwrsjQPOqbKPi6X5OZW9XViS6vyGxrbaPN9mXlPXKrouJv58Q8l PtqrK6MCTvknkb5fB2D5a6HiHUy2h63XeqAbc6iwm35EgRkcROcT8mouWFYY+TRNo9Or 8p3ioxADUvaRi9/WIiPqdLCAekmxFkFIw4GF4G2wAEzQjjOAx2mqReKMjj5PZKquddE/ sPAZCiVLz7i4jJs6kPprs0zazJn2730/kAV9UCoWc/kwzzjKBlto0wwLncLdDZikdQUv 5oYZ4AbeiybyQQHsYw0v0devzoMl2ORcOufMnNdU+cAOq85aBoyZnK9GnXKQW/rY7TIx z0Lw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=y68fsTxs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:1eca:8ee3:9269:e00c]) by smtp.gmail.com with ESMTPSA id l191-20020a6391c8000000b003fc5b1db26fsm1962875pge.52.2022.06.01.18.34.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 18:34:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH v6 14/17] tests/tcg/m68k: Add trap.c Date: Wed, 1 Jun 2022 18:33:58 -0700 Message-Id: <20220602013401.303699-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602013401.303699-1-richard.henderson@linaro.org> References: <20220602013401.303699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Test various trap instructions: chk, div, trap, trapv, trapcc, ftrapcc, and the signals and addresses that we expect from them. Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- tests/tcg/m68k/trap.c | 129 +++++++++++++++++++++++++++++++++ tests/tcg/m68k/Makefile.target | 3 + 2 files changed, 132 insertions(+) create mode 100644 tests/tcg/m68k/trap.c diff --git a/tests/tcg/m68k/trap.c b/tests/tcg/m68k/trap.c new file mode 100644 index 0000000000..96cac18d4d --- /dev/null +++ b/tests/tcg/m68k/trap.c @@ -0,0 +1,129 @@ +/* + * Test m68k trap addresses. + */ + +#define _GNU_SOURCE 1 +#include +#include +#include + +static int expect_sig; +static int expect_si_code; +static void *expect_si_addr; +static greg_t expect_mc_pc; +static volatile int got_signal; + +static void sig_handler(int sig, siginfo_t *si, void *puc) +{ + ucontext_t *uc = puc; + mcontext_t *mc = &uc->uc_mcontext; + + assert(sig == expect_sig); + assert(si->si_code == expect_si_code); + assert(si->si_addr == expect_si_addr); + assert(mc->gregs[R_PC] == expect_mc_pc); + + got_signal = 1; +} + +#define FMT_INS [ad] "a"(&expect_si_addr), [pc] "a"(&expect_mc_pc) +#define FMT0_STR(S) \ + "move.l #1f, (%[ad])\n\tmove.l #1f, (%[pc])\n" S "\n1:\n" +#define FMT2_STR(S) \ + "move.l #0f, (%[ad])\n\tmove.l #1f, (%[pc])\n" S "\n1:\n" + +#define CHECK_SIG do { assert(got_signal); got_signal = 0; } while (0) + +int main(int argc, char **argv) +{ + struct sigaction act = { + .sa_sigaction = sig_handler, + .sa_flags = SA_SIGINFO + }; + int t0, t1; + + sigaction(SIGILL, &act, NULL); + sigaction(SIGTRAP, &act, NULL); + sigaction(SIGFPE, &act, NULL); + + expect_sig = SIGFPE; + expect_si_code = FPE_INTOVF; + asm volatile(FMT2_STR("0:\tchk %0, %1") : : "d"(0), "d"(-1), FMT_INS); + CHECK_SIG; + +#if 0 + /* FIXME: chk2 not correctly translated. */ + int bounds[2] = { 0, 1 }; + asm volatile(FMT2_STR("0:\tchk2.l %0, %1") + : : "m"(bounds), "d"(2), FMT_INS); + CHECK_SIG; +#endif + + asm volatile(FMT2_STR("cmp.l %0, %1\n0:\ttrapv") + : : "d"(INT_MIN), "d"(1), FMT_INS); + CHECK_SIG; + + asm volatile(FMT2_STR("cmp.l %0, %0\n0:\ttrapeq") + : : "d"(0), FMT_INS); + CHECK_SIG; + + asm volatile(FMT2_STR("cmp.l %0, %0\n0:\ttrapeq.w #0x1234") + : : "d"(0), FMT_INS); + CHECK_SIG; + + asm volatile(FMT2_STR("cmp.l %0, %0\n0:\ttrapeq.l #0x12345678") + : : "d"(0), FMT_INS); + CHECK_SIG; + + asm volatile(FMT2_STR("fcmp.x %0, %0\n0:\tftrapeq") + : : "f"(0.0L), FMT_INS); + CHECK_SIG; + + expect_si_code = FPE_INTDIV; + + asm volatile(FMT2_STR("0:\tdivs.w %1, %0") + : "=d"(t0) : "d"(0), "0"(1), FMT_INS); + CHECK_SIG; + + asm volatile(FMT2_STR("0:\tdivsl.l %2, %1:%0") + : "=d"(t0), "=d"(t1) : "d"(0), "0"(1), FMT_INS); + CHECK_SIG; + + expect_sig = SIGILL; + expect_si_code = ILL_ILLTRP; + asm volatile(FMT0_STR("trap #1") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #2") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #3") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #4") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #5") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #6") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #7") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #8") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #9") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #10") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #11") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #12") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #13") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #14") : : FMT_INS); + CHECK_SIG; + + expect_sig = SIGTRAP; + expect_si_code = TRAP_BRKPT; + asm volatile(FMT0_STR("trap #15") : : FMT_INS); + CHECK_SIG; + + return 0; +} diff --git a/tests/tcg/m68k/Makefile.target b/tests/tcg/m68k/Makefile.target index 62f109eef4..1163c7ef03 100644 --- a/tests/tcg/m68k/Makefile.target +++ b/tests/tcg/m68k/Makefile.target @@ -3,5 +3,8 @@ # m68k specific tweaks - specifically masking out broken tests # +VPATH += $(SRC_PATH)/tests/tcg/m68k +TESTS += trap + # On m68k Linux supports 4k and 8k pages (but 8k is currently broken) EXTRA_RUNS+=run-test-mmap-4096 # run-test-mmap-8192 From patchwork Thu Jun 2 01:33:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 578092 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp113840max; 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([2602:ae:1547:e101:1eca:8ee3:9269:e00c]) by smtp.gmail.com with ESMTPSA id l191-20020a6391c8000000b003fc5b1db26fsm1962875pge.52.2022.06.01.18.34.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 18:34:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v6 15/17] linux-user/strace: Use is_error in print_syscall_err Date: Wed, 1 Jun 2022 18:33:59 -0700 Message-Id: <20220602013401.303699-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602013401.303699-1-richard.henderson@linaro.org> References: <20220602013401.303699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Errors are not all negative numbers: use is_error. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/strace.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux-user/strace.c b/linux-user/strace.c index 9fa681dea9..7d882526da 100644 --- a/linux-user/strace.c +++ b/linux-user/strace.c @@ -689,7 +689,7 @@ print_syscall_err(abi_long ret) const char *errstr; qemu_log(" = "); - if (ret < 0) { + if (is_error(ret)) { errstr = target_strerror(-ret); if (errstr) { qemu_log("-1 errno=%d (%s)", (int)-ret, errstr); From patchwork Thu Jun 2 01:34:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 578091 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp113842max; Wed, 1 Jun 2022 18:56:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy+wa2zbJeR/vwhpC5er4XJUWLU717wLNbpirmEZkDFvVOU35To0Q1lwaPOZ7t3RmFZaBUw X-Received: by 2002:ac8:7fd1:0:b0:2f3:dddb:4206 with SMTP id b17-20020ac87fd1000000b002f3dddb4206mr2122190qtk.11.1654134997265; Wed, 01 Jun 2022 18:56:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654134997; cv=none; d=google.com; s=arc-20160816; b=f7FZ4C0zkBo3RXZ2pkq6a1WSqVLz84DzGDFKcM/4ykelA7pmiSBUGy/gs+CgKn2PjK IKKsjHCbAtHHVwePqaYJAA3CHT23YJ5f3RiGJatAu+1HQ2xmhJjcqLXDslMcT7VMwRT9 VAEOc8pMUANi2NQsD/bdtX+BCMACdMBD2Dx58aasBdh5IvER/pAOAaEmLtnh0bJgEggz ZBMR9oH1qFJwwO9VLwFz70Plab7CiNOaKZCc19xG4Lq4+zisG1sppeK85IH9wAXmOt7/ hhHCJR1WY6Dxj/qp/dMNAiT7QASvWOc+zmnKAPIMAU6s6XbOtfE/4FVY2q/oF9iTYuTZ 4eyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=frtjY4kXdf+btOwpubtlaBEs6SblJPqCp8QSyGl5a7Y=; b=VE+NHGW4e7oz+wAKaFBlG2VK1nHka1iN1pPPfcQyHVKlHFR539M2wW7s91h3eGApo5 3LIZgSk21jhrBZBzTSRi9/VvcubKA6oVjFIjOBuQnU7PE6A/CH+XeochoMszrClELh15 cAOc/MbkTl8nmq7kNBgLFsxkl9M+nPezNhpoXhC3MuLhRTwm0srGBm1KeGgVyO+/w+TB jPNsVtMNDitsbMTkpWc+B7KWfi1ALkueDD5Cx7/w39slo3PY7rx2vgyj/R1grpUKb0iM TnuPcRigToxyYu1P3r8eqPc0afL6NmqA8mwvhcADlzNbmpdcbVUfdsaPehiDr56MJRoA Gvhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VTmk8IiN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:1eca:8ee3:9269:e00c]) by smtp.gmail.com with ESMTPSA id l191-20020a6391c8000000b003fc5b1db26fsm1962875pge.52.2022.06.01.18.34.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 18:34:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH v6 16/17] linux-user/strace: Adjust get_thread_area for m68k Date: Wed, 1 Jun 2022 18:34:00 -0700 Message-Id: <20220602013401.303699-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602013401.303699-1-richard.henderson@linaro.org> References: <20220602013401.303699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Unlike i386, m68k get_thread_area has no arguments. Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- linux-user/strace.list | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/linux-user/strace.list b/linux-user/strace.list index 278596acd1..72e17b1acf 100644 --- a/linux-user/strace.list +++ b/linux-user/strace.list @@ -384,8 +384,13 @@ { TARGET_NR_getsockopt, "getsockopt" , NULL, NULL, NULL }, #endif #ifdef TARGET_NR_get_thread_area +#if defined(TARGET_I386) && defined(TARGET_ABI32) { TARGET_NR_get_thread_area, "get_thread_area", "%s(0x"TARGET_ABI_FMT_lx")", NULL, NULL }, +#elif defined(TARGET_M68K) +{ TARGET_NR_get_thread_area, "get_thread_area" , "%s()", + NULL, print_syscall_ret_addr }, +#endif #endif #ifdef TARGET_NR_gettid { TARGET_NR_gettid, "gettid" , "%s()", NULL, NULL }, From patchwork Thu Jun 2 01:34:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 578077 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:5806:0:0:0:0 with SMTP id j6csp104079max; Wed, 1 Jun 2022 18:36:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzgXA+G1eVNfd3pAREbdz9YwgWgZiC8Mv3UpprKoua8cEV2IdPMw5wIrGQ8o4P54HbEx1ob X-Received: by 2002:ac8:7d82:0:b0:304:b091:e44 with SMTP id c2-20020ac87d82000000b00304b0910e44mr2123224qtd.44.1654133798222; Wed, 01 Jun 2022 18:36:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1654133798; cv=none; d=google.com; s=arc-20160816; b=S9bZymRvqzARSy4X6t1hNMfd02n/OYmQOT43lFNZl/Ai7zugDNsIeM7jFNgldC7lUg ICIZFOflOQM7GlPp5Xf1pN1OaPdMIFsYanGl5kJtu+0IMSxPEMzQ0V8T90XtPB5abvJx mmZMjv19R22wKtRyRG4acKqCL1gUbhm0QaMo/uEWM5mRr9gFNOesbUNxzJk6mD8kmKMR /cMk/oYtIoP93JXugVzRN7eWJQPSZDN7HRfADicA9wrBYuRaYudLKVxSRiRFDKve8dti J4Qy4vzNJFmp0zka+rcO5USwz02h94HHugNS/kEOuRIFojQHf3298BWh/6iI4+y7wZbJ mbpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=IPe9v04jpSOnM1YqKXysVjOVagzaKcyYJ8pPspoxKJ4=; b=AsDbuYn4j7oME1Rv5GhiMpBsFLvoMAHGy4JfZnpno2y/DKGRTwznMFIOlFcoacWWR8 brfYE0IhSb9auo5+07TIgOSgAdcdnD6+fIWUd1JCZ17vTbAup6jGQTSRA41a0uAUsWun 2CkNfKGdU6bmurrhTff8w4PdU7iLWlolJU9uX1Hfh4BUboETzXp47tqgwMU6yEa8K3Nu A2II3Q+ijvCZl1sSt8zWd6AJ8JuPyBBPsPu7EJrKIXfqw6dCmweJ8+J6G52FjeVSn8Vo p3Q6e4bv3SwE4OkgbdUoNfjp5LR8Lkf9293CpZf+gmKTxixeLIvI+BP2Hudrr/jk6dKD lIOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KLGBU8ui; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:ae:1547:e101:1eca:8ee3:9269:e00c]) by smtp.gmail.com with ESMTPSA id l191-20020a6391c8000000b003fc5b1db26fsm1962875pge.52.2022.06.01.18.34.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jun 2022 18:34:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v6 17/17] target/m68k: Mark helper_raise_exception as noreturn Date: Wed, 1 Jun 2022 18:34:01 -0700 Message-Id: <20220602013401.303699-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602013401.303699-1-richard.henderson@linaro.org> References: <20220602013401.303699-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Also mark raise_exception_ra and raise_exception, lest we generate a warning about helper_raise_exception returning. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/helper.h | 2 +- target/m68k/op_helper.c | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/target/m68k/helper.h b/target/m68k/helper.h index f016c4c1c2..c9bed2b884 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -109,7 +109,7 @@ DEF_HELPER_3(set_mac_extu, void, env, i32, i32) DEF_HELPER_2(flush_flags, void, env, i32) DEF_HELPER_2(set_ccr, void, env, i32) DEF_HELPER_FLAGS_1(get_ccr, TCG_CALL_NO_WG_SE, i32, env) -DEF_HELPER_2(raise_exception, void, env, i32) +DEF_HELPER_2(raise_exception, noreturn, env, i32) DEF_HELPER_FLAGS_3(bfffo_reg, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 61948d92bb..d9937ca8dc 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -532,7 +532,8 @@ bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request) #endif /* !CONFIG_USER_ONLY */ -static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr) +G_NORETURN static void +raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr) { CPUState *cs = env_cpu(env); @@ -540,7 +541,7 @@ static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr) cpu_loop_exit_restore(cs, raddr); } -static void raise_exception(CPUM68KState *env, int tt) +G_NORETURN static void raise_exception(CPUM68KState *env, int tt) { raise_exception_ra(env, tt, 0); }