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Gateway) with SMTP id D6.D7.08924.81E65926; Tue, 31 May 2022 10:23:36 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220531012333epsmtip25b80ec45fbb45fdb9cc2f1be95f565f0~0DA0jejt01198911989epsmtip28; Tue, 31 May 2022 01:23:33 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, linux-phy@lists.infradead.org Cc: devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, avri.altman@wdc.com, bvanassche@acm.org, martin.petersen@oracle.com, chanho61.park@samsung.com, pankaj.dubey@samsung.com, Alim Akhtar , linux-fsd@tesla.com, Bharat Uppal Subject: [PATCH 1/6] dt-bindings: phy: Add FSD UFS PHY bindings Date: Tue, 31 May 2022 06:52:15 +0530 Message-Id: <20220531012220.80563-2-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: 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Kozlowski --- Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml index f6ed1a005e7a..ee354bf37c64 100644 --- a/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml @@ -17,6 +17,7 @@ properties: enum: - samsung,exynos7-ufs-phy - samsung,exynosautov9-ufs-phy + - tesla,fsd-ufs-phy reg: maxItems: 1 From patchwork Tue May 31 01:22:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 578428 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59634C433EF for ; Tue, 31 May 2022 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Ar/fp7nBc61KGYIlUqNFVb04LA2DlFiKMxINtZiLihMBI3njxucCAAA= X-CMS-MailID: 20220531012341epcas5p19b15b4916b210687ab6b46d6da0b2273 X-Msg-Generator: CA CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220531012341epcas5p19b15b4916b210687ab6b46d6da0b2273 References: <20220531012220.80563-1-alim.akhtar@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Move CDR lock offset to drv data so that it can be extended for other SoCs which are having CDR lock at different register offset. Cc: linux-fsd@tesla.com Signed-off-by: Bharat Uppal Signed-off-by: Alim Akhtar --- drivers/phy/samsung/phy-exynos7-ufs.c | 3 +++ drivers/phy/samsung/phy-exynosautov9-ufs.c | 2 ++ drivers/phy/samsung/phy-samsung-ufs.c | 3 ++- drivers/phy/samsung/phy-samsung-ufs.h | 2 +- 4 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos7-ufs.c b/drivers/phy/samsung/phy-exynos7-ufs.c index 7c9008e163db..d1a37273cb1f 100644 --- a/drivers/phy/samsung/phy-exynos7-ufs.c +++ b/drivers/phy/samsung/phy-exynos7-ufs.c @@ -11,6 +11,8 @@ #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0) +#define PHY_CDR_LOCK_STATUS 0x5e + /* Calibration for phy initialization */ static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = { PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY), @@ -74,4 +76,5 @@ const struct samsung_ufs_phy_drvdata exynos7_ufs_phy = { .en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN, }, .has_symbol_clk = 1, + .cdr_lock_status_offset = PHY_CDR_LOCK_STATUS, }; diff --git a/drivers/phy/samsung/phy-exynosautov9-ufs.c b/drivers/phy/samsung/phy-exynosautov9-ufs.c index 36398a15c2db..1572b985c70d 100644 --- a/drivers/phy/samsung/phy-exynosautov9-ufs.c +++ b/drivers/phy/samsung/phy-exynosautov9-ufs.c @@ -10,6 +10,7 @@ #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL 0x728 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1 #define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0) +#define EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e #define PHY_TRSV_REG_CFG_AUTOV9(o, v, d) \ PHY_TRSV_REG_CFG_OFFSET(o, v, d, 0x50) @@ -64,4 +65,5 @@ const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy = { .en = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CTRL_EN, }, .has_symbol_clk = 0, + .cdr_lock_status_offset = EXYNOSAUTOV9_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS, }; diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c index 602ddef259eb..8e5ae228daa7 100644 --- a/drivers/phy/samsung/phy-samsung-ufs.c +++ b/drivers/phy/samsung/phy-samsung-ufs.c @@ -63,7 +63,8 @@ static int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy) } err = readl_poll_timeout( - ufs_phy->reg_pma + PHY_APB_ADDR(PHY_CDR_LOCK_STATUS), + ufs_phy->reg_pma + + PHY_APB_ADDR(ufs_phy->drvdata->cdr_lock_status_offset), val, (val & PHY_CDR_LOCK_BIT), sleep_us, timeout_us); if (err) dev_err(ufs_phy->dev, diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h index 91a0e9f94f98..965c79bbc278 100644 --- a/drivers/phy/samsung/phy-samsung-ufs.h +++ b/drivers/phy/samsung/phy-samsung-ufs.h @@ -40,7 +40,6 @@ /* UFS PHY registers */ #define PHY_PLL_LOCK_STATUS 0x1e -#define PHY_CDR_LOCK_STATUS 0x5e #define PHY_PLL_LOCK_BIT BIT(5) #define PHY_CDR_LOCK_BIT BIT(4) @@ -109,6 +108,7 @@ struct samsung_ufs_phy_drvdata { u32 en; } isol; bool has_symbol_clk; + u32 cdr_lock_status_offset; }; struct samsung_ufs_phy { From patchwork Tue May 31 01:22:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 577699 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 140C1C433EF for ; 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d=samsung.com; s=mail20170921; t=1653960236; bh=QZHGho2JKSlEyIt4ZhoVZeWPhKB73n2EAzBRYPzripw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=k3dassqiGazRdDroM0AN99ZTiNb5OWpwOgklrBw0Wl5wNCT97RUJwU7aajPfHiVl8 wfQKPirI0sN/rw78Ayqg4m0j9IzLCM2V8mTf+YIRkX7clma42uhZAOXuyrKCYsdsOo V2H1F+LslMkrxqi2myVf4j2IJSSmI/mMN5u5jCLs= Received: from epsnrtp3.localdomain (unknown [182.195.42.164]) by epcas5p3.samsung.com (KnoxPortal) with ESMTP id 20220531012351epcas5p3db0fb51226b0fa287c2468f610bc24c1~0DBFZZM5m3040830408epcas5p3p; Tue, 31 May 2022 01:23:51 +0000 (GMT) Received: from epsmges5p1new.samsung.com (unknown [182.195.38.175]) by epsnrtp3.localdomain (Postfix) with ESMTP id 4LBvgS2dpvz4x9QK; Tue, 31 May 2022 01:23:48 +0000 (GMT) Received: from epcas5p4.samsung.com ( [182.195.41.42]) by epsmges5p1new.samsung.com (Symantec Messaging Gateway) with SMTP id DE.5B.10063.42E65926; Tue, 31 May 2022 10:23:48 +0900 (KST) Received: from epsmtrp2.samsung.com (unknown [182.195.40.14]) by epcas5p4.samsung.com (KnoxPortal) with ESMTPA id 20220531012347epcas5p48262cae18c75bb6ed029f7cd920800b4~0DBB14DkA2668226682epcas5p4i; Tue, 31 May 2022 01:23:47 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20220531012347epsmtrp2e9a64abf3508759450a76123798ec30d~0DBB0738X2334523345epsmtrp27; Tue, 31 May 2022 01:23:47 +0000 (GMT) X-AuditID: b6c32a49-4cbff7000000274f-9b-62956e24a637 Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id E4.6F.11276.32E65926; Tue, 31 May 2022 10:23:47 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220531012344epsmtip2c93362e8a3348c22cacae47095827136~0DA_mL-cf1203612036epsmtip26; Tue, 31 May 2022 01:23:44 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, linux-phy@lists.infradead.org Cc: devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, avri.altman@wdc.com, bvanassche@acm.org, martin.petersen@oracle.com, chanho61.park@samsung.com, pankaj.dubey@samsung.com, Alim Akhtar , linux-fsd@tesla.com, Bharat Uppal Subject: [PATCH 3/6] phy: samsung-ufs: add support for FSD ufs phy driver Date: Tue, 31 May 2022 06:52:17 +0530 Message-Id: <20220531012220.80563-4-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220531012220.80563-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprAJsWRmVeSWpSXmKPExsWy7bCmlq5K3tQkg8vbhSwezNvGZvHy51U2 i2svL7BbTPvwk9ni8n5ti/lHzrFa9L14yGyx6fE1VouHr8ItLu+aw2YxYdU3Fovu6zvYLJYf /8dksWjrF3aL1r1H2C123jnB7CDgcfmKt8emVZ1sHneu7WHz2Lyk3uPj01ssHn1bVjF6/Gua y+7xeZOcR/uBbqYAzqhsm4zUxJTUIoXUvOT8lMy8dFsl7+B453hTMwNDXUNLC3MlhbzE3FRb JRefAF23zBygH5QUyhJzSoFCAYnFxUr6djZF+aUlqQoZ+cUltkqpBSk5BSYFesWJucWleel6 eaklVoYGBkamQIUJ2RkPL/xlKriuVHGzbxJ7A+Mv2S5GTg4JAROJtWt/s3QxcnEICexmlOj4 1sIIkhAS+MQoMWU1N0TiG6PEjuVLWGE6du45wgaR2Mso8fLPVyYIp4VJYt6vj2BVbALaEnen bwFLiAg0M0oc7NgF5jALnGOSeLZ3A5DDwSEs4ClxdL4YSAOLgKrE6/fL2EFsXgEbidZPe5kh 1slLrN5wAMzmFLCV6N54GmyOhMBCDonNn84zQRS5SHTcb2WHsIUlXh3fAmVLSXx+t5cNZJeE gIfEoj9SEOEMibfL1zNC2PYSB67MYQEpYRbQlFi/Sx8kzCzAJ9H7+wkTRCevREebEES1qkTz u6ssELa0xMTubmigeEg0d+1jhITDBEaJA2e3s01glJ2FMHUBI+MqRsnUguLc9NRi0wLDvNRy eEQl5+duYgQnTS3PHYx3H3zQO8TIxMF4iFGCg1lJhNcqYmqSEG9KYmVValF+fFFpTmrxIUZT YJBNZJYSTc4Hpu28knhDE0sDEzMzMxNLYzNDJXFegf+NSUIC6YklqdmpqQWpRTB9TBycUg1M Trd0vFTMvp/bUSH2y4rx/c7UV1faFEzygqbfcCsKKAvsV8irP6yy3m9HWOY0/kUr6tberY/k vhbE0WT7tjQt7OOuD87MxjW7C+8ufD1b7N/0tscy+zJ3r2vn0HmqEfVc5KjUUZ7v/GYeEZdD BE65PCtJq3P7xLjh7vzTezUuBGiq3ozcevcks0L4ZcPOi0Vb3gglhczQmLm4I2jX1K7dF7Xt n60y27C/+6Hfn3d6H59c0BNKjJUQmCd7o6xL5/rPfFvJa3KuRe2nYpkXzZhXvTTw8WrLxUsm C5tutf+2fq+53u3gkH+f3PbWJJh7G0vcvL9u+8YP/1vrU9s3LTauXrL4x//TJ8KT+F4JFV/8 qcRSnJFoqMVcVJwIAGodk5MjBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrELMWRmVeSWpSXmKPExsWy7bCSvK5y3tQkg6Y1phYP5m1js3j58yqb xbWXF9gtpn34yWxxeb+2xfwj51gt+l48ZLbY9Pgaq8XDV+EWl3fNYbOYsOobi0X39R1sFsuP /2OyWLT1C7tF694j7BY775xgdhDwuHzF22PTqk42jzvX9rB5bF5S7/Hx6S0Wj74tqxg9/jXN Zff4vEnOo/1AN1MAZxSXTUpqTmZZapG+XQJXxsMLf5kKritV3OybxN7A+Eu2i5GTQ0LARGLn niNsXYxcHEICuxkl/p5ezgKRkJa4vnECO4QtLLHy33MwW0igiUli1odcEJtNQFvi7vQtTCC2 iEA7o8T97WwgNrPAHSaJVT0iXYwcHMICnhJH54uBhFkEVCVev18GNoZXwEai9dNeZojx8hKr NxwAszkFbCW6N55mglhlI/H4/muWCYx8CxgZVjFKphYU56bnFhsWGOallusVJ+YWl+al6yXn 525iBAe7luYOxu2rPugdYmTiYDzEKMHBrCTCaxUxNUmINyWxsiq1KD++qDQntfgQozQHi5I4 74Wuk/FCAumJJanZqakFqUUwWSYOTqkGpnDmI+/XzwvdJbU1bvVE88Tnx69zcomfsMx9290Y sdIjdOH7C1msbm+0ew6pxYlnXAvPmPoguKwvUVjvZbxe+HIPx+3PmE6WTMi48D4tym1po+L0 18oynpvSkrju3t7U4nj9w5Nrr4wb9n2a0MbymPnNtP//NgnM8DgmPqVx5gzmzWXn1LV4atnF PhfN/r83aFaZpJjL4Wc3j936duFo4hfOQtGraz6qKLNr79/dHDdlZ6xO4s16g0usdVY3kt7+ E9Tveq74/8TpDpZ9K037xYvOmns4q/v+j+XwdtYx7JL3PznLkrvw2axHU679fvb9rE23YD13 bEhastfO1GWPtu8qTzzeybCQY5NqS71WpxJLcUaioRZzUXEiAFtSiELlAgAA X-CMS-MailID: 20220531012347epcas5p48262cae18c75bb6ed029f7cd920800b4 X-Msg-Generator: CA CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220531012347epcas5p48262cae18c75bb6ed029f7cd920800b4 References: <20220531012220.80563-1-alim.akhtar@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Adds support for Tesla FSD ufs phy driver. This SoC has different cdr lock status offset. Cc: linux-fsd@tesla.com Signed-off-by: Bharat Uppal Signed-off-by: Alim Akhtar --- drivers/phy/samsung/Makefile | 1 + drivers/phy/samsung/phy-fsd-ufs.c | 63 +++++++++++++++++++++++++++ drivers/phy/samsung/phy-samsung-ufs.c | 3 ++ drivers/phy/samsung/phy-samsung-ufs.h | 1 + 4 files changed, 68 insertions(+) create mode 100644 drivers/phy/samsung/phy-fsd-ufs.c diff --git a/drivers/phy/samsung/Makefile b/drivers/phy/samsung/Makefile index 65e4cc59403f..afb34a153e34 100644 --- a/drivers/phy/samsung/Makefile +++ b/drivers/phy/samsung/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-exynos-ufs.o phy-exynos-ufs-y += phy-samsung-ufs.o phy-exynos-ufs-y += phy-exynos7-ufs.o phy-exynos-ufs-y += phy-exynosautov9-ufs.o +phy-exynos-ufs-y += phy-fsd-ufs.o obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o phy-exynos-usb2-y += phy-samsung-usb2.o phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o diff --git a/drivers/phy/samsung/phy-fsd-ufs.c b/drivers/phy/samsung/phy-fsd-ufs.c new file mode 100644 index 000000000000..a03656006093 --- /dev/null +++ b/drivers/phy/samsung/phy-fsd-ufs.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * UFS PHY driver data for FSD SoC + * + * Copyright (C) 2022 Samsung Electronics Co., Ltd. + * + */ +#ifndef _PHY_FSD_UFS_H_ +#define _PHY_FSD_UFS_H_ + +#include "phy-samsung-ufs.h" + +#define FSD_EMBEDDED_COMBO_PHY_CTRL 0x724 +#define FSD_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1 +#define FSD_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0) +#define FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x6e + +static const struct samsung_ufs_phy_cfg fsd_pre_init_cfg[] = { + PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY), + PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY), + PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY), + PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY), + PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY), + END_UFS_PHY_CFG +}; + +/* Calibration for HS mode series A/B */ +static const struct samsung_ufs_phy_cfg fsd_pre_pwr_hs_cfg[] = { + END_UFS_PHY_CFG +}; + +/* Calibration for HS mode series A/B atfer PMC */ +static const struct samsung_ufs_phy_cfg fsd_post_pwr_hs_cfg[] = { + END_UFS_PHY_CFG +}; + +static const struct samsung_ufs_phy_cfg *fsd_ufs_phy_cfgs[CFG_TAG_MAX] = { + [CFG_PRE_INIT] = fsd_pre_init_cfg, + [CFG_PRE_PWR_HS] = fsd_pre_pwr_hs_cfg, + [CFG_POST_PWR_HS] = fsd_post_pwr_hs_cfg, +}; + +const struct samsung_ufs_phy_drvdata fsd_ufs_phy = { + .cfg = fsd_ufs_phy_cfgs, + .isol = { + .offset = FSD_EMBEDDED_COMBO_PHY_CTRL, + .mask = FSD_EMBEDDED_COMBO_PHY_CTRL_MASK, + .en = FSD_EMBEDDED_COMBO_PHY_CTRL_EN, + }, + .has_symbol_clk = 0, + .cdr_lock_status_offset = FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS, +}; + +#endif /* _PHY_FSD_UFS_H_ */ diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c index 8e5ae228daa7..935c5c7a6d1e 100644 --- a/drivers/phy/samsung/phy-samsung-ufs.c +++ b/drivers/phy/samsung/phy-samsung-ufs.c @@ -351,6 +351,9 @@ static const struct of_device_id samsung_ufs_phy_match[] = { }, { .compatible = "samsung,exynosautov9-ufs-phy", .data = &exynosautov9_ufs_phy, + }, { + .compatible = "tesla,fsd-ufs-phy", + .data = &fsd_ufs_phy, }, {}, }; diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h index 965c79bbc278..74b40ef8e1d8 100644 --- a/drivers/phy/samsung/phy-samsung-ufs.h +++ b/drivers/phy/samsung/phy-samsung-ufs.h @@ -142,5 +142,6 @@ static inline void samsung_ufs_phy_ctrl_isol( extern const struct samsung_ufs_phy_drvdata exynos7_ufs_phy; extern const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy; +extern const struct samsung_ufs_phy_drvdata fsd_ufs_phy; #endif /* _PHY_SAMSUNG_UFS_ */ From patchwork Tue May 31 01:22:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 578427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2696C4332F for ; Tue, 31 May 2022 01:24:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243397AbiEaBYL (ORCPT ); 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Tue, 31 May 2022 01:23:51 +0000 (GMT) X-AuditID: b6c32a49-4b5ff7000000274f-ae-62956e28cd72 Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id 01.E7.08924.72E65926; Tue, 31 May 2022 10:23:51 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220531012349epsmtip2131f8e569927d4ac937c103a6681b312~0DBC4b_bT0656506565epsmtip2R; Tue, 31 May 2022 01:23:48 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, linux-phy@lists.infradead.org Cc: devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, avri.altman@wdc.com, bvanassche@acm.org, martin.petersen@oracle.com, chanho61.park@samsung.com, pankaj.dubey@samsung.com, Alim Akhtar , linux-fsd@tesla.com, Bharat Uppal Subject: [PATCH 4/6] dt-bindings: ufs: exynos-ufs: add fsd compatible Date: Tue, 31 May 2022 06:52:18 +0530 Message-Id: <20220531012220.80563-5-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220531012220.80563-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprEJsWRmVeSWpSXmKPExsWy7bCmuq5G3tQkg4ntohYP5m1js3j58yqb xbWXF9gtpn34yWxxeb+2xfwj51gt+l48ZLbY9Pgaq8XDV+EWl3fNYbOYsOobi0X39R1sFsuP /2OyWLT1C7tF694j7BY775xgdhDwuHzF22PTqk42jzvX9rB5bF5S7/Hx6S0Wj74tqxg9/jXN Zff4vEnOo/1AN1MAZ1S2TUZqYkpqkUJqXnJ+SmZeuq2Sd3C8c7ypmYGhrqGlhbmSQl5ibqqt kotPgK5bZg7QD0oKZYk5pUChgMTiYiV9O5ui/NKSVIWM/OISW6XUgpScApMCveLE3OLSvHS9 vNQSK0MDAyNToMKE7Iyuni3sBevYKpYvOsXcwLiFtYuRk0NCwERiQscE5i5GLg4hgd2MEm3H 5rJDOJ8YJZZd74JyPjNKrFtwlR2mZe2hs0wQiV2MEgt7fkBVtTBJnDt3kw2kik1AW+Lu9C1g VSICzYwSBzt2gTnMAueYJJ7t3cAEUiUs4Coxe+4jFhCbRUBVYurO+WBxXgEbiY1Hz0OdKC+x esMBZhCbU8BWonvjabBBEgILOSRO9T9mgShykbjwcTOULSzx6vgWqGOlJD6/2wt0EgeQ7SGx 6I8URDhD4u3y9YwQtr3EgStzWEBKmAU0Jdbv0gcJMwvwSfT+fsIE0ckr0dEmBFGtKtH87irU ImmJid3dUFd6SExc9IIVEhATGCW6n75gnMAoOwth6gJGxlWMkqkFxbnpqcWmBYZ5qeXwqErO z93ECE6cWp47GO8++KB3iJGJg/EQowQHs5IIr1XE1CQh3pTEyqrUovz4otKc1OJDjKbAIJvI LCWanA9M3Xkl8YYmlgYmZmZmJpbGZoZK4rwC/xuThATSE0tSs1NTC1KLYPqYODilGpiU66/0 3oip+iOip24Tzla2qLDNp+HBnIajQv+ubp7l963pts2Jy+9lKpI2z07eW/Vv/+Md/czqEon/ f//jntDySnJanJnHyrrN2r85brTXVZoI1U6Xsot6LGcxMyPku98pxhlbml1333hYfrxVuM7u 3PLXG5wDGx/GbKr95HSxLmD52pwDDU5dLCEV1rdyFt00uej3w2jDVBuTlnWCldHK7HM1VY59 aF//U7uWWSJbmflYZ9j+f92PN612KFx7599Uh1s3LgcwPPrc8eDnkrL5O69Ofzdf1a/rx4Pe 6QbzdpSb17yLnbvMNOkPq4XEfa6lMc+8JypM/D7pbHiIpFDeRFGRNyt2VV9WsElyeOCtxFKc kWioxVxUnAgA6oa5ByUEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrMLMWRmVeSWpSXmKPExsWy7bCSvK563tQkg/1XpCwezNvGZvHy51U2 i2svL7BbTPvwk9ni8n5ti/lHzrFa9L14yGyx6fE1VouHr8ItLu+aw2YxYdU3Fovu6zvYLJYf /8dksWjrF3aL1r1H2C123jnB7CDgcfmKt8emVZ1sHneu7WHz2Lyk3uPj01ssHn1bVjF6/Gua y+7xeZOcR/uBbqYAzigum5TUnMyy1CJ9uwSujK6eLewF69gqli86xdzAuIW1i5GTQ0LARGLt obNMXYxcHEICOxglVqyayQ6RkJa4vnEClC0ssfLfczBbSKCJSWLPCk0Qm01AW+Lu9C1MILaI QDujxP3tbCA2s8AdJolVPSIgtrCAq8TsuY9YQGwWAVWJqTvng9XzCthIbDx6HuoIeYnVGw4w g9icArYS3RtPM0HsspF4fP81ywRGvgWMDKsYJVMLinPTc4sNC4zyUsv1ihNzi0vz0vWS83M3 MYLDXUtrB+OeVR/0DjEycTAeYpTgYFYS4bWKmJokxJuSWFmVWpQfX1Sak1p8iFGag0VJnPdC 18l4IYH0xJLU7NTUgtQimCwTB6dUA1NpgGWTtfzNL1d2BjJ2lgvHTjbWyllz//e++9NX5Mc+ U9PM/BwyTYfniI8Md+y382t7XvwyubL4w8nJ86Mnvfp2rdtbdv2H57dZd3KVHC39YW78ZmI1 f9D1oJmMh1Uzyr+vSue26fCXiDdrTuTp9npzzc/0oub3zSoH1MNeHldI3dS+6MWJzQuvpzxz ELz+ONP5tXLaLgFxkfao6B8bD8+Yd6VxZfHSqwenm6dNTy3Z06J+SFV1suKuoBlLtwuus2Bb oHjvYUxi2yuuHWtTxc++vngi5UNK4QRVvcijcmr7JMOuTJFdMH12gf6NWbfmdTqprQ+Zsd7R vWx72DzDd9nLln0u231x89UEn6B5ObapSizFGYmGWsxFxYkAePRM4uYCAAA= X-CMS-MailID: 20220531012351epcas5p389e28e28a48f9bb14a52fc81c417296d X-Msg-Generator: CA CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220531012351epcas5p389e28e28a48f9bb14a52fc81c417296d References: <20220531012220.80563-1-alim.akhtar@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Adds tesla,fsd-ufs compatible for Tesla FSD SoC. Cc: linux-fsd@tesla.com Signed-off-by: Bharat Uppal Signed-off-by: Alim Akhtar --- Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml index c949eb617313..2c715eec48b8 100644 --- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml @@ -21,6 +21,7 @@ properties: - samsung,exynos7-ufs - samsung,exynosautov9-ufs - samsung,exynosautov9-ufs-vh + - tesla,fsd-ufs reg: items: From patchwork Tue May 31 01:22:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 577698 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55AD3C433EF for ; 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Tue, 31 May 2022 01:23:56 +0000 (GMT) Received: from epsmgms1p2.samsung.com (unknown [182.195.42.42]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20220531012356epsmtrp2a2343259f48e5fd9f8f8cd0e86a169b0~0DBJ5ave-2334523345epsmtrp2H; Tue, 31 May 2022 01:23:56 +0000 (GMT) X-AuditID: b6c32a4b-213ff70000002622-ec-62956e2d6a0d Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id 54.E7.08924.C2E65926; Tue, 31 May 2022 10:23:56 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220531012354epsmtip2e196cfc9b9eaccacbcf04cc720ef3495~0DBHqNe8D0656506565epsmtip2T; Tue, 31 May 2022 01:23:54 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, linux-phy@lists.infradead.org Cc: devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, avri.altman@wdc.com, bvanassche@acm.org, martin.petersen@oracle.com, chanho61.park@samsung.com, pankaj.dubey@samsung.com, Alim Akhtar , linux-fsd@tesla.com, Bharat Uppal Subject: [PATCH 5/6] ufs: host: ufs-exynos: add support for fsd ufs hci Date: Tue, 31 May 2022 06:52:19 +0530 Message-Id: <20220531012220.80563-6-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220531012220.80563-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprAJsWRmVeSWpSXmKPExsWy7bCmhq5u3tQkg4Y7bBYP5m1js3j58yqb xbWXF9gtpn34yWxxeb+2xfwj51gt+l48ZLbY9Pgaq8XDV+EWl3fNYbOYsOobi0X39R1sFsuP /2OyWLT1C7tF694j7BY775xgdhDwuHzF22PTqk42jzvX9rB5bF5S7/Hx6S0Wj74tqxg9/jXN Zff4vEnOo/1AN1MAZ1S2TUZqYkpqkUJqXnJ+SmZeuq2Sd3C8c7ypmYGhrqGlhbmSQl5ibqqt kotPgK5bZg7QD0oKZYk5pUChgMTiYiV9O5ui/NKSVIWM/OISW6XUgpScApMCveLE3OLSvHS9 vNQSK0MDAyNToMKE7IxDS1czF6wxr+jd4tDA+EK3i5GTQ0LARGLZxynsXYxcHEICuxklvuxt YIFwPjFKnNzYwAThfGaUeNP4jB2mZeqzBcwQiV2MEs3v/jFCOC1MEl/a9rGAVLEJaEvcnb4F rF1EoJlR4mDHLjCHWeAck8SzvRuYQKqEBdwl/sw9D9bBIqAqMaN/LRuIzStgI9F3rZ0JYp+8 xOoNB5hBbE4BW4nujafBBkkIzOSQWLH6CCtEkYvEhOMnoBqEJV4d3wJ1rJTE53d7gYZyANke Eov+SEGEMyTeLl/PCGHbSxy4MocFpIRZQFNi/S59kDCzAJ9E7+8nTBCdvBIdbUIQ1apAD19l gbClJSZ2d0Md4CFx89VxsOuFBCYwSuy5Wj6BUXYWwtAFjIyrGCVTC4pz01OLTQuM81LL4RGV nJ+7iRGcNLW8dzA+evBB7xAjEwfjIUYJDmYlEV6riKlJQrwpiZVVqUX58UWlOanFhxhNgSE2 kVlKNDkfmLbzSuINTSwNTMzMzEwsjc0MlcR5Bf43JgkJpCeWpGanphakFsH0MXFwSjUw7euZ PUHxZ//3SbYNG04w39TK+aG6eMGtkrnpYb/e/5rLwHVna1mBvQ2DGuudla7vzL66TSz+9tGr M9Pm4mn9q3oaRrNOfZ5tPe/tm9YbR0o3Vx7sPGz6/PJenZLHmyNtf65nzL8q3fYrdv/Sq/wd ocYnT/84KrGk52C5591O5Q87pwUf7hK6apD/x63lfenLH1Hud+06HGTfFs613RzQrG1ZLHxu 8cxlLTM5w+8VXJghZne5Qt7LRP7Y/QNKQpxin/su1974y8lcLH5c7kBj+JmCnSbi69ONqrZr Sm1+YbKsuaTtIGNV3dd/xy/1Jn2XP3v2wgSGrvXKIcmL1v97pPe9OeXSSmMFuxehftfNNyix FGckGmoxFxUnAgD3EZgHIwQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrELMWRmVeSWpSXmKPExsWy7bCSvK5O3tQkg+/f5S0ezNvGZvHy51U2 i2svL7BbTPvwk9ni8n5ti/lHzrFa9L14yGyx6fE1VouHr8ItLu+aw2YxYdU3Fovu6zvYLJYf /8dksWjrF3aL1r1H2C123jnB7CDgcfmKt8emVZ1sHneu7WHz2Lyk3uPj01ssHn1bVjF6/Gua y+7xeZOcR/uBbqYAzigum5TUnMyy1CJ9uwSujENLVzMXrDGv6N3i0MD4QreLkZNDQsBEYuqz BcwgtpDADkaJ31cVIOLSEtc3TmCHsIUlVv57DmRzAdU0MUm8mbmaCSTBJqAtcXf6FjBbRKCd UeL+djYQm1ngDpPEqh4REFtYwF3iz9zzLCA2i4CqxIz+tWA1vAI2En3X2pkgFshLrN5wAOwI TgFbie6Np5kgDrKReHz/NcsERr4FjAyrGCVTC4pz03OLDQuM8lLL9YoTc4tL89L1kvNzNzGC g11LawfjnlUf9A4xMnEwHmKU4GBWEuG1ipiaJMSbklhZlVqUH19UmpNafIhRmoNFSZz3QtfJ eCGB9MSS1OzU1ILUIpgsEwenVAOTTO427fMsi1IqDyg5mU2emdT3OaFV8kyWV/b1mXv9j09Y XhdZp76L7V6zfTRL0H7X4+XcAXM818yTEJ783/oee6Nn7ibzxPXLpHzDEv6d38u7IWxhaZyW S623Dd9qVp7Nr8NCr8tv4tLLNP/zdnfmRbavc+J81rPpX9D6E/9hexaf9vWZiuvmeVyIirJU Y4/UTI5aubqkfRuvnN89xledZcH73HIq/XvjZz+8803nVrl7rCm/6zaD6LcrHR9K+T3lnxLF dfib+N/1SzwzcuwtvRSjBDIuGMVy7Tkayf8xS9slKjt52u5l9gz1693sPnuGX5y6O/Kv5O2q FdXskXuzBbMM2pefLohqXsYjpMRSnJFoqMVcVJwIABKdi9PlAgAA X-CMS-MailID: 20220531012356epcas5p3cd6638d4d3eccb28a28d064c9f585a4f X-Msg-Generator: CA CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220531012356epcas5p3cd6638d4d3eccb28a28d064c9f585a4f References: <20220531012220.80563-1-alim.akhtar@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Adds support of UFS HCI which is found in Tesla FSD SoC. FSD also have an addition bit for MPHY APB clock which was not there (was reserved) for previous exynos SoC. Cc: linux-fsd@tesla.com Signed-off-by: Bharat Uppal Signed-off-by: Alim Akhtar --- drivers/ufs/host/ufs-exynos.c | 143 +++++++++++++++++++++++++++++++++- 1 file changed, 142 insertions(+), 1 deletion(-) diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index a81d8cbd542f..b3efdc4caca2 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -52,11 +52,12 @@ #define HCI_ERR_EN_DME_LAYER 0x88 #define HCI_CLKSTOP_CTRL 0xB0 #define REFCLKOUT_STOP BIT(4) +#define MPHY_APBCLK_STOP BIT(3) #define REFCLK_STOP BIT(2) #define UNIPRO_MCLK_STOP BIT(1) #define UNIPRO_PCLK_STOP BIT(0) #define CLK_STOP_MASK (REFCLKOUT_STOP | REFCLK_STOP |\ - UNIPRO_MCLK_STOP |\ + UNIPRO_MCLK_STOP | MPHY_APBCLK_STOP|\ UNIPRO_PCLK_STOP) #define HCI_MISC 0xB4 #define REFCLK_CTRL_EN BIT(7) @@ -386,6 +387,104 @@ static int exynos7_ufs_post_pwr_change(struct exynos_ufs *ufs, return 0; } +static inline int fsd_ufs_pre_link(struct exynos_ufs *ufs) +{ + int i; + struct ufs_hba *hba = ufs->hba; + + ufshcd_dme_set(hba, UIC_ARG_MIB(0x9514), 1000000000L / ufs->mclk_rate); + ufshcd_dme_set(hba, UIC_ARG_MIB(0x201), 0x12); + ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); + + for_each_ufs_tx_lane(ufs, i) { + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0xAA, i), 1000000000L / ufs->mclk_rate); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x8F, i), 0x3F); + } + + for_each_ufs_rx_lane(ufs, i) { + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x12, i), 1000000000L / ufs->mclk_rate); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x5C, i), 0x38); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x0F, i), 0x0); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x65, i), 0x1); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x69, i), 0x1); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x21, i), 0x0); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x22, i), 0x0); + } + + ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); + ufshcd_dme_set(hba, UIC_ARG_MIB(0x9536), 0x4E20); + ufshcd_dme_set(hba, UIC_ARG_MIB(0x9564), 0x2e820183); + ufshcd_dme_set(hba, UIC_ARG_MIB(0x155E), 0x0); + ufshcd_dme_set(hba, UIC_ARG_MIB(0x3000), 0x0); + ufshcd_dme_set(hba, UIC_ARG_MIB(0x3001), 0x1); + ufshcd_dme_set(hba, UIC_ARG_MIB(0x4021), 0x1); + ufshcd_dme_set(hba, UIC_ARG_MIB(0x4020), 0x1); + + return 0; +} + +static inline int fsd_ufs_post_link(struct exynos_ufs *ufs) +{ + int i; + struct ufs_hba *hba = ufs->hba; + u32 hw_cap_min_tactivate; + u32 peer_rx_min_actv_time_cap; + u32 max_rx_hibern8_time_cap; + + ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(0x8F, 4), + &hw_cap_min_tactivate); /* HW Capability of MIN_TACTIVATE */ + ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A8), + &peer_rx_min_actv_time_cap); /* PA_TActivate */ + ufshcd_dme_get(hba, UIC_ARG_MIB(0x15A7), + &max_rx_hibern8_time_cap); /* PA_Hibern8Time */ + + if (peer_rx_min_actv_time_cap >= hw_cap_min_tactivate) + ufshcd_dme_peer_set(hba, UIC_ARG_MIB(0x15A8), + peer_rx_min_actv_time_cap + 1); + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A7), max_rx_hibern8_time_cap + 1); + + ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x01); + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15A4), 0xFA); + ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x00); + + ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40); + + for_each_ufs_rx_lane(ufs, i) { + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x35, i), 0x05); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x73, i), 0x01); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x41, i), 0x02); + ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x42, i), 0xAC); + } + + ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0); + + return 0; +} + +static inline int fsd_ufs_pre_pwr_change(struct exynos_ufs *ufs, + struct ufs_pa_layer_attr *pwr) +{ + struct ufs_hba *hba = ufs->hba; + + ufshcd_dme_set(hba, UIC_ARG_MIB(0x1569), 0x1); + ufshcd_dme_set(hba, UIC_ARG_MIB(0x1584), 0x1); + ufshcd_dme_set(hba, UIC_ARG_MIB(0x2041), 8064); + ufshcd_dme_set(hba, UIC_ARG_MIB(0x2042), 28224); + ufshcd_dme_set(hba, UIC_ARG_MIB(0x2043), 20160); + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B0), 12000); + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B1), 32000); + ufshcd_dme_set(hba, UIC_ARG_MIB(0x15B2), 16000); + + unipro_writel(ufs, 8064, 0x7888); + unipro_writel(ufs, 28224, 0x788C); + unipro_writel(ufs, 20160, 0x7890); + unipro_writel(ufs, 12000, 0x78B8); + unipro_writel(ufs, 32000, 0x78BC); + unipro_writel(ufs, 16000, 0x78C0); + + return 0; +} + /* * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w * Control should be disabled in the below cases @@ -1595,6 +1694,46 @@ static struct exynos_ufs_drv_data exynos_ufs_drvs = { .post_pwr_change = exynos7_ufs_post_pwr_change, }; +static struct exynos_ufs_uic_attr fsd_uic_attr = { + .tx_trailingclks = 0x10, + .tx_dif_p_nsec = 3000000, /* unit: ns */ + .tx_dif_n_nsec = 1000000, /* unit: ns */ + .tx_high_z_cnt_nsec = 20000, /* unit: ns */ + .tx_base_unit_nsec = 100000, /* unit: ns */ + .tx_gran_unit_nsec = 4000, /* unit: ns */ + .tx_sleep_cnt = 1000, /* unit: ns */ + .tx_min_activatetime = 0xa, + .rx_filler_enable = 0x2, + .rx_dif_p_nsec = 1000000, /* unit: ns */ + .rx_hibern8_wait_nsec = 4000000, /* unit: ns */ + .rx_base_unit_nsec = 100000, /* unit: ns */ + .rx_gran_unit_nsec = 4000, /* unit: ns */ + .rx_sleep_cnt = 1280, /* unit: ns */ + .rx_stall_cnt = 320, /* unit: ns */ + .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf), + .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf), + .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf), + .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf), + .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf), + .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf), + .pa_dbg_option_suite = 0x2E820183, +}; + +struct exynos_ufs_drv_data fsd_ufs_drvs = { + .uic_attr = &fsd_uic_attr, + .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN | + UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR | + UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR | + UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR, + .opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL | + EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL | + EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR | + EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX, + .pre_link = fsd_ufs_pre_link, + .post_link = fsd_ufs_post_link, + .pre_pwr_change = fsd_ufs_pre_pwr_change, +}; + static const struct of_device_id exynos_ufs_of_match[] = { { .compatible = "samsung,exynos7-ufs", .data = &exynos_ufs_drvs }, @@ -1602,6 +1741,8 @@ static const struct of_device_id exynos_ufs_of_match[] = { .data = &exynosauto_ufs_drvs }, { .compatible = "samsung,exynosautov9-ufs-vh", .data = &exynosauto_ufs_vh_drvs }, + { .compatible = "tesla,fsd-ufs", + .data = &fsd_ufs_drvs }, {}, }; From patchwork Tue May 31 01:22:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alim Akhtar X-Patchwork-Id: 578426 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBFACC433EF for ; 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Tue, 31 May 2022 01:24:00 +0000 (GMT) Received: from epsmgms1p2.samsung.com (unknown [182.195.42.42]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20220531012400epsmtrp26af95bbb0198d4c767cba8093e9ccbdc~0DBN0TsLa2336523365epsmtrp2J; Tue, 31 May 2022 01:24:00 +0000 (GMT) X-AuditID: b6c32a49-4cbff7000000274f-cf-62956e3181c9 Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgms1p2.samsung.com (Symantec Messaging Gateway) with SMTP id 08.E7.08924.03E65926; Tue, 31 May 2022 10:24:00 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.108.73.139]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220531012358epsmtip25d577968a0c855a2a15e88600739b30f~0DBLbqcdK1203612036epsmtip2B; Tue, 31 May 2022 01:23:58 +0000 (GMT) From: Alim Akhtar To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, linux-phy@lists.infradead.org Cc: devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, vkoul@kernel.org, avri.altman@wdc.com, bvanassche@acm.org, martin.petersen@oracle.com, chanho61.park@samsung.com, pankaj.dubey@samsung.com, Alim Akhtar , linux-fsd@tesla.com, Bharat Uppal Subject: [PATCH 6/6] arm64: dts: fsd: add ufs device node Date: Tue, 31 May 2022 06:52:20 +0530 Message-Id: <20220531012220.80563-7-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220531012220.80563-1-alim.akhtar@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprAJsWRmVeSWpSXmKPExsWy7bCmuq5h3tQkg1fTJSwezNvGZvHy51U2 i2svL7BbTPvwk9ni8n5ti/lHzrFa9L14yGyx6fE1VouHr8ItLu+aw2YxYdU3Fovu6zvYLJYf /8dksWjrF3aL1r1H2C123jnB7CDgcfmKt8emVZ1sHneu7WHz2Lyk3uPj01ssHn1bVjF6/Gua y+7xeZOcR/uBbqYAzqhsm4zUxJTUIoXUvOT8lMy8dFsl7+B453hTMwNDXUNLC3MlhbzE3FRb JRefAF23zBygH5QUyhJzSoFCAYnFxUr6djZF+aUlqQoZ+cUltkqpBSk5BSYFesWJucWleel6 eaklVoYGBkamQIUJ2Rnfzm5gL3ghXnFy6Q7mBsaTwl2MnBwSAiYSvxvmM3cxcnEICexmlFjy bhMLhPOJUeLTmjlQzmdGiWdnDjPCtFy5tZEJIrGLUaL5wTsmkISQQAuTxLdtPCA2m4C2xN3p W8CKRASaGSUOduwCc5gFzjFJPNu7AaxDWMBSYv7BhWwgNouAqsSd13/BVvAK2Eh0bD/OCrFO XmL1hgPMIDangK1E98bTYIMkBOZySOyf9hfoQA4gx0Xi9xcFiHphiVfHt7BD2FISn9/tZYMo 8ZBY9EcKIpwh8Xb5eqhv7CUOXJkDNoVZQFNi/S59kDCzAJ9E7+8nTBCdvBIdbUIQ1aoSze+u skDY0hITu7uhjvSQuL7iCDQYJzBKTHr2mmUCo+wshKkLGBlXMUqmFhTnpqcWmxYY5qWWwyMq OT93EyM4aWp57mC8++CD3iFGJg7GQ4wSHMxKIrxWEVOThHhTEiurUovy44tKc1KLDzGaAkNs IrOUaHI+MG3nlcQbmlgamJiZmZlYGpsZKonzCvxvTBISSE8sSc1OTS1ILYLpY+LglGpg8v0r N2VR4PVlDp6Z//bOZJJaoiDy94Tk4teuLfVCOz9fXrx7s98mW2meHxWzpgVXiB2/rRM6U2fS Sd01GUEMmRqTbvJP38tw+urBbI6y9396BcTyL+1OnbTShdHUP3na0fbM7+Zij5N0Zh5dyf/t A2MA25452Qbr5Vnv3YuuzbG9JRMoOPtB7vob3/K8dnkwyGkXBt0qzW1dbnv3bbDMTMmvmlnJ CZu+ftHokckx0XATfHXss5Xfx2dam/Nq9i2I33I1+mftqR2bzx+Y09KwdJVCllq375UX7r4n eI3udUwMPyDFOy3utJigmi7Lt38zNO3Fmbd+n1r5xsy+fuEa5g3yMmd4A7XzqgIumPN+VGIp zkg01GIuKk4EAG8aQsQjBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrMLMWRmVeSWpSXmKPExsWy7bCSvK5B3tQkg20r9CwezNvGZvHy51U2 i2svL7BbTPvwk9ni8n5ti/lHzrFa9L14yGyx6fE1VouHr8ItLu+aw2YxYdU3Fovu6zvYLJYf /8dksWjrF3aL1r1H2C123jnB7CDgcfmKt8emVZ1sHneu7WHz2Lyk3uPj01ssHn1bVjF6/Gua y+7xeZOcR/uBbqYAzigum5TUnMyy1CJ9uwSujG9nN7AXvBCvOLl0B3MD40nhLkZODgkBE4kr tzYygdhCAjsYJabvcoeIS0tc3ziBHcIWllj57zmQzQVU08QksXHbNFaQBJuAtsTd6VvAmkUE 2hkl7m9nA7GZBe4wSazqEQGxhQUsJeYfXAgWZxFQlbjz+i8jiM0rYCPRsf04K8QCeYnVGw4w g9icArYS3RtPQx1kI/H4/muWCYx8CxgZVjFKphYU56bnFhsWGOWllusVJ+YWl+al6yXn525i BIe7ltYOxj2rPugdYmTiYDzEKMHBrCTCaxUxNUmINyWxsiq1KD++qDQntfgQozQHi5I474Wu k/FCAumJJanZqakFqUUwWSYOTqkGJsfzYs4/NwtOYvGxyXo1ref36hM3PII2NXL5qpUzhh1K eH3nX8K7sIWdOQtjzStm7zFU2le9ZYbPhqV5Np4+mv7mPgIuV13eeFSp62tOs5rfwcb47ULM i97Dc+fFC/O+Zj07b7/xslUH92q5fyyc2B6mIdy0VeTx2d0FiQ93e3G0fXOYUcXKvlM+N9FU 1ubTrQyLOecfzlctXvv0v9vypnUzlFJjC20F5zXlTGjpV1rxnOWoh+a/cD3N4qsa0xxPSlku 1lkt5im14afDn2f/J3nqRd8teLvX4aRkuv+SY9Mu5SfxT9jZJLtty866XPWg1EmsnKyW2ZkP r6tzX0m2/qKa6xH16PvEy9bb9ogYKLEUZyQaajEXFScCADIDpGrmAgAA X-CMS-MailID: 20220531012400epcas5p1c30b75a928097bd19855dcd0d929ff10 X-Msg-Generator: CA CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220531012400epcas5p1c30b75a928097bd19855dcd0d929ff10 References: <20220531012220.80563-1-alim.akhtar@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Adds FSD ufs device node and enable the same for fsd board. This also adds the required pin configuration for the same. Cc: linux-fsd@tesla.com Signed-off-by: Bharat Uppal Signed-off-by: Alim Akhtar --- arch/arm64/boot/dts/tesla/fsd-evb.dts | 4 +++ arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 14 +++++++++++ arch/arm64/boot/dts/tesla/fsd.dtsi | 29 ++++++++++++++++++++++ 3 files changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts index 5af560c1b5e6..1db6ddf03f01 100644 --- a/arch/arm64/boot/dts/tesla/fsd-evb.dts +++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts @@ -37,3 +37,7 @@ &fin_pll { &serial_0 { status = "okay"; }; + +&ufs { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi index d4d0cb005712..387a41e251d5 100644 --- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi @@ -50,6 +50,20 @@ gpf5: gpf5-gpio-bank { interrupt-controller; #interrupt-cells = <2>; }; + + ufs_rst_n: ufs-rst-n-pins { + samsung,pins = "gpf5-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + ufs_refclk_out: ufs-refclk-out-pins { + samsung,pins = "gpf5-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; }; &pinctrl_peric { diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index af39655331de..a5972e9a2585 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -740,6 +740,35 @@ timer@10040000 { clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>; clock-names = "fin_pll", "mct"; }; + + ufs: ufs@15120000 { + compatible = "tesla,fsd-ufs"; + reg = <0x0 0x15120000 0x0 0x200>, /* 0: HCI standard */ + <0x0 0x15121100 0x0 0x200>, /* 1: Vendor specified */ + <0x0 0x15110000 0x0 0x8000>, /* 2: UNIPRO */ + <0x0 0x15130000 0x0 0x100>; /* 3: UFS protector */ + reg-names = "hci", "vs_hci", "unipro", "ufsp"; + interrupts = ; + clocks = <&clock_fsys0 UFS0_TOP0_HCLK_BUS>, + <&clock_fsys0 UFS0_TOP0_CLK_UNIPRO>; + clock-names = "core_clk", "sclk_unipro_main"; + freq-table-hz = <0 0>, <0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; + phys = <&ufs_phy>; + phy-names = "ufs-phy"; + status = "disabled"; + }; + + ufs_phy: ufs-phy@15124000 { + compatible = "tesla,fsd-ufs-phy"; + reg = <0x0 0x15124000 0x0 0x800>; + reg-names = "phy-pma"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <0>; + clocks = <&clock_fsys0 UFS0_MPHY_REFCLK_IXTAL26>; + clock-names = "ref_clk"; + }; }; };