From patchwork Thu May 26 20:44:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 576715 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66581C433EF for ; Thu, 26 May 2022 20:44:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349161AbiEZUom (ORCPT ); Thu, 26 May 2022 16:44:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236012AbiEZUoX (ORCPT ); Thu, 26 May 2022 16:44:23 -0400 Received: from mail-ed1-x529.google.com (mail-ed1-x529.google.com [IPv6:2a00:1450:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6EF3946149 for ; Thu, 26 May 2022 13:44:07 -0700 (PDT) Received: by mail-ed1-x529.google.com with SMTP id t26so3203424edt.0 for ; Thu, 26 May 2022 13:44:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=qgzdTe7fcPDB2gZCUSY8XDUZGwLpeoTk6dRLrKInLZw=; b=nfHEhi7ujlgHOW7VWTy7u/ez0jnBhNWYtx7YskXCH2/UMTlUXvVqZ8r4hDdc+eccdZ eDQJSL5qDd4CHFuv5+VR0rJBcZQwBLEhXoXQxcWSwoO5DPbdMWv6cBbwraUVhbzLHGFl YFEF6FjrPWGOCtI48xOZQV/AWbmpKgL2yntfvgn3Pi9fKgofLL9X6i3RjWbtgescg4A2 J7zFnkfDvfRGJF1aPlerzZJWjlDQtLz/2g34UhyhB+KvpnNIW3qXfYGv3Ozf0JR1Oq1E VETk/7mEwjWgVTAgIgbPjLEmhRCgqlqHaW7tm5FOLqZK0WnqmLJgsSuMxGMMNCSNhEKd Y50Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=qgzdTe7fcPDB2gZCUSY8XDUZGwLpeoTk6dRLrKInLZw=; b=aKT8lteOkJW8EffLAqgg0U36c7b1wly57Zvb1369VnWKbJbkCmu6dL/NOJXytnu84t oIYCa6MZBkinRrQ35K1rh2KABW/5tnDbYIp0wVcwHGPCQFZFaFb2HoW2yI05/FDAitua DjIz0DbKeRGMFPZWjDMh8V4p2zOedm/OZlr5uUFbE1AdRCdCMq5+9N687lNkqld8OxKD 9NwnzIYZWZNj6y1Sm4u9VsVjpSdHdUaG/3vs/hbnhG4YYIIzmgForroZzjS7zeJ2LCOW fBLK2J18AAMxpHouxXbpjgy3rCiSKPpW7aWQ6KIQFe+YCStDN3u1czkyiQ2t/FC0MQF0 45vw== X-Gm-Message-State: AOAM533WGemrIKOIBWxPAzxc4O/k8pUpxriDyybjSgDh5zWQBrAUu2dV dF4gYA05Q6pF/b/v/pr1z6msog== X-Google-Smtp-Source: ABdhPJzmbatH19Rfb7UpYoZN8s5POPS+jX9M0kXvrf1DSf2MQ6Y2AyfXy9WcElSAeYt6XR2aaTKIyg== X-Received: by 2002:a50:ed18:0:b0:42b:b880:3f27 with SMTP id j24-20020a50ed18000000b0042bb8803f27mr12083288eds.187.1653597845910; Thu, 26 May 2022 13:44:05 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-176-92.adslplus.ch. [188.155.176.92]) by smtp.gmail.com with ESMTPSA id i15-20020a1709061ccf00b006fec5cef701sm803475ejh.197.2022.05.26.13.44.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 13:44:05 -0700 (PDT) From: Krzysztof Kozlowski To: Arnd Bergmann , Olof Johansson , arm@kernel.org, soc@kernel.org, Matthias Brugger , Rob Herring , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 1/2] arm64: dts: mediatek: adjust whitespace around '=' Date: Thu, 26 May 2022 22:44:01 +0200 Message-Id: <20220526204402.832393-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski --- Output compared with dtx_diff and fdtdump. --- arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 2 +- .../boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 8 ++++---- arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 8 ++++---- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 10 +++++----- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 4 ++-- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 12 ++++++------ arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 12 ++++++------ arch/arm64/boot/dts/mediatek/mt8173.dtsi | 8 ++++---- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 8 ++++---- arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 8 ++++---- 10 files changed, 40 insertions(+), 40 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts index 11aa135aa0f3..9b1af9c80130 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts @@ -106,7 +106,7 @@ &cpu2 { }; ð { - phy-mode ="rgmii-rxid"; + phy-mode = "rgmii-rxid"; phy-handle = <ðernet_phy0>; mediatek,tx-delay-ps = <1530>; snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts index 2b9bf8dd14ec..ada06d3de1c9 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts @@ -336,14 +336,14 @@ mux { i2c1_pins: i2c1-pins { mux { function = "i2c"; - groups = "i2c1_0"; + groups = "i2c1_0"; }; }; i2c2_pins: i2c2-pins { mux { function = "i2c"; - groups = "i2c2_0"; + groups = "i2c2_0"; }; }; @@ -366,14 +366,14 @@ conf { irrx_pins: irrx-pins { mux { function = "ir"; - groups = "ir_1_rx"; + groups = "ir_1_rx"; }; }; irtx_pins: irtx-pins { mux { function = "ir"; - groups = "ir_1_tx"; + groups = "ir_1_tx"; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts index 596c073d8b05..3ee392d805d8 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts @@ -298,14 +298,14 @@ mux { i2c1_pins: i2c1-pins { mux { function = "i2c"; - groups = "i2c1_0"; + groups = "i2c1_0"; }; }; i2c2_pins: i2c2-pins { mux { function = "i2c"; - groups = "i2c2_0"; + groups = "i2c2_0"; }; }; @@ -328,14 +328,14 @@ conf { irrx_pins: irrx-pins { mux { function = "ir"; - groups = "ir_1_rx"; + groups = "ir_1_rx"; }; }; irtx_pins: irtx-pins { mux { function = "ir"; - groups = "ir_1_tx"; + groups = "ir_1_tx"; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index dbcee8b4d8d8..146e18b5b1f4 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -118,8 +118,8 @@ clk25m: oscillator { }; psci { - compatible = "arm,psci-0.2"; - method = "smc"; + compatible = "arm,psci-0.2"; + method = "smc"; }; pmu { @@ -616,9 +616,9 @@ audsys: clock-controller@11220000 { afe: audio-controller { compatible = "mediatek,mt7622-audio"; - interrupts = , - ; - interrupt-names = "afe", "asys"; + interrupts = , + ; + interrupt-names = "afe", "asys"; clocks = <&infracfg CLK_INFRA_AUDIO_PD>, <&topckgen CLK_TOP_AUD1_SEL>, diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index d2636a0ed152..e3a407d03551 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -57,8 +57,8 @@ cpu3: cpu@3 { }; psci { - compatible = "arm,psci-0.2"; - method = "smc"; + compatible = "arm,psci-0.2"; + method = "smc"; }; reserved-memory { diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index 9c75fbb31f98..0d8f9459e35d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -300,8 +300,8 @@ da9211_vcpu_reg: BUCKA { regulator-name = "VBUCKA"; regulator-min-microvolt = < 700000>; regulator-max-microvolt = <1310000>; - regulator-min-microamp = <2000000>; - regulator-max-microamp = <4400000>; + regulator-min-microamp = <2000000>; + regulator-max-microamp = <4400000>; regulator-ramp-delay = <10000>; regulator-always-on; regulator-allowed-modes = ; regulator-max-microvolt = <1310000>; - regulator-min-microamp = <2000000>; - regulator-max-microamp = <3000000>; + regulator-min-microamp = <2000000>; + regulator-max-microamp = <3000000>; regulator-ramp-delay = <10000>; }; }; @@ -374,8 +374,8 @@ &mmc0 { mmc-hs400-1_8v; cap-mmc-hw-reset; hs400-ds-delay = <0x14015>; - mediatek,hs200-cmd-int-delay=<30>; - mediatek,hs400-cmd-int-delay=<14>; + mediatek,hs200-cmd-int-delay = <30>; + mediatek,hs400-cmd-int-delay = <14>; mediatek,hs400-cmd-resp-sel-rising; vmmc-supply = <&mt6397_vemc_3v3_reg>; vqmmc-supply = <&mt6397_vio18_reg>; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 4fa1e93302c7..0b5f154007be 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -122,8 +122,8 @@ da9211_vcpu_reg: BUCKA { regulator-name = "VBUCKA"; regulator-min-microvolt = < 700000>; regulator-max-microvolt = <1310000>; - regulator-min-microamp = <2000000>; - regulator-max-microamp = <4400000>; + regulator-min-microamp = <2000000>; + regulator-max-microamp = <4400000>; regulator-ramp-delay = <10000>; regulator-always-on; }; @@ -132,8 +132,8 @@ da9211_vgpu_reg: BUCKB { regulator-name = "VBUCKB"; regulator-min-microvolt = < 700000>; regulator-max-microvolt = <1310000>; - regulator-min-microamp = <2000000>; - regulator-max-microamp = <3000000>; + regulator-min-microamp = <2000000>; + regulator-max-microamp = <3000000>; regulator-ramp-delay = <10000>; }; }; @@ -148,8 +148,8 @@ &mmc0 { bus-width = <8>; max-frequency = <50000000>; cap-mmc-highspeed; - mediatek,hs200-cmd-int-delay=<26>; - mediatek,hs400-cmd-int-delay=<14>; + mediatek,hs200-cmd-int-delay = <26>; + mediatek,hs400-cmd-int-delay = <14>; mediatek,hs400-cmd-resp-sel-rising; vmmc-supply = <&mt6397_vemc_3v3_reg>; vqmmc-supply = <&mt6397_vio18_reg>; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 40d7b47fc52e..5e903ab5884c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -246,9 +246,9 @@ pmu_a72 { psci { compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; method = "smc"; - cpu_suspend = <0x84000001>; - cpu_off = <0x84000002>; - cpu_on = <0x84000003>; + cpu_suspend = <0x84000001>; + cpu_off = <0x84000002>; + cpu_on = <0x84000003>; }; clk26m: oscillator0 { @@ -1505,7 +1505,7 @@ larb5: larb@19001000 { vcodec_enc_vp8: vcodec@19002000 { compatible = "mediatek,mt8173-vcodec-enc-vp8"; - reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ + reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ interrupts = ; iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, <&iommu M4U_PORT_VENC_REC_FRM_SET2>, diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 01e650251928..42b208132a88 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -295,8 +295,8 @@ pmu-a73 { }; psci { - compatible = "arm,psci-1.0"; - method = "smc"; + compatible = "arm,psci-1.0"; + method = "smc"; }; clk26m: oscillator { @@ -504,7 +504,7 @@ power-domain@MT8183_POWER_DOMAIN_CONN { power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC { reg = ; - clocks = <&topckgen CLK_TOP_MUX_MFG>; + clocks = <&topckgen CLK_TOP_MUX_MFG>; clock-names = "mfg"; #address-cells = <1>; #size-cells = <0>; @@ -1150,7 +1150,7 @@ i2c8: i2c@1101b000 { }; ssusb: usb@11201000 { - compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3"; + compatible = "mediatek,mt8183-mtu3", "mediatek,mtu3"; reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; reg-names = "mac", "ippc"; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts index db25a515e420..690dc7717f2c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts @@ -139,19 +139,19 @@ pins { }; &u3phy0 { - status="okay"; + status = "okay"; }; &u3phy1 { - status="okay"; + status = "okay"; }; &u3phy2 { - status="okay"; + status = "okay"; }; &u3phy3 { - status="okay"; + status = "okay"; }; &uart0 { From patchwork Thu May 26 20:43:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 576717 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38DA0C433F5 for ; Thu, 26 May 2022 20:44:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348669AbiEZUoP (ORCPT ); Thu, 26 May 2022 16:44:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54460 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348995AbiEZUnu (ORCPT ); Thu, 26 May 2022 16:43:50 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 28C71E7307 for ; Thu, 26 May 2022 13:43:33 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id gi33so5174504ejc.3 for ; Thu, 26 May 2022 13:43:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2HbAAEhEhYPigEy5cs4rYAx85JfdiA+8XIt4PraJMOg=; b=P8tHOTyqEAgQlFw7egTJOe550Ta1tvdTEeiO1gEXgm9y8ZrqrdORGg3oswlcUyeTxI y0X7KCXz8A+r1De3ccJvte6lWbPYsnPT2De6GGVA6BdU6J0NpcYI7EvZ1uAErnA9yAYv 6PYxVjPcoEHdTEqyTlXdD24RfKWavrpPF5HGfI25elFrNM3eMJRYgzeAY3+62dVcOoMv Rxns0jt1hPUxLIhlkU+SvCQFx+hqLvWuKwpBI9A+bVCk9MKMDkHejJ+uJCW0uL6tMhDB QmlySI77keo7egiGDOxnPa+cjID7uS7PZ3aafB6Z4yUmnCGFWbIE1POak6dMl3Yj+9Ak lyEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2HbAAEhEhYPigEy5cs4rYAx85JfdiA+8XIt4PraJMOg=; b=VILYhlCAbYxgtXnCScfy/0R/ec563APig+/PQR+btNkPGV1GqcXXFBFPeC+8n8p1rJ vVRFjr/z9be2uUPncUdVkpTFbO5eFuuHRGTMPrpmrOdd5MOU0z5JhKI03WuJU+30fCK6 d71DPHiIgWszKBxyYifY5mU9z1LdQdYLvAVTIJbz6E6K445A898hj2djQK/ulP5+vU1/ YxgdiigDxou49ApTvHt1Yy0AZCWMiO99q/gz1KgDBkxQYY/2TwY4+vpDN8c2OSvzGk8H ltpYuyxfmrfDvnr6Gnu83VaN0fqEJadYuG0EzIPbdZQMt6vhZEuinA1smY9c634EQ2X5 /NSQ== X-Gm-Message-State: AOAM5321ytXtq3/9IKrhWYPPbbzZ7Lc2MHiBpVE7fbflieLSGqjNdpcD KTAjCc9Sa/TdhmFxDmAs6lq2Kg== X-Google-Smtp-Source: ABdhPJxHCgn2QBJAFPGldWA5KZJv7wyYzN6zUcA8bMbI7GXutPNmSdMxYiVHIutNpQV32tf5lqpFFA== X-Received: by 2002:a17:906:a383:b0:6f5:132c:1a14 with SMTP id k3-20020a170906a38300b006f5132c1a14mr35985269ejz.21.1653597812346; Thu, 26 May 2022 13:43:32 -0700 (PDT) Received: from localhost.localdomain (xdsl-188-155-176-92.adslplus.ch. [188.155.176.92]) by smtp.gmail.com with ESMTPSA id y11-20020a170906070b00b006fec28bd09fsm816846ejb.22.2022.05.26.13.43.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 13:43:31 -0700 (PDT) From: Krzysztof Kozlowski To: Rob Herring , Krzysztof Kozlowski , Alim Akhtar , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 2/2] ARM: dts: exynos: adjust whitespace around '=' Date: Thu, 26 May 2022 22:43:23 +0200 Message-Id: <20220526204323.832243-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220526204323.832243-1-krzysztof.kozlowski@linaro.org> References: <20220526204323.832243-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski --- Output compared with dtx_diff and fdtdump. --- arch/arm/boot/dts/exynos3250-artik5.dtsi | 2 +- arch/arm/boot/dts/exynos4210-trats.dts | 2 +- arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi | 2 +- arch/arm/boot/dts/exynos5.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi index 7b429622a288..0ac3f284fbb8 100644 --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi @@ -357,7 +357,7 @@ &mshc_1 { &pinctrl_1 { bten: bten-pins { - samsung,pins ="gpx1-7"; + samsung,pins = "gpx1-7"; samsung,pin-function = ; samsung,pin-pud = ; samsung,pin-con-pdn = ; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 01f44d95f671..b8e9dd23fc51 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -180,7 +180,7 @@ panel@0 { vdd3-supply = <&vcclcd_reg>; vci-supply = <&vlcd_reg>; reset-gpios = <&gpy4 5 GPIO_ACTIVE_HIGH>; - power-on-delay= <50>; + power-on-delay = <50>; reset-delay = <100>; init-delay = <100>; flip-horizontal; diff --git a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi index 03dffc690b79..aa7de6de8e19 100644 --- a/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi +++ b/arch/arm/boot/dts/exynos4412-galaxy-s3.dtsi @@ -107,7 +107,7 @@ panel@0 { vdd3-supply = <&lcd_vdd3_reg>; vci-supply = <&ldo25_reg>; reset-gpios = <&gpf2 1 GPIO_ACTIVE_HIGH>; - power-on-delay= <50>; + power-on-delay = <50>; reset-delay = <100>; init-delay = <100>; flip-horizontal; diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 9ce9fb3fc190..c8da0d4b1b33 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -89,7 +89,7 @@ gic: interrupt-controller@10481000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; #interrupt-cells = <3>; interrupt-controller; - reg = <0x10481000 0x1000>, + reg = <0x10481000 0x1000>, <0x10482000 0x2000>, <0x10484000 0x2000>, <0x10486000 0x2000>;