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[174.21.71.225]) by smtp.gmail.com with ESMTPSA id j11-20020aa7928b000000b0050dc7628133sm3861420pfa.13.2022.05.27.09.48.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 May 2022 09:48:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH v5 01/17] target/m68k: Raise the TRAPn exception with the correct pc Date: Fri, 27 May 2022 09:47:51 -0700 Message-Id: <20220527164807.135038-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220527164807.135038-1-richard.henderson@linaro.org> References: <20220527164807.135038-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rather than adjust the PC in all of the consumers, raise the exception with the correct PC in the first place. Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- linux-user/m68k/cpu_loop.c | 1 - target/m68k/op_helper.c | 9 --------- target/m68k/translate.c | 2 +- 3 files changed, 1 insertion(+), 11 deletions(-) diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index d1bf8548b7..56417f7401 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -56,7 +56,6 @@ void cpu_loop(CPUM68KState *env) { abi_long ret; n = env->dregs[0]; - env->pc += 2; ret = do_syscall(env, n, env->dregs[1], diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 8decc61240..d30f988ae0 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -217,11 +217,6 @@ static void cf_interrupt_all(CPUM68KState *env, int is_hw) cpu_loop_exit(cs); return; } - if (cs->exception_index >= EXCP_TRAP0 - && cs->exception_index <= EXCP_TRAP15) { - /* Move the PC after the trap instruction. */ - retaddr += 2; - } } vector = cs->exception_index << 2; @@ -304,10 +299,6 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) /* Return from an exception. */ m68k_rte(env); return; - case EXCP_TRAP0 ... EXCP_TRAP15: - /* Move the PC after the trap instruction. */ - retaddr += 2; - break; } } diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 4026572ed8..6d6d026e3c 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4860,7 +4860,7 @@ DISAS_INSN(wdebug) DISAS_INSN(trap) { - gen_exception(s, s->base.pc_next, EXCP_TRAP0 + (insn & 0xf)); + gen_exception(s, s->pc, EXCP_TRAP0 + (insn & 0xf)); } static void gen_load_fcr(DisasContext *s, TCGv res, int reg) From patchwork Fri May 27 16:47:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 576521 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:8607:0:0:0:0 with SMTP id bb7csp816101mab; Fri, 27 May 2022 10:04:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzIpik5NVb0QeMadEYYiqiHoDBbzCEzfT50xVESPWDn4LkXR5exIVBXBQB2ZPEr4k11W85C X-Received: by 2002:a37:9284:0:b0:6a3:55a3:81dd with SMTP id u126-20020a379284000000b006a355a381ddmr24276167qkd.316.1653671071637; Fri, 27 May 2022 10:04:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653671071; cv=none; d=google.com; s=arc-20160816; b=aqKp4Hy34jgeh2MN6Fe1qTGidtq4/AFQQcNs5NaWS6T/QrNvUKJPfO5bHVrXV0Z2u5 r/qk1X5rqHgr3UpRl9wFFuXVNHRurM3ekYzw1yiBHMOpmvcciU4BusMhE5dTh6ZsxtIc 5iCDdd3da5eRPT5uaMpDglz/2Fwe6LOFTMLIJ280K28s7STICcui5B/1/faoi8Y3WYYw atAuhmIOzNw3j+NqLznTakQ8IF9iSMySkjGndFHY1nG76QF9rfrNz9UslUvYNiSymzT0 GiUybtfxcrHYHRhzAWzb9xBPfFWZg9KHWT/Mmf3nDQ0QrH6sKXv/c6Y5F6Grhd94hJS/ 8/tQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hV+IA21ry8VojR25e1IAEE42j7p287jopA93G1Fi9U8=; b=cwESKCbeUqq8Fp51gCXlnu+zvieKC7JYRpWNMfnKmBPkkyOKuiA5ZJYRj+PZPsZFdo Q6PGQ3YC9sLjJTOJXPMPVgVwIkEmWIt8I5KUt/i+M/EL5i4CRCE0J1nN3WIroW48M4Wt 8HQ0/j5BJPZ/hw8YrU4CVpvuHV7MQDqHm6mLWd1PgGW8+l4UK4iu1DPVuliu5n4c5YSC Gr4yl7Qq7eKkx7I7kE9JdedphOvs6yG+aI4j7CcZ+cdeSmnc6QMtmBUSyaudKBrEGwhH joNqpuvDBUL16uNntooFOrZwCJODxr5nUyjG/lvhOm+h9mlR1h8F/5yRZejDjLYOsYRn Fjxg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=szRP+MhW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.71.225]) by smtp.gmail.com with ESMTPSA id j11-20020aa7928b000000b0050dc7628133sm3861420pfa.13.2022.05.27.09.48.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 May 2022 09:48:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v5 02/17] target/m68k: Switch over exception type in m68k_interrupt_all Date: Fri, 27 May 2022 09:47:52 -0700 Message-Id: <20220527164807.135038-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220527164807.135038-1-richard.henderson@linaro.org> References: <20220527164807.135038-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Replace an if ladder with a switch for clarity. Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/m68k/op_helper.c | 49 +++++++++++++++++++++++++---------------- 1 file changed, 30 insertions(+), 19 deletions(-) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index d30f988ae0..2b94a6ec84 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -333,7 +333,8 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) sp &= ~1; } - if (cs->exception_index == EXCP_ACCESS) { + switch (cs->exception_index) { + case EXCP_ACCESS: if (env->mmu.fault) { cpu_abort(cs, "DOUBLE MMU FAULT\n"); } @@ -391,29 +392,39 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) "ssw: %08x ea: %08x sfc: %d dfc: %d\n", env->mmu.ssw, env->mmu.ar, env->sfc, env->dfc); } - } else if (cs->exception_index == EXCP_ADDRESS) { + break; + + case EXCP_ADDRESS: do_stack_frame(env, &sp, 2, oldsr, 0, retaddr); - } else if (cs->exception_index == EXCP_ILLEGAL || - cs->exception_index == EXCP_DIV0 || - cs->exception_index == EXCP_CHK || - cs->exception_index == EXCP_TRAPCC || - cs->exception_index == EXCP_TRACE) { + break; + + case EXCP_ILLEGAL: + case EXCP_DIV0: + case EXCP_CHK: + case EXCP_TRAPCC: + case EXCP_TRACE: /* FIXME: addr is not only env->pc */ do_stack_frame(env, &sp, 2, oldsr, env->pc, retaddr); - } else if (is_hw && oldsr & SR_M && - cs->exception_index >= EXCP_SPURIOUS && - cs->exception_index <= EXCP_INT_LEVEL_7) { - do_stack_frame(env, &sp, 0, oldsr, 0, retaddr); - oldsr = sr; - env->aregs[7] = sp; - cpu_m68k_set_sr(env, sr &= ~SR_M); - sp = env->aregs[7]; - if (!m68k_feature(env, M68K_FEATURE_UNALIGNED_DATA)) { - sp &= ~1; + break; + + case EXCP_SPURIOUS ... EXCP_INT_LEVEL_7: + if (is_hw && oldsr & SR_M) { + do_stack_frame(env, &sp, 0, oldsr, 0, retaddr); + oldsr = sr; + env->aregs[7] = sp; + cpu_m68k_set_sr(env, sr &= ~SR_M); + sp = env->aregs[7]; + if (!m68k_feature(env, M68K_FEATURE_UNALIGNED_DATA)) { + sp &= ~1; + } + do_stack_frame(env, &sp, 1, oldsr, 0, retaddr); + break; } - do_stack_frame(env, &sp, 1, oldsr, 0, retaddr); - } else { + /* fall through */ + + default: do_stack_frame(env, &sp, 0, oldsr, 0, retaddr); + break; } env->aregs[7] = sp; From patchwork Fri May 27 16:47:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 576508 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:8607:0:0:0:0 with SMTP id bb7csp803855mab; Fri, 27 May 2022 09:49:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx5IxNT2YvRcAhICokGXvCu0hbk6dS9v4key18WhkQkz7S33/SFnSBRwS+138e821AntMBN X-Received: by 2002:a05:620a:a9c:b0:6a3:8411:6c78 with SMTP id v28-20020a05620a0a9c00b006a384116c78mr18190604qkg.689.1653670180662; Fri, 27 May 2022 09:49:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653670180; cv=none; d=google.com; s=arc-20160816; b=lXJANG7QuOLU2SFpf/a1sM22tZNlKjYbHRUfpiDKjBwyUziJ2PaJvlVk4P6wfVTjr0 DF+LZ1MraVFWRz+18+AOfXUuXwVPE4RdT0+ngqqQFIt3TkseH6T5bgifr5x8Q7UrF4Hj VoPfixIlOEq4830NVIU1NJllaJkrMHxup4+tfuI3nGDtTsCWnQqny41IUgvceLOiOd2E lyda27ieBZLLN85tou6EdDmNRO5xzOdC57+7qt/g+8Swp5LSptRB8wXQ3YX4WHntzKao Vj8z7XLBZomhNxQJwvacb96f2lI/cDywbRixl4avnqfo+PkiVtfT4rJqdB3jLR464IGO tmOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=mCzaU+JrOI2uB5gjGXQ6lDaHwnlMpGfIPzqc07MdKqM=; b=ROGQu3+TOHhCQFTw3Eztz/TvQgDWqjyyDxlyUGu4jsdfTE9k/R13TaWMjEFU/Ioueq JztCv6cMGIlj9hKvaVVFfEyqegJ2sixGqjmeuOsMrPA6YK+CgxovLcSmX+EKLeQrwOQ1 I4Q16Gtm/naif99mwObeEr9nvL/YD9hXRk84MG/u64LX36xdQJXolIeJ5/dMsUR17FYq cIqHrGpPq/4g8Mu234bSzf460X7z44OhpJe4ycsdUnjxGaeZs9Har0V7src/OAYWjS5G fgk/eQESuzh/rMoyu5QkPusCmrEy+vkM/koaDuzUqICX8qgZK8tZ+C4dbPE0D7Z5lIIR h0WQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="EPjKqx/M"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.71.225]) by smtp.gmail.com with ESMTPSA id j11-20020aa7928b000000b0050dc7628133sm3861420pfa.13.2022.05.27.09.48.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 May 2022 09:48:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v5 03/17] target/m68k: Fix coding style in m68k_interrupt_all Date: Fri, 27 May 2022 09:47:53 -0700 Message-Id: <20220527164807.135038-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220527164807.135038-1-richard.henderson@linaro.org> References: <20220527164807.135038-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add parenthesis around & vs &&. Remove assignment to sr in function call argument -- note that sr is unused after the call, so the assignment was never needed, only the result of the & expression. Suggested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/op_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 2b94a6ec84..0f41c2dce3 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -408,11 +408,11 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) break; case EXCP_SPURIOUS ... EXCP_INT_LEVEL_7: - if (is_hw && oldsr & SR_M) { + if (is_hw && (oldsr & SR_M)) { do_stack_frame(env, &sp, 0, oldsr, 0, retaddr); oldsr = sr; env->aregs[7] = sp; - cpu_m68k_set_sr(env, sr &= ~SR_M); + cpu_m68k_set_sr(env, sr & ~SR_M); sp = env->aregs[7]; if (!m68k_feature(env, M68K_FEATURE_UNALIGNED_DATA)) { sp &= ~1; From patchwork Fri May 27 16:47:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 576512 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:8607:0:0:0:0 with SMTP id bb7csp807578mab; Fri, 27 May 2022 09:54:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxTajgZCrKeeOcEDHh36dDdpxG3wxA4JaESlrELol9yAKV/x3jPsoEZax2n57Pat6dF5J5C X-Received: by 2002:ac8:5b50:0:b0:2f9:3e39:b75b with SMTP id n16-20020ac85b50000000b002f93e39b75bmr18456460qtw.60.1653670457436; Fri, 27 May 2022 09:54:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653670457; cv=none; d=google.com; s=arc-20160816; b=IFVlJRlo8ENtxUYv1L/gW79OCRKRbKruu0n5pY9bC7+HbtRanWUUCbOjByTMdZ1+lI imYrgCjvPdaYkp+yhrsY62ODT81VwENmZe1I2zhF3M3idTX9HyOe+81LqxhBxCBMaDnK p/xYE3eXNcoz9/u02H/TlHX/XUGJSnTiXz+dzu+glO0EJTddcpuUqT1dXot/wtaUGdB+ sm3IYTqSz+CCbKpcPy+u4k2la0yf0rmuT8nSz535mgwaVBAexxOOyoAwi51eYl2yDuOF BMTDcPThAE7qwvrr7CnyeuoZ01nQA61RWzexCueemBPxdfLcZAPnfsvPYsB5zOFbirvp t0XA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=P8QVHsssV/N9S00mQXjYBPgFpjBb96NXM+kaVdZ/lRE=; b=b9CwSNa5F70eZEY2EkJ+OMZkR5HmdAtwxi2/4zBSnZf/4I5zIeY8MNRQgm9uF+GnL7 DMwoeF4PCJ6ZsoQ06fiFs48BxwwURLu7M3kMoNHN2IuF7J+Vc2N4QNkJRwW/GNM4gjTF 6wGW82L/ZdMvDqwGxH249ELQbvc83gPsGWRR2nh9pVHfs32a7GxT0fqPtEW+wOy1nWL1 8/npUhQq/BOXP7iGbOw7YEqQmvfqsM4q14b26cR8BhAn1BSDjK8aKicT9b1DDclHrz6u SFpD2v5Qd8iJQhLK2vVn/s5+J+Kr0oXl/aBh1b6pkrNZB5+hFTYijBeU9e2a6xNxIu7b tqOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=e+X6FO9n; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.71.225]) by smtp.gmail.com with ESMTPSA id j11-20020aa7928b000000b0050dc7628133sm3861420pfa.13.2022.05.27.09.48.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 May 2022 09:48:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH v5 04/17] linux-user/m68k: Handle EXCP_TRAP1 through EXCP_TRAP15 Date: Fri, 27 May 2022 09:47:54 -0700 Message-Id: <20220527164807.135038-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220527164807.135038-1-richard.henderson@linaro.org> References: <20220527164807.135038-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These are raised by guest instructions, and should not fall through into the default abort case. Signed-off-by: Richard Henderson Reviewed-by: Laurent Vivier --- linux-user/m68k/cpu_loop.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index 56417f7401..12e5d9cd53 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -75,7 +75,11 @@ void cpu_loop(CPUM68KState *env) case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; + case EXCP_TRAP0 + 1 ... EXCP_TRAP0 + 14: + force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLTRP, env->pc); + break; case EXCP_DEBUG: + case EXCP_TRAP15: force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc); break; case EXCP_ATOMIC: From patchwork Fri May 27 16:47:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 576514 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:8607:0:0:0:0 with SMTP id bb7csp809736mab; Fri, 27 May 2022 09:57:16 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxz/4Z80mRUoYVkXZO7qxUAMe9YtEhJwUBj5G7NMfo6sOVlQ8oRAVI7A0rtOhVQt+xB3Zrw X-Received: by 2002:a05:6214:1c05:b0:462:134d:6fac with SMTP id u5-20020a0562141c0500b00462134d6facmr29682428qvc.76.1653670636439; Fri, 27 May 2022 09:57:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653670636; cv=none; d=google.com; s=arc-20160816; b=LNk/2WSOCnUYpAB6tQ1n0+9fNTFCumuteuMQpWIZuyEipCd04dFsGhDk4qf3qxAKN6 icQUaWplSsFDgsSXUTmeCxyMYNLFHlQ08S4ZVIyxWyP9QXPajiUC7/U64fKmbTYZYpma By7xaVCRM51axP176aGM4HCMgE/TkoWefyz1bRcAEcejusTuJ+JADL/chwkvmQ2iIVoM Ag1bgAhLmOvMcpUXizThhfzQ4+v4h3QHa2SkijP8NwywP5wJ6LVWvJCDdQOlTflHXYU4 a9alaSB2FkxGLw5AyrMDzOBTiHfW+7vgKpfY8fhXKI+nqrz05dUSs8k4StPrlOc98j/W bjtQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=dBQmcYvQNWemNoz94qCXnnbynO5dcM+A32yDVQduyko=; b=vMJugTYjQllICFJWGZo5MePoZ7cv4X/gJ0zJQ+OpHmu1ZF5963YH9iWGNMOvpwVZL1 dkW8uGatr2oUQnHTmGCOJvk7dAvEs+qqMorbmFVX79tMSvXxjS6UEHQX3rgWsk/8HF/e yfoao3ivM1HekwaJYHcItCOaJyrCCL2fyciF8xMSlbZX4xQyoVcJBBR0Jp2ZO7/WcpVY x6HhIkSM2rKJNCI+LvTGUAW9u7GMaXb0LKGoeHROqh3YfN/4bMIsZML3gCRbuHyZGfWe /WXORMLa6KY+e1CQFyFLpK4TmnGXQNrA3ifjs0JyDh7vrOgMkSR+tkmsyNL0VuFS6Gp0 GZyQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Gy510/cG"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.71.225]) by smtp.gmail.com with ESMTPSA id j11-20020aa7928b000000b0050dc7628133sm3861420pfa.13.2022.05.27.09.48.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 May 2022 09:48:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v5 05/17] target/m68k: Remove retaddr in m68k_interrupt_all Date: Fri, 27 May 2022 09:47:55 -0700 Message-Id: <20220527164807.135038-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220527164807.135038-1-richard.henderson@linaro.org> References: <20220527164807.135038-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The only value this variable holds is now env->pc. Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/m68k/op_helper.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 0f41c2dce3..777869790b 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -287,12 +287,9 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) { CPUState *cs = env_cpu(env); uint32_t sp; - uint32_t retaddr; uint32_t vector; uint16_t sr, oldsr; - retaddr = env->pc; - if (!is_hw) { switch (cs->exception_index) { case EXCP_RTE: @@ -385,7 +382,7 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) sp -= 4; cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0); - do_stack_frame(env, &sp, 7, oldsr, 0, retaddr); + do_stack_frame(env, &sp, 7, oldsr, 0, env->pc); env->mmu.fault = false; if (qemu_loglevel_mask(CPU_LOG_INT)) { qemu_log(" " @@ -395,7 +392,7 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) break; case EXCP_ADDRESS: - do_stack_frame(env, &sp, 2, oldsr, 0, retaddr); + do_stack_frame(env, &sp, 2, oldsr, 0, env->pc); break; case EXCP_ILLEGAL: @@ -404,12 +401,12 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) case EXCP_TRAPCC: case EXCP_TRACE: /* FIXME: addr is not only env->pc */ - do_stack_frame(env, &sp, 2, oldsr, env->pc, retaddr); + do_stack_frame(env, &sp, 2, oldsr, env->pc, env->pc); break; case EXCP_SPURIOUS ... EXCP_INT_LEVEL_7: if (is_hw && (oldsr & SR_M)) { - do_stack_frame(env, &sp, 0, oldsr, 0, retaddr); + do_stack_frame(env, &sp, 0, oldsr, 0, env->pc); oldsr = sr; env->aregs[7] = sp; cpu_m68k_set_sr(env, sr & ~SR_M); @@ -417,13 +414,13 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) if (!m68k_feature(env, M68K_FEATURE_UNALIGNED_DATA)) { sp &= ~1; } - do_stack_frame(env, &sp, 1, oldsr, 0, retaddr); + do_stack_frame(env, &sp, 1, oldsr, 0, env->pc); break; } /* fall through */ default: - do_stack_frame(env, &sp, 0, oldsr, 0, retaddr); + do_stack_frame(env, &sp, 0, oldsr, 0, env->pc); break; } From patchwork Fri May 27 16:47:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 576517 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:8607:0:0:0:0 with SMTP id bb7csp813293mab; Fri, 27 May 2022 10:01:36 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzQCFSY+UD2LvNex1X+BrmrOCgatGa5Qh8iSEqb9bwkI5efkLb2R8H+oFZi4joyW3pGX97W X-Received: by 2002:a05:620a:46a9:b0:6a3:a6b0:70c5 with SMTP id bq41-20020a05620a46a900b006a3a6b070c5mr16497655qkb.208.1653670896491; Fri, 27 May 2022 10:01:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653670896; cv=none; d=google.com; s=arc-20160816; b=IEBJq7CiN7rt8phZhH0qCqk6d+D3FjrgqsXztnBY+MCwU1oDIXLpG9CVh2qOOc4XD5 ooL4BqpsqxacBTn21hxSUGX0M/mG1OiN6bisF3iw3UYd2EFEYCxpDeyhdrAoKMParLz7 IQaWeB7nZ8M3y2+LXnjAkw4cDQnPqtwQQ+VXUgSvXYPuCvDPLM0+6p4pWiXt27lVUXHB EeLATdsHQoOmCUBMUnS+/JI2KFngIvkeE1zYsrFVhOD5GuGuMZdwoTrfuo7rEA3pxm4M 6PDKHXPRX5u0KZY1pK10DlpCNqdklpzxUuk7T01Z07X2iPeUBRBayJUl94EUgOl/AApl vW4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=lTUaM+lqbn8KxvXwj+n9JX47C53ZG33aTbTDGh5Ahv4=; b=h76Di7HTvGcvEsxlQ+bVqVe1d/mvpd2ez37jw4utzCBqrluFCxHPKnsAElBjxPaUuA cVhfghs5GHgh7SOsQnwexFGptE5Wfgk/tA/VGXnh7FFXE++w9dRobPPh1xKXlZDZ/+/v kKp/2FlvS407C5t/264ZFsWORqlkD1I9najSvsVzrwTXdKrL+ZzutzzO6MVpXPZBl9H0 c5n7fnKDapXkzBQLYRxUqG1lg5pFaJX3S0kVe8HTLW1b7WbozRMyenSWZshAR6G8rN1w gNAICGiGz8xFMrJZpxNhUAfs+QHPJTK5SnAkfA09gi6qx0pmscFd5nn+FW9kspUfEunV /36A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=x0jZrnsn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.71.225]) by smtp.gmail.com with ESMTPSA id j11-20020aa7928b000000b0050dc7628133sm3861420pfa.13.2022.05.27.09.48.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 May 2022 09:48:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH v5 06/17] target/m68k: Fix address argument for EXCP_CHK Date: Fri, 27 May 2022 09:47:56 -0700 Message-Id: <20220527164807.135038-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220527164807.135038-1-richard.henderson@linaro.org> References: <20220527164807.135038-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" According to the M68040 Users Manual, section 8.4.3, Six word stack frame (format 2), CHK, CHK2 (and others) are supposed to record the next insn in PC and the address of the trapping instruction in ADDRESS. Create a raise_exception_format2 function to centralize recording of the trapping pc in mmu.ar, plus advancing to the next insn. Update m68k_interrupt_all to pass mmu.ar to do_stack_frame. Update cpu_loop to pass mmu.ar to siginfo.si_addr, as the kernel does in trap_c(). Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/cpu.h | 6 +++++ linux-user/m68k/cpu_loop.c | 2 +- target/m68k/op_helper.c | 54 ++++++++++++++++++++------------------ 3 files changed, 36 insertions(+), 26 deletions(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 9b3bf7a448..558c3c67d6 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -122,6 +122,12 @@ typedef struct CPUArchState { /* MMU status. */ struct { + /* + * Holds the "address" value in between raising an exception + * and creation of the exception stack frame. + * Used for both Format 7 exceptions (Access, i.e. mmu) + * and Format 2 exceptions (chk, div0, trapcc, etc). + */ uint32_t ar; uint32_t ssw; /* 68040 */ diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index 12e5d9cd53..e24d17e180 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -47,7 +47,7 @@ void cpu_loop(CPUM68KState *env) force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc); break; case EXCP_CHK: - force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, env->pc); + force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, env->mmu.ar); break; case EXCP_DIV0: force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->pc); diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 777869790b..750d65576f 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -397,13 +397,16 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) case EXCP_ILLEGAL: case EXCP_DIV0: - case EXCP_CHK: case EXCP_TRAPCC: case EXCP_TRACE: /* FIXME: addr is not only env->pc */ do_stack_frame(env, &sp, 2, oldsr, env->pc, env->pc); break; + case EXCP_CHK: + do_stack_frame(env, &sp, 2, oldsr, env->mmu.ar, env->pc); + break; + case EXCP_SPURIOUS ... EXCP_INT_LEVEL_7: if (is_hw && (oldsr & SR_M)) { do_stack_frame(env, &sp, 0, oldsr, 0, env->pc); @@ -548,6 +551,29 @@ void HELPER(raise_exception)(CPUM68KState *env, uint32_t tt) raise_exception(env, tt); } +G_NORETURN static void +raise_exception_format2(CPUM68KState *env, int tt, int ilen, uintptr_t raddr) +{ + CPUState *cs = env_cpu(env); + + cs->exception_index = tt; + + /* Recover PC and CC_OP for the beginning of the insn. */ + cpu_restore_state(cs, raddr, true); + + /* Flags are current in env->cc_*, or are undefined. */ + env->cc_op = CC_OP_FLAGS; + + /* + * Remember original pc in mmu.ar, for the Format 2 stack frame. + * Adjust PC to end of the insn. + */ + env->mmu.ar = env->pc; + env->pc += ilen; + + cpu_loop_exit(cs); +} + void HELPER(divuw)(CPUM68KState *env, int destr, uint32_t den) { uint32_t num = env->dregs[destr]; @@ -1065,18 +1091,7 @@ void HELPER(chk)(CPUM68KState *env, int32_t val, int32_t ub) env->cc_c = 0 <= ub ? val < 0 || val > ub : val > ub && val < 0; if (val < 0 || val > ub) { - CPUState *cs = env_cpu(env); - - /* Recover PC and CC_OP for the beginning of the insn. */ - cpu_restore_state(cs, GETPC(), true); - - /* flags have been modified by gen_flush_flags() */ - env->cc_op = CC_OP_FLAGS; - /* Adjust PC to end of the insn. */ - env->pc += 2; - - cs->exception_index = EXCP_CHK; - cpu_loop_exit(cs); + raise_exception_format2(env, EXCP_CHK, 2, GETPC()); } } @@ -1097,17 +1112,6 @@ void HELPER(chk2)(CPUM68KState *env, int32_t val, int32_t lb, int32_t ub) env->cc_c = lb <= ub ? val < lb || val > ub : val > ub && val < lb; if (env->cc_c) { - CPUState *cs = env_cpu(env); - - /* Recover PC and CC_OP for the beginning of the insn. */ - cpu_restore_state(cs, GETPC(), true); - - /* flags have been modified by gen_flush_flags() */ - env->cc_op = CC_OP_FLAGS; - /* Adjust PC to end of the insn. */ - env->pc += 4; - - cs->exception_index = EXCP_CHK; - cpu_loop_exit(cs); + raise_exception_format2(env, EXCP_CHK, 4, GETPC()); } } From patchwork Fri May 27 16:47:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 576510 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:8607:0:0:0:0 with SMTP id bb7csp806960mab; Fri, 27 May 2022 09:53:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyGNLqcAB/N+cr0QQZMu9hGWdx6/sEQ3r/7xmO+A/VVdlT33xDs00ebzNopsbeDFq60Fcqo X-Received: by 2002:a05:6214:234b:b0:461:f43b:cede with SMTP id hu11-20020a056214234b00b00461f43bcedemr36676777qvb.3.1653670408448; Fri, 27 May 2022 09:53:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653670408; cv=none; d=google.com; s=arc-20160816; b=SH6qKwr2ET5pYorO418dt8k0+n9AxCplOiLBmiWNJshmRB1ePG4JnMiSDRcelEtdRF +CYVn6o0+oQ12BG1CW6my3IQpNJ15exg5axVRMO/FJWIymeJF36dKfMSrfg0YlRgDPHN n1eeqcXME8pmAFdFxKRI+OF0MRXEkjsJWEHtp5lMHUkF6QG8UE7nfBZcLt8tOaU+MqO3 329olnJ9oxASh9KsxqpC1cQ5OINoEmG7qAiOR+fiuZrUmdthQA9W9Wn06H2q/4B7VgWs 8JXl1eOvJMmEXpzvmE0HrG8La8NB/SOjSlEX1H8q5gcAXEeAXybKq6VeqfiU2Y0MuOHx oDrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9h8O/PKdXL0KvuNK2v2gIq3YV3vKmkNQsNhTF8q3vR8=; b=x6ZAFo8yT5Yp/pH0CnZpYFR+lAXnn+odjKoMKACR4LgcGaIZCjsbiuS4+O8xInUSLm JcMJkMe8iGWxAOAmF3N4PbQRQLUB3hwNrlXckS6eO2aEtiSwnoJOv09eSG0E9Uwj5CAP afUD984ar4b4ylYF1Ynw9UHWiahJWmN6LIKcrNBRp4juMyNj5zweTz28ox9IRG6FkE4i ChJHhzDJevXFcgJrGTW7mgrkFpo5L8OnhVEJe7y2uloCFmolJMNNwbAKSPU9xbjV6DES Et5DHFRrWMcmo4AwA/GIVsvEnntoHyC5D1tIREHJcL3vn8y6gjAJ06vhbeXJxU0dghn2 v5ZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=F9MiOENo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.71.225]) by smtp.gmail.com with ESMTPSA id j11-20020aa7928b000000b0050dc7628133sm3861420pfa.13.2022.05.27.09.48.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 May 2022 09:48:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH v5 07/17] target/m68k: Fix pc, c flag, and address argument for EXCP_DIV0 Date: Fri, 27 May 2022 09:47:57 -0700 Message-Id: <20220527164807.135038-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220527164807.135038-1-richard.henderson@linaro.org> References: <20220527164807.135038-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" According to the M68040 Users Manual, section 8.4.3, Six word stack frame (format 2), Zero Div (and others) is supposed to record the next insn in PC and the address of the trapping instruction in ADDRESS. While the N, Z and V flags are documented to be undefine on DIV0, the C flag is documented as always cleared. Update helper_div* to take the instruction length as an argument and use raise_exception_format2. Hoist the reset of the C flag above the division by zero check. Update m68k_interrupt_all to pass mmu.ar to do_stack_frame. Update cpu_loop to pass mmu.ar to siginfo.si_addr, as the kernel does in trap_c(). Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/helper.h | 12 +++++----- linux-user/m68k/cpu_loop.c | 2 +- target/m68k/op_helper.c | 48 +++++++++++++++++++++++--------------- target/m68k/translate.c | 33 +++++++++++++------------- 4 files changed, 52 insertions(+), 43 deletions(-) diff --git a/target/m68k/helper.h b/target/m68k/helper.h index 0a6b4146f6..f016c4c1c2 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -1,12 +1,12 @@ DEF_HELPER_1(bitrev, i32, i32) DEF_HELPER_1(ff1, i32, i32) DEF_HELPER_FLAGS_2(sats, TCG_CALL_NO_RWG_SE, i32, i32, i32) -DEF_HELPER_3(divuw, void, env, int, i32) -DEF_HELPER_3(divsw, void, env, int, s32) -DEF_HELPER_4(divul, void, env, int, int, i32) -DEF_HELPER_4(divsl, void, env, int, int, s32) -DEF_HELPER_4(divull, void, env, int, int, i32) -DEF_HELPER_4(divsll, void, env, int, int, s32) +DEF_HELPER_4(divuw, void, env, int, i32, int) +DEF_HELPER_4(divsw, void, env, int, s32, int) +DEF_HELPER_5(divul, void, env, int, int, i32, int) +DEF_HELPER_5(divsl, void, env, int, int, s32, int) +DEF_HELPER_5(divull, void, env, int, int, i32, int) +DEF_HELPER_5(divsll, void, env, int, int, s32, int) DEF_HELPER_2(set_sr, void, env, i32) DEF_HELPER_3(cf_movec_to, void, env, i32, i32) DEF_HELPER_3(m68k_movec_to, void, env, i32, i32) diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index e24d17e180..6598bce3c4 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -50,7 +50,7 @@ void cpu_loop(CPUM68KState *env) force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, env->mmu.ar); break; case EXCP_DIV0: - force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->pc); + force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->mmu.ar); break; case EXCP_TRAP0: { diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 750d65576f..729ee0e934 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -396,7 +396,6 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) break; case EXCP_ILLEGAL: - case EXCP_DIV0: case EXCP_TRAPCC: case EXCP_TRACE: /* FIXME: addr is not only env->pc */ @@ -404,6 +403,7 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) break; case EXCP_CHK: + case EXCP_DIV0: do_stack_frame(env, &sp, 2, oldsr, env->mmu.ar, env->pc); break; @@ -574,18 +574,19 @@ raise_exception_format2(CPUM68KState *env, int tt, int ilen, uintptr_t raddr) cpu_loop_exit(cs); } -void HELPER(divuw)(CPUM68KState *env, int destr, uint32_t den) +void HELPER(divuw)(CPUM68KState *env, int destr, uint32_t den, int ilen) { uint32_t num = env->dregs[destr]; uint32_t quot, rem; + env->cc_c = 0; /* always cleared, even if div0 */ + if (den == 0) { - raise_exception_ra(env, EXCP_DIV0, GETPC()); + raise_exception_format2(env, EXCP_DIV0, ilen, GETPC()); } quot = num / den; rem = num % den; - env->cc_c = 0; /* always cleared, even if overflow */ if (quot > 0xffff) { env->cc_v = -1; /* @@ -601,18 +602,19 @@ void HELPER(divuw)(CPUM68KState *env, int destr, uint32_t den) env->cc_v = 0; } -void HELPER(divsw)(CPUM68KState *env, int destr, int32_t den) +void HELPER(divsw)(CPUM68KState *env, int destr, int32_t den, int ilen) { int32_t num = env->dregs[destr]; uint32_t quot, rem; + env->cc_c = 0; /* always cleared, even if overflow/div0 */ + if (den == 0) { - raise_exception_ra(env, EXCP_DIV0, GETPC()); + raise_exception_format2(env, EXCP_DIV0, ilen, GETPC()); } quot = num / den; rem = num % den; - env->cc_c = 0; /* always cleared, even if overflow */ if (quot != (int16_t)quot) { env->cc_v = -1; /* nothing else is modified */ @@ -629,18 +631,20 @@ void HELPER(divsw)(CPUM68KState *env, int destr, int32_t den) env->cc_v = 0; } -void HELPER(divul)(CPUM68KState *env, int numr, int regr, uint32_t den) +void HELPER(divul)(CPUM68KState *env, int numr, int regr, + uint32_t den, int ilen) { uint32_t num = env->dregs[numr]; uint32_t quot, rem; + env->cc_c = 0; /* always cleared, even if div0 */ + if (den == 0) { - raise_exception_ra(env, EXCP_DIV0, GETPC()); + raise_exception_format2(env, EXCP_DIV0, ilen, GETPC()); } quot = num / den; rem = num % den; - env->cc_c = 0; env->cc_z = quot; env->cc_n = quot; env->cc_v = 0; @@ -657,18 +661,20 @@ void HELPER(divul)(CPUM68KState *env, int numr, int regr, uint32_t den) } } -void HELPER(divsl)(CPUM68KState *env, int numr, int regr, int32_t den) +void HELPER(divsl)(CPUM68KState *env, int numr, int regr, + int32_t den, int ilen) { int32_t num = env->dregs[numr]; int32_t quot, rem; + env->cc_c = 0; /* always cleared, even if overflow/div0 */ + if (den == 0) { - raise_exception_ra(env, EXCP_DIV0, GETPC()); + raise_exception_format2(env, EXCP_DIV0, ilen, GETPC()); } quot = num / den; rem = num % den; - env->cc_c = 0; env->cc_z = quot; env->cc_n = quot; env->cc_v = 0; @@ -685,19 +691,21 @@ void HELPER(divsl)(CPUM68KState *env, int numr, int regr, int32_t den) } } -void HELPER(divull)(CPUM68KState *env, int numr, int regr, uint32_t den) +void HELPER(divull)(CPUM68KState *env, int numr, int regr, + uint32_t den, int ilen) { uint64_t num = deposit64(env->dregs[numr], 32, 32, env->dregs[regr]); uint64_t quot; uint32_t rem; + env->cc_c = 0; /* always cleared, even if overflow/div0 */ + if (den == 0) { - raise_exception_ra(env, EXCP_DIV0, GETPC()); + raise_exception_format2(env, EXCP_DIV0, ilen, GETPC()); } quot = num / den; rem = num % den; - env->cc_c = 0; /* always cleared, even if overflow */ if (quot > 0xffffffffULL) { env->cc_v = -1; /* @@ -720,19 +728,21 @@ void HELPER(divull)(CPUM68KState *env, int numr, int regr, uint32_t den) env->dregs[numr] = quot; } -void HELPER(divsll)(CPUM68KState *env, int numr, int regr, int32_t den) +void HELPER(divsll)(CPUM68KState *env, int numr, int regr, + int32_t den, int ilen) { int64_t num = deposit64(env->dregs[numr], 32, 32, env->dregs[regr]); int64_t quot; int32_t rem; + env->cc_c = 0; /* always cleared, even if overflow/div0 */ + if (den == 0) { - raise_exception_ra(env, EXCP_DIV0, GETPC()); + raise_exception_format2(env, EXCP_DIV0, ilen, GETPC()); } quot = num / den; rem = num % den; - env->cc_c = 0; /* always cleared, even if overflow */ if (quot != (int32_t)quot) { env->cc_v = -1; /* diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 6d6d026e3c..d775345bfa 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -1601,6 +1601,7 @@ DISAS_INSN(divw) int sign; TCGv src; TCGv destr; + TCGv ilen; /* divX.w ,Dn 32/16 -> 16r:16q */ @@ -1609,20 +1610,20 @@ DISAS_INSN(divw) /* dest.l / src.w */ SRC_EA(env, src, OS_WORD, sign, NULL); - destr = tcg_const_i32(REG(insn, 9)); + destr = tcg_constant_i32(REG(insn, 9)); + ilen = tcg_constant_i32(s->pc - s->base.pc_next); if (sign) { - gen_helper_divsw(cpu_env, destr, src); + gen_helper_divsw(cpu_env, destr, src, ilen); } else { - gen_helper_divuw(cpu_env, destr, src); + gen_helper_divuw(cpu_env, destr, src, ilen); } - tcg_temp_free(destr); set_cc_op(s, CC_OP_FLAGS); } DISAS_INSN(divl) { - TCGv num, reg, den; + TCGv num, reg, den, ilen; int sign; uint16_t ext; @@ -1639,15 +1640,14 @@ DISAS_INSN(divl) /* divX.l , Dr:Dq 64/32 -> 32r:32q */ SRC_EA(env, den, OS_LONG, 0, NULL); - num = tcg_const_i32(REG(ext, 12)); - reg = tcg_const_i32(REG(ext, 0)); + num = tcg_constant_i32(REG(ext, 12)); + reg = tcg_constant_i32(REG(ext, 0)); + ilen = tcg_constant_i32(s->pc - s->base.pc_next); if (sign) { - gen_helper_divsll(cpu_env, num, reg, den); + gen_helper_divsll(cpu_env, num, reg, den, ilen); } else { - gen_helper_divull(cpu_env, num, reg, den); + gen_helper_divull(cpu_env, num, reg, den, ilen); } - tcg_temp_free(reg); - tcg_temp_free(num); set_cc_op(s, CC_OP_FLAGS); return; } @@ -1656,15 +1656,14 @@ DISAS_INSN(divl) /* divXl.l , Dr:Dq 32/32 -> 32r:32q */ SRC_EA(env, den, OS_LONG, 0, NULL); - num = tcg_const_i32(REG(ext, 12)); - reg = tcg_const_i32(REG(ext, 0)); + num = tcg_constant_i32(REG(ext, 12)); + reg = tcg_constant_i32(REG(ext, 0)); + ilen = tcg_constant_i32(s->pc - s->base.pc_next); if (sign) { - gen_helper_divsl(cpu_env, num, reg, den); + gen_helper_divsl(cpu_env, num, reg, den, ilen); } else { - gen_helper_divul(cpu_env, num, reg, den); + gen_helper_divul(cpu_env, num, reg, den, ilen); } - tcg_temp_free(reg); - tcg_temp_free(num); set_cc_op(s, CC_OP_FLAGS); } From patchwork Fri May 27 16:47:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 576513 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:8607:0:0:0:0 with SMTP id bb7csp809139mab; Fri, 27 May 2022 09:56:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy790uNJf1LgrFwYRAirVHCVNlhWZ/ia7h5aDEnJJEy2Jth6XzUs88WbdzbuyPAPDsqSy0t X-Received: by 2002:a05:622a:ca:b0:2f9:3f2c:c463 with SMTP id p10-20020a05622a00ca00b002f93f2cc463mr17684373qtw.386.1653670585678; Fri, 27 May 2022 09:56:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; 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[174.21.71.225]) by smtp.gmail.com with ESMTPSA id j11-20020aa7928b000000b0050dc7628133sm3861420pfa.13.2022.05.27.09.48.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 May 2022 09:48:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH v5 08/17] target/m68k: Fix address argument for EXCP_TRACE Date: Fri, 27 May 2022 09:47:58 -0700 Message-Id: <20220527164807.135038-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220527164807.135038-1-richard.henderson@linaro.org> References: <20220527164807.135038-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" According to the M68040 Users Manual, section 8.4.3, Six word stack frame (format 2), Trace (and others) is supposed to record the next insn in PC and the address of the trapping instruction in ADDRESS. Create gen_raise_exception_format2 to record the trapping pc in env->mmu.ar. Update m68k_interrupt_all to pass the value to do_stack_frame. Update cpu_loop to handle EXCP_TRACE. Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- linux-user/m68k/cpu_loop.c | 3 +++ target/m68k/op_helper.c | 2 +- target/m68k/translate.c | 49 +++++++++++++++++++++++++------------- 3 files changed, 36 insertions(+), 18 deletions(-) diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index 6598bce3c4..fcf9220552 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -52,6 +52,9 @@ void cpu_loop(CPUM68KState *env) case EXCP_DIV0: force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->mmu.ar); break; + case EXCP_TRACE: + force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_TRACE, env->mmu.ar); + break; case EXCP_TRAP0: { abi_long ret; diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 729ee0e934..3cb71c9140 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -397,13 +397,13 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) case EXCP_ILLEGAL: case EXCP_TRAPCC: - case EXCP_TRACE: /* FIXME: addr is not only env->pc */ do_stack_frame(env, &sp, 2, oldsr, env->pc, env->pc); break; case EXCP_CHK: case EXCP_DIV0: + case EXCP_TRACE: do_stack_frame(env, &sp, 2, oldsr, env->mmu.ar, env->pc); break; diff --git a/target/m68k/translate.c b/target/m68k/translate.c index d775345bfa..399d9232e4 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -114,6 +114,7 @@ typedef struct DisasContext { DisasContextBase base; CPUM68KState *env; target_ulong pc; + target_ulong pc_prev; CCOp cc_op; /* Current CC operation */ int cc_op_synced; TCGv_i64 mactmp; @@ -298,6 +299,21 @@ static void gen_raise_exception(int nr) tcg_temp_free_i32(tmp); } +static void gen_raise_exception_format2(DisasContext *s, int nr, + target_ulong this_pc) +{ + /* + * Pass the address of the insn to the exception handler, + * for recording in the Format $2 (6-word) stack frame. + * Re-use mmu.ar for the purpose, since that's only valid + * after tlb_fill. + */ + tcg_gen_st_i32(tcg_constant_i32(this_pc), cpu_env, + offsetof(CPUM68KState, mmu.ar)); + gen_raise_exception(nr); + s->base.is_jmp = DISAS_NORETURN; +} + static void gen_exception(DisasContext *s, uint32_t dest, int nr) { update_cc_op(s); @@ -1494,12 +1510,13 @@ static void gen_exit_tb(DisasContext *s) } while (0) /* Generate a jump to an immediate address. */ -static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest) +static void gen_jmp_tb(DisasContext *s, int n, target_ulong dest, + target_ulong src) { if (unlikely(s->ss_active)) { update_cc_op(s); tcg_gen_movi_i32(QREG_PC, dest); - gen_raise_exception(EXCP_TRACE); + gen_raise_exception_format2(s, EXCP_TRACE, src); } else if (translator_use_goto_tb(&s->base, dest)) { tcg_gen_goto_tb(n); tcg_gen_movi_i32(QREG_PC, dest); @@ -1548,9 +1565,9 @@ DISAS_INSN(dbcc) tcg_gen_addi_i32(tmp, tmp, -1); gen_partset_reg(OS_WORD, reg, tmp); tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, -1, l1); - gen_jmp_tb(s, 1, base + offset); + gen_jmp_tb(s, 1, base + offset, s->base.pc_next); gen_set_label(l1); - gen_jmp_tb(s, 0, s->pc); + gen_jmp_tb(s, 0, s->pc, s->base.pc_next); } DISAS_INSN(undef_mac) @@ -3096,13 +3113,13 @@ DISAS_INSN(branch) /* Bcc */ TCGLabel *l1 = gen_new_label(); gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1); - gen_jmp_tb(s, 1, base + offset); + gen_jmp_tb(s, 1, base + offset, s->base.pc_next); gen_set_label(l1); - gen_jmp_tb(s, 0, s->pc); + gen_jmp_tb(s, 0, s->pc, s->base.pc_next); } else { /* Unconditional branch. */ update_cc_op(s); - gen_jmp_tb(s, 0, base + offset); + gen_jmp_tb(s, 0, base + offset, s->base.pc_next); } } @@ -5485,9 +5502,9 @@ DISAS_INSN(fbcc) l1 = gen_new_label(); update_cc_op(s); gen_fjmpcc(s, insn & 0x3f, l1); - gen_jmp_tb(s, 0, s->pc); + gen_jmp_tb(s, 0, s->pc, s->base.pc_next); gen_set_label(l1); - gen_jmp_tb(s, 1, base + offset); + gen_jmp_tb(s, 1, base + offset, s->base.pc_next); } DISAS_INSN(fscc) @@ -6158,6 +6175,8 @@ static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) dc->env = env; dc->pc = dc->base.pc_first; + /* This value will always be filled in properly before m68k_tr_tb_stop. */ + dc->pc_prev = 0xdeadbeef; dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_synced = 1; dc->done_mac = 0; @@ -6191,6 +6210,7 @@ static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) do_writebacks(dc); do_release(dc); + dc->pc_prev = dc->base.pc_next; dc->base.pc_next = dc->pc; if (dc->base.is_jmp == DISAS_NEXT) { @@ -6225,17 +6245,12 @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) break; case DISAS_TOO_MANY: update_cc_op(dc); - if (dc->ss_active) { - tcg_gen_movi_i32(QREG_PC, dc->pc); - gen_raise_exception(EXCP_TRACE); - } else { - gen_jmp_tb(dc, 0, dc->pc); - } + gen_jmp_tb(dc, 0, dc->pc, dc->pc_prev); break; case DISAS_JUMP: /* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */ if (dc->ss_active) { - gen_raise_exception(EXCP_TRACE); + gen_raise_exception_format2(dc, EXCP_TRACE, dc->pc_prev); } else { tcg_gen_lookup_and_goto_ptr(); } @@ -6246,7 +6261,7 @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) * other state that may require returning to the main loop. */ if (dc->ss_active) { - gen_raise_exception(EXCP_TRACE); + gen_raise_exception_format2(dc, EXCP_TRACE, dc->pc_prev); } else { tcg_gen_exit_tb(NULL, 0); } From patchwork Fri May 27 16:47:59 2022 Content-Type: text/plain; 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[174.21.71.225]) by smtp.gmail.com with ESMTPSA id j11-20020aa7928b000000b0050dc7628133sm3861420pfa.13.2022.05.27.09.48.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 May 2022 09:48:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH v5 09/17] target/m68k: Fix stack frame for EXCP_ILLEGAL Date: Fri, 27 May 2022 09:47:59 -0700 Message-Id: <20220527164807.135038-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220527164807.135038-1-richard.henderson@linaro.org> References: <20220527164807.135038-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" According to the M68040 Users Manual, section 8.4.1, Four word stack frame (format 0), includes Illegal Instruction. Use the correct frame format, which does not use the ADDR argument. Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/op_helper.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 3cb71c9140..aa62158eb9 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -391,11 +391,14 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) } break; + case EXCP_ILLEGAL: + do_stack_frame(env, &sp, 0, oldsr, 0, env->pc); + break; + case EXCP_ADDRESS: do_stack_frame(env, &sp, 2, oldsr, 0, env->pc); break; - case EXCP_ILLEGAL: case EXCP_TRAPCC: /* FIXME: addr is not only env->pc */ do_stack_frame(env, &sp, 2, oldsr, env->pc, env->pc); From patchwork Fri May 27 16:48:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 576511 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:8607:0:0:0:0 with SMTP id bb7csp807010mab; Fri, 27 May 2022 09:53:32 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwud8cgFP/OpOorCE1wxC6Bz9Lk1wEd5RpTf1RkkKUwihs60av0B9Kzf+3/j7zbjMXMS5m4 X-Received: by 2002:ac8:5a43:0:b0:2f9:3533:9995 with SMTP id o3-20020ac85a43000000b002f935339995mr21636150qta.619.1653670412139; Fri, 27 May 2022 09:53:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653670412; cv=none; d=google.com; s=arc-20160816; b=f4evK+xCpZGYELKCp6z+tqRwcnvfDnJFWquyGj9dcEGLBNZhzE2imHC3zpRfd7lBBZ SzMwMpHz8Thtnfvb4tD3TckkvShAY9r+KCyPf17plfoz98GfbmzatrvhvCk9Ibwd1TsM Z8PZColf8eRAhson7n+N7AQAwCiROM7d3TfivYWCQKWd+mzCxiTOrxlksj8VDwgSXTYd bMavJXsWdcGQV8rgPe6uB+YE2kgCevKlDU2u+AG6eU/4uGsZnq++7P/6sKpnAfSkGuK+ 00FNCYZdS9hs/vzaXpcQ1DkdmPimJ8MMI/sgv0JDXBFu1kTdkJrN3il1SF5ek2LAuqw9 vgBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=KyWq1SP5mJS//TtONTeiMPT3+Dc2kCMkrVruGMXnAYM=; b=wP09RhTzAqcuRfdBR7CQZigPEfdazMoV1y5pMKSXOrN+J3pffQsDbSKLVPTlXZEPut QxL0j2KMJpBx84GLIWL1DkJKg0DJYxfeDaKJY+ibnhoMtMamZnWRNa/Qz68LvjHZP8OB XjQRlnRlKnMYMcxsSW1MNDJwmfLHSRWaVWjRP1oZRtRVD9YJjubscwjWv9RRO0USS8+v aeCNvYJ9XZcQpBKnmFxOvC9jDG1pNOuWRJfrCkHDbfD93Bw+zzmbeRkWBcXB+GNma+t7 1ugN4AjER1Kz4bzYNZbmThaJDBVmt5BRZVmLPTCzJWeFzspZlzeW3z62yivWojSIQ47T AQHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QKzG4W7P; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.71.225]) by smtp.gmail.com with ESMTPSA id j11-20020aa7928b000000b0050dc7628133sm3861420pfa.13.2022.05.27.09.48.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 May 2022 09:48:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH v5 10/17] target/m68k: Implement TRAPcc Date: Fri, 27 May 2022 09:48:00 -0700 Message-Id: <20220527164807.135038-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220527164807.135038-1-richard.henderson@linaro.org> References: <20220527164807.135038-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Resolves: https://gitlab.com/qemu-project/qemu/-/issues/754 Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/cpu.h | 2 ++ linux-user/m68k/cpu_loop.c | 1 + target/m68k/cpu.c | 1 + target/m68k/op_helper.c | 6 +---- target/m68k/translate.c | 49 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 54 insertions(+), 5 deletions(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 558c3c67d6..4d8f48e8c7 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -534,6 +534,8 @@ enum m68k_features { M68K_FEATURE_MOVEC, /* Unaligned data accesses (680[2346]0) */ M68K_FEATURE_UNALIGNED_DATA, + /* TRAPcc insn. (680[2346]0, and CPU32) */ + M68K_FEATURE_TRAPCC, }; static inline int m68k_feature(CPUM68KState *env, int feature) diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index fcf9220552..3d3033155f 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -47,6 +47,7 @@ void cpu_loop(CPUM68KState *env) force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc); break; case EXCP_CHK: + case EXCP_TRAPCC: force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, env->mmu.ar); break; case EXCP_DIV0: diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index c7aeb7da9c..5f778773d1 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -162,6 +162,7 @@ static void m68020_cpu_initfn(Object *obj) m68k_set_feature(env, M68K_FEATURE_CHK2); m68k_set_feature(env, M68K_FEATURE_MSP); m68k_set_feature(env, M68K_FEATURE_UNALIGNED_DATA); + m68k_set_feature(env, M68K_FEATURE_TRAPCC); } /* diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index aa62158eb9..61948d92bb 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -399,14 +399,10 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) do_stack_frame(env, &sp, 2, oldsr, 0, env->pc); break; - case EXCP_TRAPCC: - /* FIXME: addr is not only env->pc */ - do_stack_frame(env, &sp, 2, oldsr, env->pc, env->pc); - break; - case EXCP_CHK: case EXCP_DIV0: case EXCP_TRACE: + case EXCP_TRAPCC: do_stack_frame(env, &sp, 2, oldsr, env->mmu.ar, env->pc); break; diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 399d9232e4..c4fe8abc03 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4879,6 +4879,54 @@ DISAS_INSN(trap) gen_exception(s, s->pc, EXCP_TRAP0 + (insn & 0xf)); } +static void do_trapcc(DisasContext *s, DisasCompare *c) +{ + if (c->tcond != TCG_COND_NEVER) { + TCGLabel *over = NULL; + + update_cc_op(s); + + if (c->tcond != TCG_COND_ALWAYS) { + /* Jump over if !c. */ + over = gen_new_label(); + tcg_gen_brcond_i32(tcg_invert_cond(c->tcond), c->v1, c->v2, over); + } + + tcg_gen_movi_i32(QREG_PC, s->pc); + gen_raise_exception_format2(s, EXCP_TRAPCC, s->base.pc_next); + + if (over != NULL) { + gen_set_label(over); + s->base.is_jmp = DISAS_NEXT; + } + } + free_cond(c); +} + +DISAS_INSN(trapcc) +{ + DisasCompare c; + + /* Consume and discard the immediate operand. */ + switch (extract32(insn, 0, 3)) { + case 2: /* trapcc.w */ + (void)read_im16(env, s); + break; + case 3: /* trapcc.l */ + (void)read_im32(env, s); + break; + case 4: /* trapcc (no operand) */ + break; + default: + /* Illegal insn */ + disas_undef(env, s, insn); + return; + } + + gen_cc_cond(&c, s, extract32(insn, 8, 4)); + do_trapcc(s, &c); +} + static void gen_load_fcr(DisasContext *s, TCGv res, int reg) { switch (reg) { @@ -6050,6 +6098,7 @@ void register_m68k_insns (CPUM68KState *env) INSN(scc, 50c0, f0f8, CF_ISA_A); /* Scc.B Dx */ INSN(scc, 50c0, f0c0, M68000); /* Scc.B */ INSN(dbcc, 50c8, f0f8, M68000); + INSN(trapcc, 50f8, f0f8, TRAPCC); INSN(tpf, 51f8, fff8, CF_ISA_A); /* Branch instructions. */ From patchwork Fri May 27 16:48:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 576515 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:8607:0:0:0:0 with SMTP id bb7csp810217mab; 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[174.21.71.225]) by smtp.gmail.com with ESMTPSA id j11-20020aa7928b000000b0050dc7628133sm3861420pfa.13.2022.05.27.09.48.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 May 2022 09:48:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v5 11/17] target/m68k: Implement TPF in terms of TRAPcc Date: Fri, 27 May 2022 09:48:01 -0700 Message-Id: <20220527164807.135038-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220527164807.135038-1-richard.henderson@linaro.org> References: <20220527164807.135038-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" TPF stands for "trap false", and is a long-form nop for ColdFire. Re-use the immediate consumption code from trapcc; the insn will already expand to a nop because of the TCG_COND_NEVER test within do_trapcc. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/translate.c | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index c4fe8abc03..bb5ed1b7b1 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -3075,22 +3075,6 @@ DISAS_INSN(addsubq) tcg_temp_free(dest); } -DISAS_INSN(tpf) -{ - switch (insn & 7) { - case 2: /* One extension word. */ - s->pc += 2; - break; - case 3: /* Two extension words. */ - s->pc += 4; - break; - case 4: /* No extension words. */ - break; - default: - disas_undef(env, s, insn); - } -} - DISAS_INSN(branch) { int32_t offset; @@ -6099,7 +6083,7 @@ void register_m68k_insns (CPUM68KState *env) INSN(scc, 50c0, f0c0, M68000); /* Scc.B */ INSN(dbcc, 50c8, f0f8, M68000); INSN(trapcc, 50f8, f0f8, TRAPCC); - INSN(tpf, 51f8, fff8, CF_ISA_A); + INSN(trapcc, 51f8, fff8, CF_ISA_A); /* TPF (trapf) */ /* Branch instructions. */ BASE(branch, 6000, f000); From patchwork Fri May 27 16:48:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 576518 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:8607:0:0:0:0 with SMTP id bb7csp813622mab; Fri, 27 May 2022 10:01:54 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwZMtTd9UFLL9K8mNxheUGwe0X7SFj0mCkMW2wsL1MQIqAqsyyUvCIsNMnXV1R3Zwox8wu7 X-Received: by 2002:a5d:598e:0:b0:20f:c303:83e7 with SMTP id n14-20020a5d598e000000b0020fc30383e7mr28750729wri.244.1653670914468; Fri, 27 May 2022 10:01:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653670914; cv=none; d=google.com; s=arc-20160816; b=C0g++gvCArhwGnrqH+H3d9eHcioMSK/cwkPBlkfApeUQPp2wx5aER/29roEC75XOvQ 6HuePBEb7BcsUjDWNFPcs3tHq0Oas5WyyZG4qf+bgGavEVXPw+uc64n0a/gA0HixIoYv RMz4STaSpdl1BRWMAmWI32405USAz8vwu70loANJh1z+vpWss388Wy7Kc+NMjPe3RsQH 7k5rpMIkZnH7WhxJml7auHZRzSFI+KUOVtpbUQcSh92Oo5LCgVPZYVPtxQdsxtI2l7CB Oqx6OUT1KJbfBjCIZFxhb+uNaLy9kLBGgupKT8U7e/SSvaAczrEEX4rCIpCQbziIHExk QSuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=0nKCx0fk9E4IrZSh0Ih9XJaTHZRzsP+YmI+UgWL7HrA=; b=hRhkO2A0QfGoeRdb1ES2iNPYxhE1tHhmrV0mD7P8a+/moJ0xUbkc75Sqpl6up+DHmc 30jdoCsgc052zPSy2odS7t2oVDnYcXTuvEo9CuY/lkEVE/AwOc1eljxkuJ+on4AzaPAc NTosc3zStdVCvnC9Yji6qO3Mxchs/DijPkxjVx56NYwjDkgAvKjC/u0i+11dG2JKzBH1 VpO9Uy0GksNSx15J9rD7eR0CyWRsFmswLC5y3d5d+oBtfo3YwSnLugaA+6lIIjqneYwf rCgabJrdoZci0BMDj9owpZp9bT2vLo81+K2h5EjedSb8RBFAvZs1GdOyt38rF7em3+QW B8fw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DgW6dNT6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.71.225]) by smtp.gmail.com with ESMTPSA id j11-20020aa7928b000000b0050dc7628133sm3861420pfa.13.2022.05.27.09.48.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 May 2022 09:48:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH v5 12/17] target/m68k: Implement TRAPV Date: Fri, 27 May 2022 09:48:02 -0700 Message-Id: <20220527164807.135038-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220527164807.135038-1-richard.henderson@linaro.org> References: <20220527164807.135038-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/translate.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index bb5ed1b7b1..0cd7ef89e3 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4911,6 +4911,14 @@ DISAS_INSN(trapcc) do_trapcc(s, &c); } +DISAS_INSN(trapv) +{ + DisasCompare c; + + gen_cc_cond(&c, s, 9); /* V set */ + do_trapcc(s, &c); +} + static void gen_load_fcr(DisasContext *s, TCGv res, int reg) { switch (reg) { @@ -6074,6 +6082,7 @@ void register_m68k_insns (CPUM68KState *env) BASE(nop, 4e71, ffff); INSN(rtd, 4e74, ffff, RTD); BASE(rts, 4e75, ffff); + INSN(trapv, 4e76, ffff, M68000); INSN(rtr, 4e77, ffff, M68000); BASE(jump, 4e80, ffc0); BASE(jump, 4ec0, ffc0); From patchwork Fri May 27 16:48:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 576516 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:8607:0:0:0:0 with SMTP id bb7csp811646mab; Fri, 27 May 2022 09:59:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzGrobcgJiUQhr4Y81SEL9plLK/k9Cin7UMHH0i6GjBxLI+NJ7chLU/V1qNrxz1jpyXSr2H X-Received: by 2002:a05:622a:1988:b0:2f9:4132:6ee5 with SMTP id u8-20020a05622a198800b002f941326ee5mr16321767qtc.650.1653670792628; Fri, 27 May 2022 09:59:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653670792; cv=none; d=google.com; s=arc-20160816; b=LxIipP7iDQxsFc3s+ZbtRfhh3vLEGR+0MGLunv7bCXmdQJTwK498R1nUegWz3UMAeg /AsSAdFUnaqLwKKT6QgmKx0DdSlXGiPm/ytI6OTfoPqN6ocerCQd0O8i8p/jDHPx27eQ xfTIda10F3ka6LTz9/nXRPJ53U3qHS73SrAsthE7fL+7VkCIHgw0/oNnBribrHCITMnP JybAeEzqgfAipHq82VLwPigRdn9gC2UjQZMtR6bs2ksK/PnI6dpfgD0SW4TTJbDw5UhB gFM1n8C0mLh69j6lW9YKtPqCGDpLnKMVqCvjuxxEaPJeSW7gt7HBJc+3yVKEUwUKLBzC FIsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=iwCHC5zYGGXmRt70+BuzxFh5vRmOK8/ztMHW5zGIQq0=; b=AI+w5SS1sSDFym+9Hbjbn/t0CzyDBBkRp+h+MUnc0+wtlrBHYNATBwCN4hPe/xGwvS rS3s2FOD+Vtx3GdF6kng54W7eb6g9wH8XtZd7nI28YylfsCegRwBcsJIGdtzERLf5V9a puBwfo8pGRyBYCaVz9WDcUtpLqznzSQVjDN4MQvrKUhjv1IGDQhzfNxzBTi3p6WlifGl A7zKAW2O91MfOlLSM1L76bhYtVDwx1NJr24E8tU0s/OB68nt3uXtRIdeC4W+CCNXQGSU pJ1DivgDB4c3PDb6BsX1fhIS4uJQRaNhOhT44WuO06+vvkeJ1y/79zcfkBfbDWBKaePG EiDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QcdlxC8U; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.71.225]) by smtp.gmail.com with ESMTPSA id j11-20020aa7928b000000b0050dc7628133sm3861420pfa.13.2022.05.27.09.48.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 May 2022 09:48:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH v5 13/17] target/m68k: Implement FTRAPcc Date: Fri, 27 May 2022 09:48:03 -0700 Message-Id: <20220527164807.135038-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220527164807.135038-1-richard.henderson@linaro.org> References: <20220527164807.135038-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/translate.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 0cd7ef89e3..a3141d7f77 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -5567,6 +5567,35 @@ DISAS_INSN(fscc) tcg_temp_free(tmp); } +DISAS_INSN(ftrapcc) +{ + DisasCompare c; + uint16_t ext; + int cond; + + ext = read_im16(env, s); + cond = ext & 0x3f; + + /* Consume and discard the immediate operand. */ + switch (extract32(insn, 0, 3)) { + case 2: /* ftrapcc.w */ + (void)read_im16(env, s); + break; + case 3: /* ftrapcc.l */ + (void)read_im32(env, s); + break; + case 4: /* ftrapcc (no operand) */ + break; + default: + /* Illegal insn */ + disas_undef(env, s, insn); + return; + } + + gen_fcc_cond(&c, s, cond); + do_trapcc(s, &c); +} + #if defined(CONFIG_SOFTMMU) DISAS_INSN(frestore) { @@ -6190,6 +6219,7 @@ void register_m68k_insns (CPUM68KState *env) INSN(fbcc, f280, ffc0, CF_FPU); INSN(fpu, f200, ffc0, FPU); INSN(fscc, f240, ffc0, FPU); + INSN(ftrapcc, f278, fff8, FPU); INSN(fbcc, f280, ff80, FPU); #if defined(CONFIG_SOFTMMU) INSN(frestore, f340, ffc0, CF_FPU); From patchwork Fri May 27 16:48:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 576524 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:8607:0:0:0:0 with SMTP id bb7csp820466mab; Fri, 27 May 2022 10:09:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwsb7wR4ttX4HiG/WPLB8VIc1GTAcFPAXLZYwGxPEKjpQObNAutT4F92RjyYGR6cx4tOsit X-Received: by 2002:a05:6214:1bca:b0:462:12c7:e51c with SMTP id m10-20020a0562141bca00b0046212c7e51cmr29951424qvc.16.1653671365107; Fri, 27 May 2022 10:09:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653671365; cv=none; d=google.com; s=arc-20160816; b=MAIPD3H2l5LCeuUadBWIQSQN/8pYBaBUv3W3HHRgMCN3zcIJYSfKNqLGUNhv9zO24W ayOyVNKsnOO4WfwcIv9ffWB/sosB+9TFyjl+OQuyfdP9QJgXJfYgwFMAz+5oVWXPIZU6 hcuuVklRnd135r2a6SgEDU1CUXlbx52OUAm2R3Fngft/WndKI3mJ5uA/snTVVxV4S4Dj YaHjr0dRYcfy2qVL6MP9wcgTf6NhgtXaXKLjQhhY79wbVUa4D3rjcxS2ZtHJCKypfNKX 6UwZ+JJBpX6007IWI5/FvIfaN6vHeVzi7XIsZnFNEKoXb8zz9OpYUeypicSXK1zXs6cP 8ssA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Ec0dbY3Lo89Y5jy2prv7uGoDI+hJWJ+BkmpUFqfWdho=; b=cMM6al2Lo0K77WosozaQNreuULUoPKgpJcEZomYwIekYDc+71AlaEQr490vW5qkF02 j+HMX9vxhj7HryyyYCEMxuOzrMWL7CxjyhYMe5eI2mnVykfn64IMlRU8KKqLcspqemxe a4wdmsDS3WUnMIw4/YCVcO4E0yNkx0rRKVEG98PYLeC8Ga4OSKoJncyxBCMhxXIjM52Y c/iwqlkc7aZSY8iPgFlqxS1zDN/gIm0d6cxBN4SAyN0ZbZAwNnKXAhLFh1rLQ52hAZU8 8kYzfkQ8rDuyA+TNJrhhz+iRWRUeBBAOV4mWWonqR9ERRvXqiqFZniIW9xsRpY5V4n9D 8MFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vVw1Mejz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.71.225]) by smtp.gmail.com with ESMTPSA id j11-20020aa7928b000000b0050dc7628133sm3861420pfa.13.2022.05.27.09.48.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 May 2022 09:48:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH v5 14/17] tests/tcg/m68k: Add trap.c Date: Fri, 27 May 2022 09:48:04 -0700 Message-Id: <20220527164807.135038-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220527164807.135038-1-richard.henderson@linaro.org> References: <20220527164807.135038-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Test various trap instructions: chk, div, trap, trapv, trapcc, ftrapcc, and the signals and addresses that we expect from them. Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- tests/tcg/m68k/trap.c | 129 +++++++++++++++++++++++++++++++++ tests/tcg/m68k/Makefile.target | 3 + 2 files changed, 132 insertions(+) create mode 100644 tests/tcg/m68k/trap.c diff --git a/tests/tcg/m68k/trap.c b/tests/tcg/m68k/trap.c new file mode 100644 index 0000000000..96cac18d4d --- /dev/null +++ b/tests/tcg/m68k/trap.c @@ -0,0 +1,129 @@ +/* + * Test m68k trap addresses. + */ + +#define _GNU_SOURCE 1 +#include +#include +#include + +static int expect_sig; +static int expect_si_code; +static void *expect_si_addr; +static greg_t expect_mc_pc; +static volatile int got_signal; + +static void sig_handler(int sig, siginfo_t *si, void *puc) +{ + ucontext_t *uc = puc; + mcontext_t *mc = &uc->uc_mcontext; + + assert(sig == expect_sig); + assert(si->si_code == expect_si_code); + assert(si->si_addr == expect_si_addr); + assert(mc->gregs[R_PC] == expect_mc_pc); + + got_signal = 1; +} + +#define FMT_INS [ad] "a"(&expect_si_addr), [pc] "a"(&expect_mc_pc) +#define FMT0_STR(S) \ + "move.l #1f, (%[ad])\n\tmove.l #1f, (%[pc])\n" S "\n1:\n" +#define FMT2_STR(S) \ + "move.l #0f, (%[ad])\n\tmove.l #1f, (%[pc])\n" S "\n1:\n" + +#define CHECK_SIG do { assert(got_signal); got_signal = 0; } while (0) + +int main(int argc, char **argv) +{ + struct sigaction act = { + .sa_sigaction = sig_handler, + .sa_flags = SA_SIGINFO + }; + int t0, t1; + + sigaction(SIGILL, &act, NULL); + sigaction(SIGTRAP, &act, NULL); + sigaction(SIGFPE, &act, NULL); + + expect_sig = SIGFPE; + expect_si_code = FPE_INTOVF; + asm volatile(FMT2_STR("0:\tchk %0, %1") : : "d"(0), "d"(-1), FMT_INS); + CHECK_SIG; + +#if 0 + /* FIXME: chk2 not correctly translated. */ + int bounds[2] = { 0, 1 }; + asm volatile(FMT2_STR("0:\tchk2.l %0, %1") + : : "m"(bounds), "d"(2), FMT_INS); + CHECK_SIG; +#endif + + asm volatile(FMT2_STR("cmp.l %0, %1\n0:\ttrapv") + : : "d"(INT_MIN), "d"(1), FMT_INS); + CHECK_SIG; + + asm volatile(FMT2_STR("cmp.l %0, %0\n0:\ttrapeq") + : : "d"(0), FMT_INS); + CHECK_SIG; + + asm volatile(FMT2_STR("cmp.l %0, %0\n0:\ttrapeq.w #0x1234") + : : "d"(0), FMT_INS); + CHECK_SIG; + + asm volatile(FMT2_STR("cmp.l %0, %0\n0:\ttrapeq.l #0x12345678") + : : "d"(0), FMT_INS); + CHECK_SIG; + + asm volatile(FMT2_STR("fcmp.x %0, %0\n0:\tftrapeq") + : : "f"(0.0L), FMT_INS); + CHECK_SIG; + + expect_si_code = FPE_INTDIV; + + asm volatile(FMT2_STR("0:\tdivs.w %1, %0") + : "=d"(t0) : "d"(0), "0"(1), FMT_INS); + CHECK_SIG; + + asm volatile(FMT2_STR("0:\tdivsl.l %2, %1:%0") + : "=d"(t0), "=d"(t1) : "d"(0), "0"(1), FMT_INS); + CHECK_SIG; + + expect_sig = SIGILL; + expect_si_code = ILL_ILLTRP; + asm volatile(FMT0_STR("trap #1") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #2") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #3") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #4") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #5") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #6") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #7") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #8") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #9") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #10") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #11") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #12") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #13") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #14") : : FMT_INS); + CHECK_SIG; + + expect_sig = SIGTRAP; + expect_si_code = TRAP_BRKPT; + asm volatile(FMT0_STR("trap #15") : : FMT_INS); + CHECK_SIG; + + return 0; +} diff --git a/tests/tcg/m68k/Makefile.target b/tests/tcg/m68k/Makefile.target index 62f109eef4..1163c7ef03 100644 --- a/tests/tcg/m68k/Makefile.target +++ b/tests/tcg/m68k/Makefile.target @@ -3,5 +3,8 @@ # m68k specific tweaks - specifically masking out broken tests # +VPATH += $(SRC_PATH)/tests/tcg/m68k +TESTS += trap + # On m68k Linux supports 4k and 8k pages (but 8k is currently broken) EXTRA_RUNS+=run-test-mmap-4096 # run-test-mmap-8192 From patchwork Fri May 27 16:48:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 576523 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:8607:0:0:0:0 with SMTP id bb7csp818881mab; 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[174.21.71.225]) by smtp.gmail.com with ESMTPSA id j11-20020aa7928b000000b0050dc7628133sm3861420pfa.13.2022.05.27.09.48.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 May 2022 09:48:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v5 15/17] linux-user/strace: Use is_error in print_syscall_err Date: Fri, 27 May 2022 09:48:05 -0700 Message-Id: <20220527164807.135038-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220527164807.135038-1-richard.henderson@linaro.org> References: <20220527164807.135038-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Errors are not all negative numbers: use is_error. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Reviewed-by: Laurent Vivier --- linux-user/strace.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux-user/strace.c b/linux-user/strace.c index 9fa681dea9..7d882526da 100644 --- a/linux-user/strace.c +++ b/linux-user/strace.c @@ -689,7 +689,7 @@ print_syscall_err(abi_long ret) const char *errstr; qemu_log(" = "); - if (ret < 0) { + if (is_error(ret)) { errstr = target_strerror(-ret); if (errstr) { qemu_log("-1 errno=%d (%s)", (int)-ret, errstr); From patchwork Fri May 27 16:48:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 576519 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:8607:0:0:0:0 with SMTP id bb7csp815369mab; Fri, 27 May 2022 10:03:41 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx8fm75MGMSPFESBMGU6n07vLfLW7R99BIU/Tf4o+NAGHqnU3rOw2TmqaErDejTytxtv5n3 X-Received: by 2002:a05:622a:1484:b0:2f3:c837:57a6 with SMTP id t4-20020a05622a148400b002f3c83757a6mr34194068qtx.460.1653671021777; Fri, 27 May 2022 10:03:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653671021; cv=none; d=google.com; s=arc-20160816; b=nhgtNsYOwfGHDkqVL9JHUP5oLmAX0U5ti4/pvj8S86Py7EsIAY5lQneGZL+aXNWxqC 3CrAfCxOUIc4tazh1MFqo+m6K/bkfPFv11sbEwRP/jdRLiH6MHg9GbR2rqVO+MOLsf0e o6VpFMivpUriALSJzkZOAaFujrBSDMM8vPsOX9wY7xknkyID3+eU1eC8CJ4MImyXS2jL YREWocBcdqNsbhGC+LvZ+V4FPkeJhvwTWwH/2i5+xUV1wS4PNFPgXJrQk0dK6T2YHL8t q09fOJHiFtcRmphD9PiAdkZAaR0xuaWG7xvERw8T2ae0qn4w3Y8tg9hnfowpFEjzxSKG scHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=frtjY4kXdf+btOwpubtlaBEs6SblJPqCp8QSyGl5a7Y=; b=Qr67PR6pDpFup+r9lq9SImTpsINUDxftSl6BLscUVRD59qxblTztTraxtpY0poqQdf N4B9xRkEP355OWGDsu5H60uvq3Z03bE9RCX/OVCyrScxK9iqMsY+MPDU77u7CTsWXyOq GpZvasoii0DgfLNDYGgnqIl2EcLMIejzQ71v2FWCsLBacu/fLZHjQMV22xOtOTVggx/L blv3rSkvgVEIJ1LNfLYoMWrCyhdbkOp+4yMG/pigBKmEtrq3iavyl9Jrf4GEbu6omNjc WwkFQqx4kTI1suKxqN4jRfEikJJd/NX8rGWodokJUyT+CyzWgwE2lRA6y+z858vYqbao QHPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=a+PuiOW9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.71.225]) by smtp.gmail.com with ESMTPSA id j11-20020aa7928b000000b0050dc7628133sm3861420pfa.13.2022.05.27.09.48.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 May 2022 09:48:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu Subject: [PATCH v5 16/17] linux-user/strace: Adjust get_thread_area for m68k Date: Fri, 27 May 2022 09:48:06 -0700 Message-Id: <20220527164807.135038-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220527164807.135038-1-richard.henderson@linaro.org> References: <20220527164807.135038-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Unlike i386, m68k get_thread_area has no arguments. Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- linux-user/strace.list | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/linux-user/strace.list b/linux-user/strace.list index 278596acd1..72e17b1acf 100644 --- a/linux-user/strace.list +++ b/linux-user/strace.list @@ -384,8 +384,13 @@ { TARGET_NR_getsockopt, "getsockopt" , NULL, NULL, NULL }, #endif #ifdef TARGET_NR_get_thread_area +#if defined(TARGET_I386) && defined(TARGET_ABI32) { TARGET_NR_get_thread_area, "get_thread_area", "%s(0x"TARGET_ABI_FMT_lx")", NULL, NULL }, +#elif defined(TARGET_M68K) +{ TARGET_NR_get_thread_area, "get_thread_area" , "%s()", + NULL, print_syscall_ret_addr }, +#endif #endif #ifdef TARGET_NR_gettid { TARGET_NR_gettid, "gettid" , "%s()", NULL, NULL }, From patchwork Fri May 27 16:48:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 576522 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:8607:0:0:0:0 with SMTP id bb7csp818285mab; Fri, 27 May 2022 10:06:43 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxeN9STOHAHY+wRQboyaDf0+1hdd/7ASC1f7yScmphDHhEi0vJ8V+drUATQ0sYl/vuierPN X-Received: by 2002:a05:622a:1a82:b0:2f3:b411:e016 with SMTP id s2-20020a05622a1a8200b002f3b411e016mr34408526qtc.218.1653671203702; Fri, 27 May 2022 10:06:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653671203; cv=none; d=google.com; s=arc-20160816; b=mtnkCQDfR07jjJQpD5ziLX5m8GAUKcpy/DS9DaYU07yN/fOePmg2mfYXLcQB2fMSA0 VhwB1WSDUq0zpsXtYuvCM4c8jAeSSJh7y+uuYbgfQc6xlQAdM7KwukNZTVdQu+Zj+tBo +0bworqcy7aw+Pr118i1pO41am1m95zuQpoHHd62m85D/xMTAIAyKjySD5PocBlzCjGW gKzpJEj7YUTdr+sbNeBnlRUTHbhnqQTdjlZsXZa8vaBChxoqt0UhAljucWNQRHTwo9We 4UQvz26lMK2V2bllIw5zqNUOE9E6kN5xnY0Yk6BPdZtluBNjlWu/cY7ZDkTpESnN+Twm jJMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=IPe9v04jpSOnM1YqKXysVjOVagzaKcyYJ8pPspoxKJ4=; b=mAk3h8NBd1tV+CFhWITf8vmL8LCjcYMo70wpGPj/+LEfrfwyjpjF0dcKy4MShfVZ+6 5f01EIYbmnKJXXNdmCu6zvyP0uEhrPu7Qc6LfOIgglYVYMB3x/3gk/pyUk8Q0IswU8fl voV4T3pr/qIbmbtpfqPpR5y2Ru+vwQijKHSK3u8Du+4RsbGXUUj5+Rp44nQI7L4Zw2sx Xm96nfP/m8apPjzWmmAKHoux+s0WC8DdtB8oo4pgJp2YRBJfiEwAbRBg8X1fvD7b13b6 bOi0u2ZfVnUNn9eo4mVDnivqiFTHhG0wqvUSc+PqONMiGeEwRoXcKtNLbbeIpIZCqYqs JLPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cc3NKSUy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.71.225]) by smtp.gmail.com with ESMTPSA id j11-20020aa7928b000000b0050dc7628133sm3861420pfa.13.2022.05.27.09.48.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 May 2022 09:48:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v5 17/17] target/m68k: Mark helper_raise_exception as noreturn Date: Fri, 27 May 2022 09:48:07 -0700 Message-Id: <20220527164807.135038-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220527164807.135038-1-richard.henderson@linaro.org> References: <20220527164807.135038-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Also mark raise_exception_ra and raise_exception, lest we generate a warning about helper_raise_exception returning. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/helper.h | 2 +- target/m68k/op_helper.c | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/target/m68k/helper.h b/target/m68k/helper.h index f016c4c1c2..c9bed2b884 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -109,7 +109,7 @@ DEF_HELPER_3(set_mac_extu, void, env, i32, i32) DEF_HELPER_2(flush_flags, void, env, i32) DEF_HELPER_2(set_ccr, void, env, i32) DEF_HELPER_FLAGS_1(get_ccr, TCG_CALL_NO_WG_SE, i32, env) -DEF_HELPER_2(raise_exception, void, env, i32) +DEF_HELPER_2(raise_exception, noreturn, env, i32) DEF_HELPER_FLAGS_3(bfffo_reg, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 61948d92bb..d9937ca8dc 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -532,7 +532,8 @@ bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request) #endif /* !CONFIG_USER_ONLY */ -static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr) +G_NORETURN static void +raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr) { CPUState *cs = env_cpu(env); @@ -540,7 +541,7 @@ static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr) cpu_loop_exit_restore(cs, raddr); } -static void raise_exception(CPUM68KState *env, int tt) +G_NORETURN static void raise_exception(CPUM68KState *env, int tt) { raise_exception_ra(env, tt, 0); }