From patchwork Thu May 26 10:11:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 576334 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5809DC433F5 for ; Thu, 26 May 2022 10:11:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231981AbiEZKLp (ORCPT ); Thu, 26 May 2022 06:11:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41446 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346961AbiEZKLo (ORCPT ); Thu, 26 May 2022 06:11:44 -0400 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 52A6A10EE for ; Thu, 26 May 2022 03:11:43 -0700 (PDT) Received: by mail-pl1-x631.google.com with SMTP id w3so1039851plp.13 for ; Thu, 26 May 2022 03:11:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R1Oz1yAZDHQvhQh2SWx4vMTfkt8zOrGF2iQud75B5Lk=; b=MeBvlYLKJh6EnE4Nk4fnvlwLHRYUqSTpb3CTh8pn85TV32ZdSCclJiU4pcvaTDtwkA RZbKn8P//rgHWSQg9zJ8xqvTjG1wd8fm2yEN7plSFM4jAukcfO5ZPNZLN62yaHGP446f OsYZwKq12ORSAtDuUkFSQa3gr9WaXe7cH1K+StKOeIZS26YGAlqMye3q8lokxQ5dSMcF jKEKvVeOJ9qWyneCm3ObTYXlMLJK1mEq5SeCL4CISyt3QDyZVcMYYWoKUkSRXRt/iNOJ y+BTc8jKia4Tyw239NwQz9dEOEI5n8gY6PO71NKx3vrvGN9W1RCwgirGLD4gqqsJjqf3 ohBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=R1Oz1yAZDHQvhQh2SWx4vMTfkt8zOrGF2iQud75B5Lk=; b=j7ksEvGwga+f27yvtu55VustxYmm2hvp6TawdSyfwE876ulPKyRTIe256PpxRc5Mti wOhxwvKvFhdp3GRR20y4yKJwXGNb2dzMG4bmO1v3fVbK+5v4dSSTFsYOTSk5hRpVBlCc t/OOh1LtP2FhE31KiSrPkVGK5isP4aoGtacLGpUsxpJUIttTkVb8qpYZU5LRgYCpQQeH DZ4DsX/F9C3w62svrjbbm0E7qw07VfOJGxaICld4s3a/VGEbUR7Q4/Z3deztnJ2q48Mo yrOizPx25OIJDtOk6nta+EvYhcyLf8Fj9Wgy7jPTSqatKgZNboWeCUqLCRKV6yH70Izv u1qg== X-Gm-Message-State: AOAM531J4+mbJj9td9P4fD7wsQgKLUlPUpyy4YUc/50wRP7qgJN5hQ2x bKQf0MHabjx+r8shyHQBUgQUsw== X-Google-Smtp-Source: ABdhPJyAv5zPzU2IwZPeCQVSm/VsddqxuggiHGPcUvNa4rsGUhxfdC58ncib9zaXi0NWNziwb/aigQ== X-Received: by 2002:a17:902:8bca:b0:15f:28b6:ad46 with SMTP id r10-20020a1709028bca00b0015f28b6ad46mr37153228plo.69.1653559902867; Thu, 26 May 2022 03:11:42 -0700 (PDT) Received: from kerodipc.Dlink ([49.206.9.238]) by smtp.gmail.com with ESMTPSA id z17-20020a170902d55100b0015f309f14d0sm1114861plf.56.2022.05.26.03.11.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 03:11:42 -0700 (PDT) From: Sunil V L To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Ard Biesheuvel , Marc Zyngier , Atish Patra , Heinrich Schuchardt , Anup Patel Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Sunil V L , Sunil V L Subject: [PATCH V2 1/5] riscv: cpu_ops_sbi: Support for 64bit hartid Date: Thu, 26 May 2022 15:41:27 +0530 Message-Id: <20220526101131.2340729-2-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220526101131.2340729-1-sunilvl@ventanamicro.com> References: <20220526101131.2340729-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-efi@vger.kernel.org The hartid can be a 64bit value on RV64 platforms. This patch modifies the hartid variable type to unsigned long so that it can hold 64bit value on RV64 platforms. Signed-off-by: Sunil V L Reviewed-by: Heinrich Schuchardt Reviewed-by: Atish Patra --- arch/riscv/kernel/cpu_ops_sbi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/cpu_ops_sbi.c b/arch/riscv/kernel/cpu_ops_sbi.c index 4f5a6f84e2a4..efa0f0816634 100644 --- a/arch/riscv/kernel/cpu_ops_sbi.c +++ b/arch/riscv/kernel/cpu_ops_sbi.c @@ -65,7 +65,7 @@ static int sbi_hsm_hart_get_status(unsigned long hartid) static int sbi_cpu_start(unsigned int cpuid, struct task_struct *tidle) { unsigned long boot_addr = __pa_symbol(secondary_start_sbi); - int hartid = cpuid_to_hartid_map(cpuid); + unsigned long hartid = cpuid_to_hartid_map(cpuid); unsigned long hsm_data; struct sbi_hart_boot_data *bdata = &per_cpu(boot_data, cpuid); @@ -107,7 +107,7 @@ static void sbi_cpu_stop(void) static int sbi_cpu_is_stopped(unsigned int cpuid) { int rc; - int hartid = cpuid_to_hartid_map(cpuid); + unsigned long hartid = cpuid_to_hartid_map(cpuid); rc = sbi_hsm_hart_get_status(hartid); From patchwork Thu May 26 10:11:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 577509 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67437C4332F for ; Thu, 26 May 2022 10:12:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346999AbiEZKL5 (ORCPT ); Thu, 26 May 2022 06:11:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346966AbiEZKLx (ORCPT ); Thu, 26 May 2022 06:11:53 -0400 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2431E218F for ; Thu, 26 May 2022 03:11:47 -0700 (PDT) Received: by mail-pl1-x635.google.com with SMTP id d22so1049894plr.9 for ; Thu, 26 May 2022 03:11:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wbBG7lEDJH2LFVXucK5oQ/R2hCfil/fSiH5Kza4Gi8k=; b=V5XR0cYmYpPHz45TXlrQdMJrLi9mC6lsy2W+x/KJ31gATxWb3Jcl0MrAB+D24bI7f3 4cWVas5pCyylxxCZLBWe4mQfSoke/VDU2WYlrymgElTYZAOaG723fCyOoELiQShkPJOT 1JZwGsy0Lp23kfxFyXK4dhbP3HKfGwYOKkJB0bxLkU+akzyGUbizbF/W22JUzStz/kvb /YZE17RoALpfuH1WSU7xai3fAWdlXw2P6hUoIe1PwT4W09BwfsX4JWi9svdHWlFZSnTi XZgvOErgNi8zbTcAf6Ej1LPhdSLC9CuCpS7dDMCmuN5koT27cwVrnYTiCV3TrhPaZwT8 /aOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wbBG7lEDJH2LFVXucK5oQ/R2hCfil/fSiH5Kza4Gi8k=; b=ZUWsMpXytxlmw0/n1l22dla+ReEG1EL3C36VbdMD6BvpzVDO/wA58er0aK6tpBjmdX YVkf2fqAHhkXXdprv/OCP0PPpnPif/Z2AFMHW55rCXIUP+6XZwS7JjfpkDQ8k4LLouMQ UCXdJcvHTItp8m5vCAWaV0erp74SQu6ae9DlUr7qFZAvwy586dQ1/yu6U6cVvwizX61P kV4TZa8qrH8gN2BbvWJtKw4J3qU0chmizU+HtBYUFHxmnEIUNIei3Aj8NsYfUdTOOhPN KWsEcCB+efKlwkKTyTr0gBEAKxcb4eOmE0aaGYTLGbHxLnoRRAhrKtACkej3L229/P+s pT4w== X-Gm-Message-State: AOAM530r2AaQSzWKBtVuz5X7g2Zy58O4Y9NVWqmb4rjVqcc554sRMfO6 qLGPB2sQDRMMhqBmp1mxK9uAdPG5DOjh+Rez X-Google-Smtp-Source: ABdhPJwr+qQVKMcopGMW+cRM74SlJB+kkVtaSsSNVzIL44tSlSNiDBT302sF2fUP6vTOWuit+8GjCQ== X-Received: by 2002:a17:902:d50e:b0:163:80b4:30a3 with SMTP id b14-20020a170902d50e00b0016380b430a3mr937520plg.159.1653559907098; Thu, 26 May 2022 03:11:47 -0700 (PDT) Received: from kerodipc.Dlink ([49.206.9.238]) by smtp.gmail.com with ESMTPSA id z17-20020a170902d55100b0015f309f14d0sm1114861plf.56.2022.05.26.03.11.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 03:11:46 -0700 (PDT) From: Sunil V L To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Ard Biesheuvel , Marc Zyngier , Atish Patra , Heinrich Schuchardt , Anup Patel Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Sunil V L , Sunil V L , stable@vger.kernel.org Subject: [PATCH V2 2/5] riscv: spinwait: Fix hartid variable type Date: Thu, 26 May 2022 15:41:28 +0530 Message-Id: <20220526101131.2340729-3-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220526101131.2340729-1-sunilvl@ventanamicro.com> References: <20220526101131.2340729-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-efi@vger.kernel.org The hartid variable is of type int but compared with ULONG_MAX(INVALID_HARTID). This issue is fixed by changing the hartid variable type to unsigned long. Fixes: c78f94f35cf6 ("RISC-V: Use __cpu_up_stack/task_pointer only for spinwait method") Cc: stable@vger.kernel.org Signed-off-by: Sunil V L --- arch/riscv/kernel/cpu_ops_spinwait.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/cpu_ops_spinwait.c b/arch/riscv/kernel/cpu_ops_spinwait.c index 346847f6c41c..3ade9152a3c7 100644 --- a/arch/riscv/kernel/cpu_ops_spinwait.c +++ b/arch/riscv/kernel/cpu_ops_spinwait.c @@ -18,7 +18,7 @@ void *__cpu_spinwait_task_pointer[NR_CPUS] __section(".data"); static void cpu_update_secondary_bootdata(unsigned int cpuid, struct task_struct *tidle) { - int hartid = cpuid_to_hartid_map(cpuid); + unsigned long hartid = cpuid_to_hartid_map(cpuid); /* * The hartid must be less than NR_CPUS to avoid out-of-bound access @@ -27,7 +27,7 @@ static void cpu_update_secondary_bootdata(unsigned int cpuid, * spinwait booting is not the recommended approach for any platforms * booting Linux in S-mode and can be disabled in the future. */ - if (hartid == INVALID_HARTID || hartid >= NR_CPUS) + if (hartid == INVALID_HARTID || hartid >= (unsigned long) NR_CPUS) return; /* Make sure tidle is updated */ From patchwork Thu May 26 10:11:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 576333 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5DB32C433EF for ; Thu, 26 May 2022 10:12:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346964AbiEZKMA (ORCPT ); Thu, 26 May 2022 06:12:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346975AbiEZKL5 (ORCPT ); Thu, 26 May 2022 06:11:57 -0400 Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D28341119 for ; Thu, 26 May 2022 03:11:51 -0700 (PDT) Received: by mail-pl1-x630.google.com with SMTP id q18so1044802pln.12 for ; Thu, 26 May 2022 03:11:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3wURJ7f8wK/rYX1AWremJ6WWxVIvdF4W4fcHK+urU4Y=; b=lGJPvC3W+KdDytFN09EumhPJrVSmrwGdIlDlX0GeN/DoMzCv8kpUJVZJ3ZwxjFOOW3 bc3zhkW3fIOhwGJRYktfEaa6VNws2H+5LeTtokOCeN7bGS0nVMAdKnCv/A1bWKN7GVQg 7l9zc2sLOaEwGo/OCT8s09I3+rVZEiuGWAX6JEr/moa/ahGPNGvoq2coD9OCgH0p2ybK 8um1khDECGbpWGLs20DbAfVxDv4gd4sfJt1KiyrK9oeHpJtqHsj7m3s4qUAA3EYTiml1 RcZeE0Hm7CulTjv7sdEW5sdjPx+nXybfeWjLOZxocdhADUQdz6Ry1qcD3twvtA/wV+mt n8aQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3wURJ7f8wK/rYX1AWremJ6WWxVIvdF4W4fcHK+urU4Y=; b=7upjbPM3MvaZKrMv0iQihUXfNd6wf7UYBiGNXu3rt1VBPMNHHNFTLf7RA9JKVRJ1Uz cAodqZk0ptm+XqbNlNBuo4A5+oGGDB+20RUMnr+T07llskYgH78xR9sgbL25hthVhaHx ALjpM+CK6qSfwa7ubcBP4529iPAmdgilLdEIkTEUGemSt1jrXu7blgGqo1z6l8oAeNHP e7BsUzsf9eaXtX1LZ1R+VDrG9iCqhJgAuEdNFBJT/yiQiqZkfKmQjOZGniw2xgRXaDSg DKPLBBxZqICPJRRjGcbQpUfqo59NKCunBo7sKYAcamQYpNP9/K5d4WKzjxiELSIeNmiH Y4pw== X-Gm-Message-State: AOAM530eCv9LXIsKnk4Cum/0AI3WiNrUQK3nYX+NvFXU/i+mUzrTaaIe po7DjQLBbp9dg2gZFloOSp/Odw== X-Google-Smtp-Source: ABdhPJyHqPUWM6TLaBadwtJgoFX8sqXAz9turIY6bW9WSl9x0ZGa0cM73mxFnfgICJ1iaqcFQ+3yLw== X-Received: by 2002:a17:902:e14c:b0:163:86e0:2137 with SMTP id d12-20020a170902e14c00b0016386e02137mr122325pla.89.1653559911140; Thu, 26 May 2022 03:11:51 -0700 (PDT) Received: from kerodipc.Dlink ([49.206.9.238]) by smtp.gmail.com with ESMTPSA id z17-20020a170902d55100b0015f309f14d0sm1114861plf.56.2022.05.26.03.11.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 03:11:50 -0700 (PDT) From: Sunil V L To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Ard Biesheuvel , Marc Zyngier , Atish Patra , Heinrich Schuchardt , Anup Patel Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Sunil V L , Sunil V L Subject: [PATCH V2 3/5] riscv: smp: Support for 64bit hartid Date: Thu, 26 May 2022 15:41:29 +0530 Message-Id: <20220526101131.2340729-4-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220526101131.2340729-1-sunilvl@ventanamicro.com> References: <20220526101131.2340729-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-efi@vger.kernel.org The hartid can be a 64bit value on RV64 platforms. This patch modifies the hartid parameter in riscv_hartid_to_cpuid() as unsigned long so that it can hold 64bit value on RV64 platforms. Signed-off-by: Sunil V L Reviewed-by: Heinrich Schuchardt Reviewed-by: Atish Patra --- arch/riscv/include/asm/smp.h | 4 ++-- arch/riscv/kernel/smp.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 23170c933d73..d3443be7eedc 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -42,7 +42,7 @@ void arch_send_call_function_ipi_mask(struct cpumask *mask); /* Hook for the generic smp_call_function_single() routine. */ void arch_send_call_function_single_ipi(int cpu); -int riscv_hartid_to_cpuid(int hartid); +int riscv_hartid_to_cpuid(unsigned long hartid); /* Set custom IPI operations */ void riscv_set_ipi_ops(const struct riscv_ipi_ops *ops); @@ -70,7 +70,7 @@ static inline void show_ipi_stats(struct seq_file *p, int prec) { } -static inline int riscv_hartid_to_cpuid(int hartid) +static inline int riscv_hartid_to_cpuid(unsigned long hartid) { if (hartid == boot_cpu_hartid) return 0; diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index b5d30ea92292..018e7dc45df6 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -47,7 +47,7 @@ static struct { unsigned long bits ____cacheline_aligned; } ipi_data[NR_CPUS] __cacheline_aligned; -int riscv_hartid_to_cpuid(int hartid) +int riscv_hartid_to_cpuid(unsigned long hartid) { int i; @@ -55,7 +55,7 @@ int riscv_hartid_to_cpuid(int hartid) if (cpuid_to_hartid_map(i) == hartid) return i; - pr_err("Couldn't find cpu id for hartid [%d]\n", hartid); + pr_err("Couldn't find cpu id for hartid [%lu]\n", hartid); return -ENOENT; } From patchwork Thu May 26 10:11:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 577508 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 169F3C433F5 for ; Thu, 26 May 2022 10:12:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347040AbiEZKMJ (ORCPT ); Thu, 26 May 2022 06:12:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245750AbiEZKMA (ORCPT ); Thu, 26 May 2022 06:12:00 -0400 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 335A125C6 for ; Thu, 26 May 2022 03:11:55 -0700 (PDT) Received: by mail-pj1-x1034.google.com with SMTP id ge11so1388533pjb.0 for ; Thu, 26 May 2022 03:11:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=K4/jbxyTjaVENdJUeS7U2YJP8/xoYroH7rqKl9F4SxI=; b=ROt7I3Nyr9Q+gowE5eM3uNJ8euXDR5tzpkgOGfYUOtOAcGLm231qu9f9ZfmSSvXSHw NTb1HFQZQ+eqfw3XPO7CZ2/yFfi5qGqik5i3Nxfblr1QjDVw9GQzc5Iud5pT/R9UuzZk ilsjgiimc3WQ3Wst8Ki+8/n26mtVA9dQxWcuUz2c4yygXmsIOIbQbaDoCl10JaO0GBmj WXkDeUd/UJ5U+/fqHWKDbEWX2mylX8PtCoo4Cg9MV/Rh0oa8p/Yo4pKdZfE//mZYDLyo zOFdV/vO+e8FzIklplLayB7HFvPXbg7Z0y+AWZDnYWpaq9WI6mo2fM/EHdcRnW2skZeA pplQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=K4/jbxyTjaVENdJUeS7U2YJP8/xoYroH7rqKl9F4SxI=; b=GOGrCO4LME15VHaU/DOTOwFOX+oh3eHQW/U5PMoAefFmMoPBRi15ise3CxSLos15Z7 oUsW9S8DkzztjM7DyQ16GPZGxGNOFSx6pUTLPjlzRNh0HX8PLI9EU7Hfp0qAGxrZJKQe LP+3n5RqV3wMQvWcrEYYMVk0LTbPhoR02fs89YZSlTtuLniWPVu6qgfxNzJQPs+l8+N7 vIcg+LMjpI070DJV/pF4WI2ZzlmOYl88ujrySJA9l+LJC20m/XUtui7MaIkttSed9CQw 7X47Y4+QBupybcl3ueId8wFUEFeLbOG1YLZeaNdLrpDY5xQ56BM1oye0ROV31gWvt1DD Hizw== X-Gm-Message-State: AOAM531I9rt4g7910ogCiI1eaq0JELyPXk1TsHqBgmjj0MMZPRtza+pQ JSM7fTBgXrvqIbrUCbnj+wKukw== X-Google-Smtp-Source: ABdhPJyhNh+f2oWMXxABwW+fRsFqwZH+cOKOcVHtaehlPykQPu0fAjtvz9npvu9D57G/VIMaJVpokg== X-Received: by 2002:a17:902:7606:b0:161:df31:68f2 with SMTP id k6-20020a170902760600b00161df3168f2mr34397649pll.151.1653559915347; Thu, 26 May 2022 03:11:55 -0700 (PDT) Received: from kerodipc.Dlink ([49.206.9.238]) by smtp.gmail.com with ESMTPSA id z17-20020a170902d55100b0015f309f14d0sm1114861plf.56.2022.05.26.03.11.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 03:11:54 -0700 (PDT) From: Sunil V L To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Ard Biesheuvel , Marc Zyngier , Atish Patra , Heinrich Schuchardt , Anup Patel Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Sunil V L , Sunil V L Subject: [PATCH V2 4/5] riscv: cpu: Support for 64bit hartid Date: Thu, 26 May 2022 15:41:30 +0530 Message-Id: <20220526101131.2340729-5-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220526101131.2340729-1-sunilvl@ventanamicro.com> References: <20220526101131.2340729-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-efi@vger.kernel.org Adds support for 64bit hartid in riscv_of_processor_hartid() - Separate return value and status code. - Make hartid variable type as unsigned long. - Update the callers. Signed-off-by: Sunil V L --- arch/riscv/include/asm/processor.h | 4 ++-- arch/riscv/kernel/cpu.c | 26 +++++++++++++++----------- arch/riscv/kernel/cpufeature.c | 6 ++++-- arch/riscv/kernel/smpboot.c | 9 +++++---- drivers/clocksource/timer-riscv.c | 15 ++++++++------- drivers/irqchip/irq-riscv-intc.c | 7 ++++--- drivers/irqchip/irq-sifive-plic.c | 7 ++++--- 7 files changed, 42 insertions(+), 32 deletions(-) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index 0749924d9e55..99fae9398506 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -75,8 +75,8 @@ static inline void wait_for_interrupt(void) } struct device_node; -int riscv_of_processor_hartid(struct device_node *node); -int riscv_of_parent_hartid(struct device_node *node); +int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid); +int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid); extern void riscv_fill_hwcap(void); extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src); diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index ccb617791e56..477a33b34c95 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -14,37 +14,36 @@ * Returns the hart ID of the given device tree node, or -ENODEV if the node * isn't an enabled and valid RISC-V hart node. */ -int riscv_of_processor_hartid(struct device_node *node) +int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) { const char *isa; - u32 hart; if (!of_device_is_compatible(node, "riscv")) { pr_warn("Found incompatible CPU\n"); return -ENODEV; } - hart = of_get_cpu_hwid(node, 0); - if (hart == ~0U) { + *hart = (unsigned long) of_get_cpu_hwid(node, 0); + if (*hart == ~0UL) { pr_warn("Found CPU without hart ID\n"); return -ENODEV; } if (!of_device_is_available(node)) { - pr_info("CPU with hartid=%d is not available\n", hart); + pr_info("CPU with hartid=%lu is not available\n", *hart); return -ENODEV; } if (of_property_read_string(node, "riscv,isa", &isa)) { - pr_warn("CPU with hartid=%d has no \"riscv,isa\" property\n", hart); + pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart); return -ENODEV; } if (isa[0] != 'r' || isa[1] != 'v') { - pr_warn("CPU with hartid=%d has an invalid ISA of \"%s\"\n", hart, isa); + pr_warn("CPU with hartid=%lu has an invalid ISA of \"%s\"\n", *hart, isa); return -ENODEV; } - return hart; + return 0; } /* @@ -53,11 +52,16 @@ int riscv_of_processor_hartid(struct device_node *node) * To achieve this, we walk up the DT tree until we find an active * RISC-V core (HART) node and extract the cpuid from it. */ -int riscv_of_parent_hartid(struct device_node *node) +int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) { + int rc; + for (; node; node = node->parent) { - if (of_device_is_compatible(node, "riscv")) - return riscv_of_processor_hartid(node); + if (of_device_is_compatible(node, "riscv")) { + rc = riscv_of_processor_hartid(node, hartid); + if (!rc) + return 0; + } } return -1; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1b2d42d7f589..49c05bd9352d 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -67,8 +67,9 @@ void __init riscv_fill_hwcap(void) struct device_node *node; const char *isa; char print_str[NUM_ALPHA_EXTS + 1]; - int i, j; + int i, j, rc; static unsigned long isa2hwcap[256] = {0}; + unsigned long hartid; isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I; isa2hwcap['m'] = isa2hwcap['M'] = COMPAT_HWCAP_ISA_M; @@ -86,7 +87,8 @@ void __init riscv_fill_hwcap(void) DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); const char *temp; - if (riscv_of_processor_hartid(node) < 0) + rc = riscv_of_processor_hartid(node, &hartid); + if (rc < 0) continue; if (of_property_read_string(node, "riscv,isa", &isa)) { diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 622f226454d5..4336610a19ee 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -76,15 +76,16 @@ void __init smp_prepare_cpus(unsigned int max_cpus) void __init setup_smp(void) { struct device_node *dn; - int hart; + unsigned long hart; bool found_boot_cpu = false; int cpuid = 1; + int rc; cpu_set_ops(0); for_each_of_cpu_node(dn) { - hart = riscv_of_processor_hartid(dn); - if (hart < 0) + rc = riscv_of_processor_hartid(dn, &hart); + if (rc < 0) continue; if (hart == cpuid_to_hartid_map(0)) { @@ -94,7 +95,7 @@ void __init setup_smp(void) continue; } if (cpuid >= NR_CPUS) { - pr_warn("Invalid cpuid [%d] for hartid [%d]\n", + pr_warn("Invalid cpuid [%d] for hartid [%lu]\n", cpuid, hart); continue; } diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 1767f8bf2013..55142c27f0bc 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -101,20 +101,21 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id) static int __init riscv_timer_init_dt(struct device_node *n) { - int cpuid, hartid, error; + int cpuid, error; + unsigned long hartid; struct device_node *child; struct irq_domain *domain; - hartid = riscv_of_processor_hartid(n); - if (hartid < 0) { - pr_warn("Not valid hartid for node [%pOF] error = [%d]\n", + error = riscv_of_processor_hartid(n, &hartid); + if (error < 0) { + pr_warn("Not valid hartid for node [%pOF] error = [%lu]\n", n, hartid); - return hartid; + return error; } cpuid = riscv_hartid_to_cpuid(hartid); if (cpuid < 0) { - pr_warn("Invalid cpuid for hartid [%d]\n", hartid); + pr_warn("Invalid cpuid for hartid [%lu]\n", hartid); return cpuid; } @@ -140,7 +141,7 @@ static int __init riscv_timer_init_dt(struct device_node *n) return -ENODEV; } - pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n", + pr_info("%s: Registering clocksource cpuid [%d] hartid [%lu]\n", __func__, cpuid, hartid); error = clocksource_register_hz(&riscv_clocksource, riscv_timebase); if (error) { diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index b65bd8878d4f..499e5f81b3fe 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -95,10 +95,11 @@ static const struct irq_domain_ops riscv_intc_domain_ops = { static int __init riscv_intc_init(struct device_node *node, struct device_node *parent) { - int rc, hartid; + int rc; + unsigned long hartid; - hartid = riscv_of_parent_hartid(node); - if (hartid < 0) { + rc = riscv_of_parent_hartid(node, &hartid); + if (rc < 0) { pr_warn("unable to find hart id for %pOF\n", node); return 0; } diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index bb87e4c3b88e..4710d9741f36 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -317,7 +317,8 @@ static int __init plic_init(struct device_node *node, for (i = 0; i < nr_contexts; i++) { struct of_phandle_args parent; irq_hw_number_t hwirq; - int cpu, hartid; + int cpu; + unsigned long hartid; if (of_irq_parse_one(node, i, &parent)) { pr_err("failed to parse parent for context %d.\n", i); @@ -341,8 +342,8 @@ static int __init plic_init(struct device_node *node, continue; } - hartid = riscv_of_parent_hartid(parent.np); - if (hartid < 0) { + error = riscv_of_parent_hartid(parent.np, &hartid); + if (error < 0) { pr_warn("failed to parse hart ID for context %d.\n", i); continue; } From patchwork Thu May 26 10:11:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 576332 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33503C433F5 for ; Thu, 26 May 2022 10:12:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346986AbiEZKMS (ORCPT ); Thu, 26 May 2022 06:12:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346992AbiEZKMH (ORCPT ); Thu, 26 May 2022 06:12:07 -0400 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4AFD225E1 for ; Thu, 26 May 2022 03:12:00 -0700 (PDT) Received: by mail-pj1-x1032.google.com with SMTP id nn3-20020a17090b38c300b001e0e091cf03so660209pjb.1 for ; Thu, 26 May 2022 03:11:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2nXJi7PiDDt9d1NL5JWtAPFwSienZjCWVKHwZcbhaBc=; b=JOR9LUUFNgj0IhaBYyG+l5lZ0VF9aY94nwBPk8vRUqj9RK+tdsptxfK3s5B99lnFXk 2ccRWc8trH74wUOJ225CGHcpTKEsX6ZzpUjc9JKnZV+6ZpPFVKTgKN0tMyqFUu9NIv5s SjbVlc6K3Cb4zoXyIamBmKjv/NuHbpn5zZE8I+rMWqlqP8gytbUKBiPlVmalQJoENPVJ E0Y615jRLoSaQgCZZ71FCsFsF0sAcF1J5QF36Fe7frEj/tXj+rdciwQp3nGid8lzS5kX D1T5HG613dqG7U8xRPU7+o3Ixt+rfgmhXvITxe1fuQ4PEweHuRsDjHSohwiIS43nevOS ltiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2nXJi7PiDDt9d1NL5JWtAPFwSienZjCWVKHwZcbhaBc=; b=3pQ8V9No2YunRLFo0fKDQLBHzFBDmkrN46Ta91A3Og7We6mDbcoWcFTUiWCvLS4w7L VLoFPYL0NPDNIqVfv9NhhiPXXGdHwPelIAdkoopI0FnQD7TsSO3S+KdRwVYHeQppH4lV G01DSOUQr+jYmFaNjaHkPaE9FtVOd4DpxbSX8gKSCO1+1eDJu/T/yUnGuA/qCcW4SNMR 86TTtb1vwyQMiN5qxSKaHhcEgxh+OE0M0peR/F7pOzh0CDdU07+DTnFuN3g6RfYhqmJN zG2QLHed7kchpPM7DGxqd6YrxN6TYjZGtYRphC5WeMudbmj7zP0ojCRilkMBfhnhQij+ JXsA== X-Gm-Message-State: AOAM5321pFSQVF+u/FM9JY5Enf4qB9VZXpIENvB0FjgXvP+l5apVBEe9 MF2w2hva/vROLUEUQHv55L/hlg== X-Google-Smtp-Source: ABdhPJzk38UFvmZ2o5iGTIUaOlnX9TN0YPEZTK04SPZov7Zl3y6PwSIE61Oh2DmJjFw+uDJ03NumjQ== X-Received: by 2002:a17:90a:408f:b0:1d1:d1ba:2abb with SMTP id l15-20020a17090a408f00b001d1d1ba2abbmr1833141pjg.152.1653559919412; Thu, 26 May 2022 03:11:59 -0700 (PDT) Received: from kerodipc.Dlink ([49.206.9.238]) by smtp.gmail.com with ESMTPSA id z17-20020a170902d55100b0015f309f14d0sm1114861plf.56.2022.05.26.03.11.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 03:11:59 -0700 (PDT) From: Sunil V L To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Thomas Gleixner , Ard Biesheuvel , Marc Zyngier , Atish Patra , Heinrich Schuchardt , Anup Patel Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Sunil V L , Sunil V L Subject: [PATCH V2 5/5] riscv/efi_stub: Support for 64bit boot-hartid Date: Thu, 26 May 2022 15:41:31 +0530 Message-Id: <20220526101131.2340729-6-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220526101131.2340729-1-sunilvl@ventanamicro.com> References: <20220526101131.2340729-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-efi@vger.kernel.org The boot-hartid can be a 64bit value on RV64 platforms. Currently, the "boot-hartid" in DT is assumed to be 32bit only. This patch detects the size of the "boot-hartid" and uses 32bit or 64bit FDT reads appropriately. Signed-off-by: Sunil V L --- drivers/firmware/efi/libstub/riscv-stub.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/firmware/efi/libstub/riscv-stub.c b/drivers/firmware/efi/libstub/riscv-stub.c index 9e85e58d1f27..b450ebf95977 100644 --- a/drivers/firmware/efi/libstub/riscv-stub.c +++ b/drivers/firmware/efi/libstub/riscv-stub.c @@ -8,6 +8,7 @@ #include #include +#include #include "efistub.h" @@ -29,7 +30,7 @@ static int get_boot_hartid_from_fdt(void) { const void *fdt; int chosen_node, len; - const fdt32_t *prop; + const void *prop; fdt = get_efi_config_table(DEVICE_TREE_GUID); if (!fdt) @@ -40,10 +41,16 @@ static int get_boot_hartid_from_fdt(void) return -EINVAL; prop = fdt_getprop((void *)fdt, chosen_node, "boot-hartid", &len); - if (!prop || len != sizeof(u32)) + if (!prop) + return -EINVAL; + + if (len == sizeof(u32)) + hartid = (unsigned long) fdt32_to_cpu(*(fdt32_t *)prop); + else if (len == sizeof(u64)) + hartid = (unsigned long) fdt64_to_cpu(__get_unaligned_t(fdt64_t, prop)); + else return -EINVAL; - hartid = fdt32_to_cpu(*prop); return 0; }