From patchwork Wed May 25 18:58:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Kocialkowski X-Patchwork-Id: 576061 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54CD5C4332F for ; Wed, 25 May 2022 18:59:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343884AbiEYS7O (ORCPT ); Wed, 25 May 2022 14:59:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60522 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343878AbiEYS7O (ORCPT ); Wed, 25 May 2022 14:59:14 -0400 Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [217.70.183.199]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F3CBD34BA7; Wed, 25 May 2022 11:59:12 -0700 (PDT) Received: (Authenticated sender: paul.kocialkowski@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 65C55FF807; Wed, 25 May 2022 18:59:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1653505151; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nhzws9Ge24y9zLTpn7LIOx4VeA6QmeditD5IQaS4nqo=; b=pyF+7sEnydvjq+ATeGBab8k+pqHn9/qP/UQOZGvHNp55k2E/NhLRcyfFFGFDXk8qtqz3Vv j7U6CEfmRRzfb4KTF0qTdVMqtzjyQrNc7zBPi56aSo/a9Y+wqywBTRYkBzoJealJJeElrf bi2lF907RpHO1VzWz6Wo6m2J/E8+FdrHaUjKhij8TyXTcYswfuzgK87NqnP7oTI5HMHI2U F/kWF5aH55dRbUrZThqnDsfSS84rd8UL3sbYKk9opxglaRr8BPoIoNKHgToujsGCjFAiJ1 kStpbENMRJu+hfgN0Bgd6g55eJuiFF+s+bPG/2StcHwppZ4cF8yn5K18O4N3sA== From: Paul Kocialkowski To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org Cc: Rob Herring , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Michael Turquette , Stephen Boyd , Frank Rowand , Maxime Ripard , Laurent Pinchart , Thomas Petazzoni , Paul Kocialkowski Subject: [PATCH v4 2/7] clk: sunxi-ng: v3s: Export MBUS and DRAM clocks to the public header Date: Wed, 25 May 2022 20:58:48 +0200 Message-Id: <20220525185853.695931-3-paul.kocialkowski@bootlin.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220525185853.695931-1-paul.kocialkowski@bootlin.com> References: <20220525185853.695931-1-paul.kocialkowski@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In order to declare a mbus node for the v3s, expose its associated clocks to the public header. Signed-off-by: Paul Kocialkowski Acked-by: Rob Herring --- drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 4 ---- include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 ++-- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h index 108eeeedcbf7..8ed4eff86ca1 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h +++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h @@ -39,14 +39,10 @@ /* The first bunch of module clocks are exported */ -#define CLK_DRAM 58 - /* All the DRAM gates are exported */ /* Some more module clocks are exported */ -#define CLK_MBUS 72 - /* And the GPU module clock is exported */ #define CLK_PLL_DDR1 74 diff --git a/include/dt-bindings/clock/sun8i-v3s-ccu.h b/include/dt-bindings/clock/sun8i-v3s-ccu.h index 014ac6123d17..4231f23bc53b 100644 --- a/include/dt-bindings/clock/sun8i-v3s-ccu.h +++ b/include/dt-bindings/clock/sun8i-v3s-ccu.h @@ -87,7 +87,7 @@ #define CLK_SPI0 55 #define CLK_USB_PHY0 56 #define CLK_USB_OHCI0 57 - +#define CLK_DRAM 58 #define CLK_DRAM_VE 59 #define CLK_DRAM_CSI 60 #define CLK_DRAM_EHCI 61 @@ -101,7 +101,7 @@ #define CLK_VE 69 #define CLK_AC_DIG 70 #define CLK_AVS 71 - +#define CLK_MBUS 72 #define CLK_MIPI_CSI 73 /* Clocks not available on V3s */ From patchwork Wed May 25 18:58:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Kocialkowski X-Patchwork-Id: 576060 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E669C433FE for ; Wed, 25 May 2022 18:59:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343901AbiEYS7V (ORCPT ); Wed, 25 May 2022 14:59:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343891AbiEYS7T (ORCPT ); Wed, 25 May 2022 14:59:19 -0400 Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD91534BA7; Wed, 25 May 2022 11:59:16 -0700 (PDT) Received: (Authenticated sender: paul.kocialkowski@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 2AB0FFF80D; Wed, 25 May 2022 18:59:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1653505154; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wcB8XbmtJH2/+Yi8wXbvB2+O44uFWVjrqjQQH76kP/4=; b=DmDlkXQjSxvvVNd8JoertHtW89K/bdAQoeDeKydt3eeRT+Q6F8oVtPtuJZGRQkxEy8n74X VPQ3YezduCPnIu6Jp/dIGu404IAt4ZPe3fUvI6vEt/ialC7oI2SFUkldkTh6QVEWWVNy8M J4htkv+Uy/R/ggC1p7j77l953mKrzyk25z8JaTtPNQngzPvoaGwwC78jxvCUKC9ZLLWu3n xHzdFDMccHu6Gocuqv6/YI79BP3cLCUoi4fpuno6jxGltFr4C76vmy1hgvFYd2p9CNIors jZAcKFgd7HY7pH6OqixghFbcoloZdm0BaIoUGhxXwSR4Ub740jNsh781WrHfSA== From: Paul Kocialkowski To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org Cc: Rob Herring , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Michael Turquette , Stephen Boyd , Frank Rowand , Maxime Ripard , Laurent Pinchart , Thomas Petazzoni , Paul Kocialkowski Subject: [PATCH v4 4/7] ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support Date: Wed, 25 May 2022 20:58:50 +0200 Message-Id: <20220525185853.695931-5-paul.kocialkowski@bootlin.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220525185853.695931-1-paul.kocialkowski@bootlin.com> References: <20220525185853.695931-1-paul.kocialkowski@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MIPI CSI-2 is supported on the V3s with an A31-based MIPI CSI-2 bridge controller. The controller uses a separate D-PHY, which is the same that is otherwise used for MIPI DSI, but used in Rx mode. On the V3s, the CSI0 controller is dedicated to MIPI CSI-2 as it does not have access to any parallel interface pins. Add all the necessary nodes (CSI0, MIPI CSI-2 bridge and D-PHY) to support the MIPI CSI-2 interface. Note that a fwnode graph link is created between CSI0 and MIPI CSI-2 even when no sensor is connected. This will result in a probe failure for the controller as long as no sensor is connected but this is fine since no other interface is available. The interconnects property is used to inherit the proper DMA offset. Signed-off-by: Paul Kocialkowski --- arch/arm/boot/dts/sun8i-v3s.dtsi | 71 ++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index a966b6a9acf5..a9405e011f3e 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -619,6 +619,77 @@ gic: interrupt-controller@1c81000 { interrupts = ; }; + csi0: camera@1cb0000 { + compatible = "allwinner,sun8i-v3s-csi"; + reg = <0x01cb0000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI1_SCLK>, + <&ccu CLK_DRAM_CSI>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_CSI>; + interconnects = <&mbus 5>; + interconnect-names = "dma-mem"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + csi0_in_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_out_csi0>; + }; + }; + }; + }; + + mipi_csi2: csi@1cb1000 { + compatible = "allwinner,sun8i-v3s-mipi-csi2", + "allwinner,sun6i-a31-mipi-csi2"; + reg = <0x01cb1000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI1_SCLK>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_CSI>; + status = "disabled"; + + phys = <&dphy>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_in: port@0 { + reg = <0>; + }; + + mipi_csi2_out: port@1 { + reg = <1>; + + mipi_csi2_out_csi0: endpoint { + remote-endpoint = <&csi0_in_mipi_csi2>; + }; + }; + }; + }; + + dphy: d-phy@1cb2000 { + compatible = "allwinner,sun6i-a31-mipi-dphy"; + reg = <0x01cb2000 0x1000>; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_MIPI_CSI>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_CSI>; + allwinner,direction = "rx"; + status = "disabled"; + #phy-cells = <0>; + }; + csi1: camera@1cb4000 { compatible = "allwinner,sun8i-v3s-csi"; reg = <0x01cb4000 0x3000>; From patchwork Wed May 25 18:58:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Kocialkowski X-Patchwork-Id: 576059 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5ED68C433EF for ; Wed, 25 May 2022 18:59:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343946AbiEYS70 (ORCPT ); Wed, 25 May 2022 14:59:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343907AbiEYS7W (ORCPT ); Wed, 25 May 2022 14:59:22 -0400 Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 005FD369F4; Wed, 25 May 2022 11:59:19 -0700 (PDT) Received: (Authenticated sender: paul.kocialkowski@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 6023AFF810; Wed, 25 May 2022 18:59:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1653505157; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=de4Hwuxb8Qceyqi37WOkBRIysyIGaR58lYVecTRLnzU=; b=Rd3+fZk6h0KEC5JsRek/A/ZNcVF67WeIXu/kG7bcdReTxRZKKpznjq5uugTTQ2fGhUTCvh 2zMenjvO34q7gec0HcRKG7OVxoMYyEhZmGhry9TeY95UgBcOc/hzq/aC/1VjV0RYLq1S+4 /cpHWGE4twPWvzk4tIRCGxp5a/fTFC0wPlBdYGLzP81N3RkSEbc5cOAMSg7+b6sg2G8Rb/ JUdeP33G692Kow7SR70dJbE/1lJ28v9oNXDUZxGr2ofofaKD4AVK1Gf0SDVrpee/sLc7I8 gLNT173jk7DnGkCae2SRNqLEcC6HAFH1QLpKLvPvMQHq/Gc4msMyl1x9y4EVtA== From: Paul Kocialkowski To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org Cc: Rob Herring , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Michael Turquette , Stephen Boyd , Frank Rowand , Maxime Ripard , Laurent Pinchart , Thomas Petazzoni , Paul Kocialkowski Subject: [PATCH v4 6/7] ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node Date: Wed, 25 May 2022 20:58:52 +0200 Message-Id: <20220525185853.695931-7-paul.kocialkowski@bootlin.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220525185853.695931-1-paul.kocialkowski@bootlin.com> References: <20220525185853.695931-1-paul.kocialkowski@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MIPI CSI-2 is supported on the A83T with a dedicated controller that covers both the protocol and D-PHY. It can be connected to the CSI interface as a V4L2 subdev through the fwnode graph. This is not done by default since connecting the bridge without a subdev attached to it will cause a failure on the CSI driver. Signed-off-by: Paul Kocialkowski --- arch/arm/boot/dts/sun8i-a83t.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 82fdb04122ca..ecf9f3b2c0c0 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -1064,6 +1064,32 @@ csi: camera@1cb0000 { status = "disabled"; }; + mipi_csi2: csi@1cb1000 { + compatible = "allwinner,sun8i-a83t-mipi-csi2"; + reg = <0x01cb1000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI_SCLK>, + <&ccu CLK_MIPI_CSI>, + <&ccu CLK_CSI_MISC>; + clock-names = "bus", "mod", "mipi", "misc"; + resets = <&ccu RST_BUS_CSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_in: port@0 { + reg = <0>; + }; + + mipi_csi2_out: port@1 { + reg = <1>; + }; + }; + }; + hdmi: hdmi@1ee0000 { compatible = "allwinner,sun8i-a83t-dw-hdmi"; reg = <0x01ee0000 0x10000>;