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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id k24-20020a05600c1c9800b003974027722csm2703693wms.47.2022.05.24.08.28.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 May 2022 08:28:03 -0700 (PDT) From: Alexandre Bailon To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, Michael Kao , Ben Tseng Subject: [PATCH v7 1/6] thermal: mediatek: Relocate driver to mediatek folder Date: Tue, 24 May 2022 17:25:48 +0200 Message-Id: <20220524152552.246193-2-abailon@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220524152552.246193-1-abailon@baylibre.com> References: <20220524152552.246193-1-abailon@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Michael Kao Add Mediatek proprietary folder to upstream more thermal zone and cooler drivers. Relocate the original thermal controller driver to it and rename as soc_temp.c to show its purpose more clearly. Signed-off-by: Michael Kao Signed-off-by: Ben Tseng Reviewed-by: Matthias Brugger Reviewed-by: AngeloGioacchino Del Regno --- drivers/thermal/Kconfig | 14 ++++------- drivers/thermal/Makefile | 2 +- drivers/thermal/mediatek/Kconfig | 23 +++++++++++++++++++ drivers/thermal/mediatek/Makefile | 1 + .../{mtk_thermal.c => mediatek/soc_temp.c} | 0 5 files changed, 29 insertions(+), 11 deletions(-) create mode 100644 drivers/thermal/mediatek/Kconfig create mode 100644 drivers/thermal/mediatek/Makefile rename drivers/thermal/{mtk_thermal.c => mediatek/soc_temp.c} (100%) diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index e37691e0bf20..8669d7278055 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -410,16 +410,10 @@ config DA9062_THERMAL zone. Compatible with the DA9062 and DA9061 PMICs. -config MTK_THERMAL - tristate "Temperature sensor driver for mediatek SoCs" - depends on ARCH_MEDIATEK || COMPILE_TEST - depends on HAS_IOMEM - depends on NVMEM || NVMEM=n - depends on RESET_CONTROLLER - default y - help - Enable this option if you want to have support for thermal management - controller present in Mediatek SoCs +menu "Mediatek thermal drivers" +depends on ARCH_MEDIATEK || COMPILE_TEST +source "drivers/thermal/mediatek/Kconfig" +endmenu config AMLOGIC_THERMAL tristate "Amlogic Thermal Support" diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index f0c36a1530d5..9ade39bdb525 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -55,7 +55,7 @@ obj-y += st/ obj-$(CONFIG_QCOM_TSENS) += qcom/ obj-y += tegra/ obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o -obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o +obj-$(CONFIG_MTK_THERMAL) += mediatek/ obj-$(CONFIG_GENERIC_ADC_THERMAL) += thermal-generic-adc.o obj-$(CONFIG_UNIPHIER_THERMAL) += uniphier_thermal.o obj-$(CONFIG_AMLOGIC_THERMAL) += amlogic_thermal.o diff --git a/drivers/thermal/mediatek/Kconfig b/drivers/thermal/mediatek/Kconfig new file mode 100644 index 000000000000..592c849b9fed --- /dev/null +++ b/drivers/thermal/mediatek/Kconfig @@ -0,0 +1,23 @@ +config MTK_THERMAL + tristate "MediaTek thermal drivers" + depends on THERMAL_OF + help + This is the option for MediaTek thermal software + solutions. Please enable corresponding options to + get temperature information from thermal sensors or + turn on throttle mechaisms for thermal mitigation. + +if MTK_THERMAL + +config MTK_SOC_THERMAL + tristate "Temperature sensor driver for MediaTek SoCs" + depends on HAS_IOMEM + depends on NVMEM + depends on RESET_CONTROLLER + help + Enable this option if you want to get SoC temperature + information for MediaTek platforms. This driver + configures thermal controllers to collect temperature + via AUXADC interface. + +endif diff --git a/drivers/thermal/mediatek/Makefile b/drivers/thermal/mediatek/Makefile new file mode 100644 index 000000000000..f75313ddce5e --- /dev/null +++ b/drivers/thermal/mediatek/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_MTK_SOC_THERMAL) += soc_temp.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mediatek/soc_temp.c similarity index 100% rename from drivers/thermal/mtk_thermal.c rename to drivers/thermal/mediatek/soc_temp.c From patchwork Tue May 24 15:25:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Bailon X-Patchwork-Id: 575903 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38B70C43219 for ; Tue, 24 May 2022 15:28:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232087AbiEXP2Y (ORCPT ); Tue, 24 May 2022 11:28:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238895AbiEXP2U (ORCPT ); Tue, 24 May 2022 11:28:20 -0400 Received: from mail-wr1-x433.google.com (mail-wr1-x433.google.com [IPv6:2a00:1450:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7329973543 for ; Tue, 24 May 2022 08:28:09 -0700 (PDT) Received: by mail-wr1-x433.google.com with SMTP id s28so26084372wrb.7 for ; Tue, 24 May 2022 08:28:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NiZa6xk9MkUsy0kBV1AgKPR3/ZpYc0vk8ORsY9H10YQ=; b=a6pZyNQk1oLcpgXHQFlCdF82gbQ+jAFaGJS7ahHCWYosCtQFt9hMXTJ1Y1qDUf/9Di jJY0wgDr3LkG6kFEc6po4aQzKwta9MPI84Zomtj68ImxOZIOx1NoPaZhOIpuwiRAYj/p U/QJWQsNu2oO29aO3IHh/5w5s8m3RCCEFDQ81lS2gA/H66m5TMlRrtAqMqE9T47Ecwdg IoNBtr7VS2SNV9cgaXbohLFvS3nYCyw/jjtlw8FRMsWWLLOAD9Kkd10U1Vqfh4kmaUSJ VgsIAR4B1+HNYkfKg/ECBpCBSeF5YkCySY0gp/CxvorOGEhjXP/6HUMCvbSAzLUDEqLK LHYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NiZa6xk9MkUsy0kBV1AgKPR3/ZpYc0vk8ORsY9H10YQ=; b=p7PIamRRofpxw0Tvi52GakkpU1W1IVhw34tyhZ9bJaMKSKDO0e3mOnkqEdHt2mE4gE WTGQrfuhSHYhUpsA/ni5ZvcyqTy2Re2lHGvWAQUNvUf1aZ4rssor8/QgFEtpLJFdKSda uQQ6xMiFctvvFSC/bxjxkOy2Xg1/hQ3uvrSYp/IVKV1t+Va0NcTvLxN6MC7/MUHs/dAw mg4M0txw4D6VVnzFzPNZHevXgVTSdFGoKTJ3/pIXCYTgaSel1yBPAQoheu+K22bJmlW+ 7UEqnQjMmot/qhpH769W1ftGMpe+jNf7D5RlwpISSHYLWg6hnwf9cRcQpth00mxlHwix l3Kw== X-Gm-Message-State: AOAM53265swHM6aRNrei86GbNeLyUMcUjxnbXrvnUGclZWsPR57wTU0H CW68k8ea84MeUb6HWWjGcv8WKQ== X-Google-Smtp-Source: ABdhPJzwznNhzRnRJe9SBGSdROAKleFzJajsmTMMwtYuH0j8wO3fYlV5oMaRMTCRqlmUmpct/YYseA== X-Received: by 2002:a5d:4e87:0:b0:20d:116f:2e2f with SMTP id e7-20020a5d4e87000000b0020d116f2e2fmr23581121wru.177.1653406088867; Tue, 24 May 2022 08:28:08 -0700 (PDT) Received: from xps-9300.baylibre (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id k24-20020a05600c1c9800b003974027722csm2703693wms.47.2022.05.24.08.28.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 May 2022 08:28:08 -0700 (PDT) From: Alexandre Bailon To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, Michael Kao , Ben Tseng , Alexandre Bailon Subject: [PATCH v7 4/6] thermal: mediatek: Add thermal zone settings for mt8195 Date: Tue, 24 May 2022 17:25:51 +0200 Message-Id: <20220524152552.246193-5-abailon@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220524152552.246193-1-abailon@baylibre.com> References: <20220524152552.246193-1-abailon@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Michael Kao Add thermal zone settings for mt8195 Signed-off-by: Michael Kao Signed-off-by: Ben Tseng Signed-off-by: Alexandre Bailon --- drivers/thermal/mediatek/soc_temp_lvts.c | 201 +++++++++++++++++++++-- 1 file changed, 187 insertions(+), 14 deletions(-) diff --git a/drivers/thermal/mediatek/soc_temp_lvts.c b/drivers/thermal/mediatek/soc_temp_lvts.c index 4b8c4c419f8e..c77c045d2599 100644 --- a/drivers/thermal/mediatek/soc_temp_lvts.c +++ b/drivers/thermal/mediatek/soc_temp_lvts.c @@ -49,6 +49,7 @@ #define CLOCK_26MHZ_CYCLE_NS (38) #define BUS_ACCESS_US (2) +#define GOLDEN_TEMP_MAX (62) #define FEATURE_DEVICE_AUTO_RCK (BIT(0)) #define FEATURE_CK26M_ACTIVE (BIT(1)) @@ -544,21 +545,10 @@ static int prepare_calibration_data(struct lvts_data *lvts_data) if (!cal_data->count_rc) return -ENOMEM; - if (ops->efuse_to_cal_data) + if (ops->efuse_to_cal_data && !cal_data->use_fake_efuse) ops->efuse_to_cal_data(lvts_data); - - cal_data->use_fake_efuse = 1; - if (cal_data->golden_temp != 0) { - cal_data->use_fake_efuse = 0; - } else { - for (i = 0; i < lvts_data->num_sensor; i++) { - if (cal_data->count_r[i] != 0 || - cal_data->count_rc[i] != 0) { - cal_data->use_fake_efuse = 0; - break; - } - } - } + if (cal_data->golden_temp == 0 || cal_data->golden_temp > GOLDEN_TEMP_MAX) + cal_data->use_fake_efuse = 1; if (cal_data->use_fake_efuse) { /* It means all efuse data are equal to 0 */ @@ -1233,11 +1223,194 @@ static const struct lvts_data mt8192_lvts_data = { }, }; +#define MT8195_NUM_LVTS (ARRAY_SIZE(mt8195_tc_settings)) + +enum mt8195_lvts_domain { + MT8195_AP_DOMAIN, + MT8195_MCU_DOMAIN, + MT8195_NUM_DOMAIN +}; + +enum mt8195_lvts_sensor_enum { + MT8195_TS1_0, + MT8195_TS1_1, + MT8195_TS2_0, + MT8195_TS2_1, + MT8195_TS3_0, + MT8195_TS3_1, + MT8195_TS3_2, + MT8195_TS3_3, + MT8195_TS4_0, + MT8195_TS4_1, + MT8195_TS5_0, + MT8195_TS5_1, + MT8195_TS6_0, + MT8195_TS6_1, + MT8195_TS6_2, + MT8195_TS7_0, + MT8195_TS7_1, + MT8195_NUM_TS +}; + +static void mt8195_efuse_to_cal_data(struct lvts_data *lvts_data) +{ + struct sensor_cal_data *cal_data = &lvts_data->cal_data; + + cal_data->golden_temp = GET_CAL_DATA_BITMASK(0, 31, 24); + cal_data->count_r[MT8195_TS1_0] = GET_CAL_DATA_BITMASK(1, 23, 0); + cal_data->count_r[MT8195_TS1_1] = (GET_CAL_DATA_BITMASK(2, 15, 0) << 8) + + GET_CAL_DATA_BITMASK(1, 31, 24); + cal_data->count_r[MT8195_TS2_0] = GET_CAL_DATA_BITMASK(3, 31, 8); + cal_data->count_r[MT8195_TS2_1] = GET_CAL_DATA_BITMASK(4, 23, 0); + cal_data->count_r[MT8195_TS3_0] = (GET_CAL_DATA_BITMASK(6, 7, 0) << 16) + + GET_CAL_DATA_BITMASK(5, 31, 16); + cal_data->count_r[MT8195_TS3_1] = GET_CAL_DATA_BITMASK(6, 31, 8); + cal_data->count_r[MT8195_TS3_2] = GET_CAL_DATA_BITMASK(7, 23, 0); + cal_data->count_r[MT8195_TS3_3] = (GET_CAL_DATA_BITMASK(8, 15, 0) << 8) + + GET_CAL_DATA_BITMASK(7, 31, 24); + cal_data->count_r[MT8195_TS4_0] = GET_CAL_DATA_BITMASK(9, 31, 8); + cal_data->count_r[MT8195_TS4_1] = GET_CAL_DATA_BITMASK(10, 23, 0); + cal_data->count_r[MT8195_TS5_0] = (GET_CAL_DATA_BITMASK(12, 7, 0) << 16) + + GET_CAL_DATA_BITMASK(11, 31, 16); + cal_data->count_r[MT8195_TS5_1] = GET_CAL_DATA_BITMASK(12, 31, 8); + cal_data->count_r[MT8195_TS6_0] = (GET_CAL_DATA_BITMASK(14, 15, 0) << 8) + + GET_CAL_DATA_BITMASK(13, 31, 24); + cal_data->count_r[MT8195_TS6_1] = (GET_CAL_DATA_BITMASK(15, 7, 0) << 16) + + GET_CAL_DATA_BITMASK(14, 31, 16); + cal_data->count_r[MT8195_TS6_2] = GET_CAL_DATA_BITMASK(15, 31, 8); + cal_data->count_r[MT8195_TS7_0] = (GET_CAL_DATA_BITMASK(17, 15, 0) << 8) + + GET_CAL_DATA_BITMASK(16, 31, 24); + cal_data->count_r[MT8195_TS7_1] = (GET_CAL_DATA_BITMASK(18, 7, 0) << 16) + + GET_CAL_DATA_BITMASK(17, 31, 16); + cal_data->count_rc[MT8195_TS1_0] = (GET_CAL_DATA_BITMASK(3, 7, 0) << 16) + + GET_CAL_DATA_BITMASK(2, 31, 16); + cal_data->count_rc[MT8195_TS2_0] = (GET_CAL_DATA_BITMASK(5, 15, 0) << 8) + + GET_CAL_DATA_BITMASK(4, 31, 24); + cal_data->count_rc[MT8195_TS3_0] = (GET_CAL_DATA_BITMASK(9, 7, 0) << 16) + + GET_CAL_DATA_BITMASK(8, 31, 16); + cal_data->count_rc[MT8195_TS4_0] = (GET_CAL_DATA_BITMASK(11, 15, 0) << 8) + + GET_CAL_DATA_BITMASK(10, 31, 24); + cal_data->count_rc[MT8195_TS5_0] = GET_CAL_DATA_BITMASK(13, 23, 0); + cal_data->count_rc[MT8195_TS6_0] = GET_CAL_DATA_BITMASK(16, 23, 0); + cal_data->count_rc[MT8195_TS7_0] = GET_CAL_DATA_BITMASK(18, 31, 8); +} + +static const struct tc_settings mt8195_tc_settings[] = { + [0] = { + .domain_index = MT8195_MCU_DOMAIN, + .addr_offset = 0x0, + .num_sensor = 2, + .sensor_map = {MT8195_TS1_0, MT8195_TS1_1}, + .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT1, + .hw_reboot_trip_point = 117000, + .irq_bit = BIT(3), + }, + [1] = { + .domain_index = MT8195_MCU_DOMAIN, + .addr_offset = 0x100, + .num_sensor = 2, + .sensor_map = {MT8195_TS2_0, MT8195_TS2_1}, + .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT0, + .hw_reboot_trip_point = 117000, + .irq_bit = BIT(4), + }, + [2] = { + .domain_index = MT8195_MCU_DOMAIN, + .addr_offset = 0x200, + .num_sensor = 4, + .sensor_map = {MT8195_TS3_0, MT8195_TS3_1, MT8195_TS3_2, MT8195_TS3_3}, + .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT0, + .hw_reboot_trip_point = 117000, + .irq_bit = BIT(5), + }, + [3] = { + .domain_index = MT8195_AP_DOMAIN, + .addr_offset = 0x0, + .num_sensor = 2, + .sensor_map = {MT8195_TS4_0, MT8195_TS4_1}, + .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT0, + .hw_reboot_trip_point = 117000, + .irq_bit = BIT(3), + }, + [4] = { + .domain_index = MT8195_AP_DOMAIN, + .addr_offset = 0x100, + .num_sensor = 2, + .sensor_map = {MT8195_TS5_0, MT8195_TS5_1}, + .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT1, + .hw_reboot_trip_point = 117000, + .irq_bit = BIT(4), + }, + [5] = { + .domain_index = MT8195_AP_DOMAIN, + .addr_offset = 0x200, + .num_sensor = 3, + .sensor_map = {MT8195_TS6_0, MT8195_TS6_1, MT8195_TS6_2}, + .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT1, + .hw_reboot_trip_point = 117000, + .irq_bit = BIT(5), + }, + [6] = { + .domain_index = MT8195_AP_DOMAIN, + .addr_offset = 0x300, + .num_sensor = 2, + .sensor_map = {MT8195_TS7_0, MT8195_TS7_1}, + .tc_speed = SET_TC_SPEED_IN_US(118, 118, 118, 118), + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT0, + .hw_reboot_trip_point = 117000, + .irq_bit = BIT(6), + } +}; + +static const struct lvts_data mt8195_lvts_data = { + .num_domain = MT8195_NUM_DOMAIN, + .num_tc = MT8195_NUM_LVTS, + .tc = mt8195_tc_settings, + .num_sensor = MT8195_NUM_TS, + .ops = { + .efuse_to_cal_data = mt8195_efuse_to_cal_data, + .device_enable_and_init = device_enable_and_init_v4, + .device_enable_auto_rck = device_enable_auto_rck_v4, + .device_read_count_rc_n = device_read_count_rc_n_v4, + .set_cal_data = set_calibration_data_v4, + .init_controller = init_controller_v4, + }, + .feature_bitmap = FEATURE_DEVICE_AUTO_RCK, + .num_efuse_addr = 22, + .num_efuse_block = 2, + .cal_data = { + .default_golden_temp = 50, + .default_count_r = 35000, + .default_count_rc = 2750, + }, + .coeff = { + .a = -250460, + .b = 250460, + }, +}; + static const struct of_device_id lvts_of_match[] = { { .compatible = "mediatek,mt8192-lvts", .data = (void *)&mt8192_lvts_data, }, + { + .compatible = "mediatek,mt8195-lvts", + .data = (void *)&mt8195_lvts_data, + }, { }, }; From patchwork Tue May 24 15:25:53 2022 Content-Type: text/plain; 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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id k24-20020a05600c1c9800b003974027722csm2703693wms.47.2022.05.24.08.28.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 May 2022 08:28:11 -0700 (PDT) From: Alexandre Bailon To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, Tinghan Shen , Ben Tseng , Alexandre Bailon Subject: [PATCH v7 6/6] arm64: dts: mt8195: Add thermal zone Date: Tue, 24 May 2022 17:25:53 +0200 Message-Id: <20220524152552.246193-7-abailon@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220524152552.246193-1-abailon@baylibre.com> References: <20220524152552.246193-1-abailon@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Tinghan Shen This adds the thermal zone for the mt8195. Signed-off-by: Tinghan Shen Signed-off-by: Ben Tseng Signed-off-by: Alexandre Bailon --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 104 +++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 51443e83d906..8421cf35ae03 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include / { @@ -812,6 +813,21 @@ spi0: spi@1100a000 { status = "disabled"; }; + lvts: lvts@1100b000 { + compatible = "mediatek,mt8195-lvts"; + #thermal-sensor-cells = <1>; + reg = <0 0x1100b000 0 0x1000>, + <0 0x11278000 0 0x1000>; + interrupts = , + ; + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; + resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>, + <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; + + nvmem-cells = <&lvts_e_data1 &lvts_e_data2>; + nvmem-cell-names = "e_data1","e_data2"; + }; + spi1: spi@11010000 { compatible = "mediatek,mt8195-spi", "mediatek,mt6765-spi"; @@ -1616,4 +1632,92 @@ vencsys_core1: clock-controller@1b000000 { #clock-cells = <1>; }; }; + + thermal_zones: thermal-zones { + cpu-big1-thermal { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 0>; + }; + cpu-big2-thermal { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 1>; + }; + cpu-big3-thermal { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 2>; + }; + cpu-big4-thermal { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 3>; + }; + cpu-little1-thermal { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 4>; + }; + cpu-little2-thermal { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 5>; + }; + cpu-little3-thermal { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 6>; + }; + cpu-little4-thermal { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 7>; + }; + vpu1-thermal { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 8>; + }; + vpu2-thermal { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 9>; + }; + gpu1-thermal { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 10>; + }; + gpu2-thermal { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 11>; + }; + vdec-thermal { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 12>; + }; + img-thermal { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 13>; + }; + infra-thermal { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 14>; + }; + cam1-thermal { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 15>; + }; + cam2-thermal { + polling-delay = <0>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&lvts 16>; + }; + }; };