From patchwork Mon May 23 10:47:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Ranquet X-Patchwork-Id: 575567 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25FABC433FE for ; Mon, 23 May 2022 10:50:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234378AbiEWKu0 (ORCPT ); Mon, 23 May 2022 06:50:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34568 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234362AbiEWKuV (ORCPT ); Mon, 23 May 2022 06:50:21 -0400 Received: from mail-wm1-x344.google.com (mail-wm1-x344.google.com [IPv6:2a00:1450:4864:20::344]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD1CC4CD62 for ; Mon, 23 May 2022 03:50:19 -0700 (PDT) Received: by mail-wm1-x344.google.com with SMTP id i82-20020a1c3b55000000b00397391910d5so5094767wma.1 for ; Mon, 23 May 2022 03:50:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RBdwv8C2zWSCXm9kFqdZLTYTeRupN3jSjblct2gox8s=; b=Z/xyqPorLXxjtX45nJY9HoVzJk17XbNfLYrKQzUC5oUtkKMtSoV+kWJ/W9h2UwUdlN 1izRYQ+g5TLX3hghia4MPgYalf8vdyabNOS2DaGlsAhoEGt/s+/KnelQ0vZbZtihbBMg 21Pyw395K/H6hYe1NjG4mAI/mc+ABytCuV7klYgDvq9vZJ7hsPVtmwjWKYUbF/bp/EcC Oilliy3/kq69ohuRdHDHt1sN0WqllfmeBK0PA3bmOt33PYByl5DZkyGxt3aG8JeVrdma MXLeIGVJyxZJTBpjD3ztKpUSnkvsiwIvClmunyObwRYCXJLItn7H8y/fT/NKL+YLfjaE ppkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RBdwv8C2zWSCXm9kFqdZLTYTeRupN3jSjblct2gox8s=; b=MDdup8jP/sH+kvmTsDIfboZ5lBBKngv2vJoIKkxxGM+ONk9qFhJ62OqnAOtIkBLJYE 8gyU41Ds3pZzN/c7OKJotBG7G29D78DI5S4/tQRzZbMjWmkHhT+QLZnMY+u3j5E94eOw cFvRyupJuKevrb5utENoQn2e7K9WkqmWwfpgz6vNmljEaNcuqBc/0jufhHDCEfm2zSNJ XZIDX7PxFOuJJ3wQsFLk2QD/k/57zRgh4YzPMW+4Ui8wI80vsVWQmKo91gA2bJ/KJDl9 79nbytByg2uK7h102/WQ6Xbby8XTyN8Iqw6UG5QHB8x8fI1h/giNmncVraTqjNWBGGG0 B2Uw== X-Gm-Message-State: AOAM530D3Soucx5cFGNcFjE1D21HUcExkjWw5cRt/9qp8ORSKZyEbeZD hcNH7feqJEwmduEkcQNhwvNDhQ== X-Google-Smtp-Source: ABdhPJxU86O9OrfPSwDpzF5vc+DzPzD1gUymNmku2eiSYHqSUNEzJviyarRmUCu72kW//QWtrovSTg== X-Received: by 2002:a05:600c:42d3:b0:397:47ae:188c with SMTP id j19-20020a05600c42d300b0039747ae188cmr6376412wme.150.1653303018361; Mon, 23 May 2022 03:50:18 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-6141-9d1b-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.50.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:50:18 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: Markus Schneider-Pargmann , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 02/21] dt-bindings: mediatek,dp: Add Display Port binding Date: Mon, 23 May 2022 12:47:35 +0200 Message-Id: <20220523104758.29531-3-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Markus Schneider-Pargmann This controller is present on several mediatek hardware. Currently mt8195 and mt8395 have this controller without a functional difference, so only one compatible field is added. The controller can have two forms, as a normal display port and as an embedded display port. Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet --- .../display/mediatek/mediatek,dp.yaml | 99 +++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml new file mode 100644 index 000000000000..36ae0a6df299 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Display Port Controller + +maintainers: + - CK Hu + - Jitao shi + +description: | + Device tree bindings for the MediaTek (embedded) Display Port controller + present on some MediaTek SoCs. + +properties: + compatible: + enum: + - mediatek,mt8195-dp-tx + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: faxi clock + + clock-names: + items: + - const: faxi + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input endpoint of the controller, usually dp_intf + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Output endpoint of the controller + + max-lanes: + maxItems: 1 + description: maximum number of lanes supported by the hardware + + max-linkrate: + maxItems: 1 + description: maximum link rate supported by the hardware + +required: + - compatible + - reg + - interrupts + - ports + - max-lanes + - max-linkrate + +additionalProperties: false + +examples: + - | + #include + #include + edp_tx: edp_tx@1c500000 { + compatible = "mediatek,mt8195-dp-tx"; + reg = <0 0x1c500000 0 0x8000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&edp_pin>; + max-lanes = /bits/ 8 <4>; + max-linkrate = /bits/ 8 <0x1e>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + edp_in: endpoint { + remote-endpoint = <&dp_intf0_out>; + }; + }; + port@1 { + reg = <1>; + edp_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; From patchwork Mon May 23 10:47:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Ranquet X-Patchwork-Id: 575566 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1785C433EF for ; Mon, 23 May 2022 10:50:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234405AbiEWKut (ORCPT ); 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[2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.50.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:50:30 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: Markus Schneider-Pargmann , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 04/21] drm/edid: Add cea_sad helpers for freq/length Date: Mon, 23 May 2022 12:47:37 +0200 Message-Id: <20220523104758.29531-5-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds two helper functions that extract the frequency and word length from a struct cea_sad. For these helper functions new defines are added that help translate the 'freq' and 'byte2' fields into real numbers. Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet --- drivers/gpu/drm/drm_edid.c | 74 ++++++++++++++++++++++++++++++++++++++ include/drm/drm_edid.h | 14 ++++++++ 2 files changed, 88 insertions(+) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 561f53831e29..61ef1b1c972c 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -4758,6 +4758,80 @@ int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) } EXPORT_SYMBOL(drm_edid_to_speaker_allocation); +/** + * drm_cea_sad_get_sample_rate - Extract the sample rate from cea_sad + * @sad: Pointer to the cea_sad struct + * + * Extracts the cea_sad frequency field and returns the sample rate in Hz. + * + * Return: Sample rate in Hz or a negative errno if parsing failed. + */ +int drm_cea_sad_get_sample_rate(const struct cea_sad *sad) +{ + switch (sad->freq) { + case DRM_CEA_SAD_FREQ_32KHZ: + return 32000; + case DRM_CEA_SAD_FREQ_44KHZ: + return 44100; + case DRM_CEA_SAD_FREQ_48KHZ: + return 48000; + case DRM_CEA_SAD_FREQ_88KHZ: + return 88200; + case DRM_CEA_SAD_FREQ_96KHZ: + return 96000; + case DRM_CEA_SAD_FREQ_176KHZ: + return 176400; + case DRM_CEA_SAD_FREQ_192KHZ: + return 192000; + default: + return -EINVAL; + } +} +EXPORT_SYMBOL(drm_cea_sad_get_sample_rate); + +static bool drm_cea_sad_is_uncompressed(const struct cea_sad *sad) +{ + switch (sad->format) { + case HDMI_AUDIO_CODING_TYPE_STREAM: + case HDMI_AUDIO_CODING_TYPE_PCM: + return true; + default: + return false; + } +} + +/** + * drm_cea_sad_get_uncompressed_word_length - Extract word length + * @sad: Pointer to the cea_sad struct + * + * Extracts the cea_sad byte2 field and returns the word length for an + * uncompressed stream. + * + * Note: This function may only be called for uncompressed audio. + * + * Return: Word length in bits or a negative errno if parsing failed. + */ +int drm_cea_sad_get_uncompressed_word_length(const struct cea_sad *sad) +{ + if (!drm_cea_sad_is_uncompressed(sad)) { + DRM_WARN("Unable to get the uncompressed word length for a compressed format: %u\n", + sad->format); + return -EINVAL; + } + + switch (sad->byte2) { + case DRM_CEA_SAD_UNCOMPRESSED_WORD_16BIT: + return 16; + case DRM_CEA_SAD_UNCOMPRESSED_WORD_20BIT: + return 20; + case DRM_CEA_SAD_UNCOMPRESSED_WORD_24BIT: + return 24; + default: + return -EINVAL; + } +} +EXPORT_SYMBOL(drm_cea_sad_get_uncompressed_word_length); + /** * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay * @connector: connector associated with the HDMI/DP sink diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index 37c420423625..7a939cb95b38 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h @@ -373,6 +373,18 @@ struct cea_sad { u8 byte2; }; +#define DRM_CEA_SAD_FREQ_32KHZ BIT(0) +#define DRM_CEA_SAD_FREQ_44KHZ BIT(1) +#define DRM_CEA_SAD_FREQ_48KHZ BIT(2) +#define DRM_CEA_SAD_FREQ_88KHZ BIT(3) +#define DRM_CEA_SAD_FREQ_96KHZ BIT(4) +#define DRM_CEA_SAD_FREQ_176KHZ BIT(5) +#define DRM_CEA_SAD_FREQ_192KHZ BIT(6) + +#define DRM_CEA_SAD_UNCOMPRESSED_WORD_16BIT BIT(0) +#define DRM_CEA_SAD_UNCOMPRESSED_WORD_20BIT BIT(1) +#define DRM_CEA_SAD_UNCOMPRESSED_WORD_24BIT BIT(2) + struct drm_encoder; struct drm_connector; struct drm_connector_state; @@ -380,6 +392,8 @@ struct drm_display_mode; int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads); int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb); +int drm_cea_sad_get_sample_rate(const struct cea_sad *sad); +int drm_cea_sad_get_uncompressed_word_length(const struct cea_sad *sad); int drm_av_sync_delay(struct drm_connector *connector, const struct drm_display_mode *mode); From patchwork Mon May 23 10:47:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Ranquet X-Patchwork-Id: 575565 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 516AAC43217 for ; Mon, 23 May 2022 10:50:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234383AbiEWKuw (ORCPT ); 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[2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.50.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:50:43 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: AngeloGioacchino Del Regno , Rex-BC Chen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 06/21] drm/mediatek: dpi: move dpi limits to SoC config Date: Mon, 23 May 2022 12:47:39 +0200 Message-Id: <20220523104758.29531-7-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add flexibility by moving the dpi limits to the SoC specific config Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen --- drivers/gpu/drm/mediatek/mtk_dpi.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 4554e2de1430..4746eb342567 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -125,6 +125,7 @@ struct mtk_dpi_conf { bool edge_sel_en; const u32 *output_fmts; u32 num_output_fmts; + const struct mtk_dpi_yc_limit *limit; }; static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask) @@ -235,9 +236,10 @@ static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height) mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); } -static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi, - struct mtk_dpi_yc_limit *limit) +static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) { + const struct mtk_dpi_yc_limit *limit = dpi->conf->limit; + mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT, Y_LIMINT_BOT_MASK); mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP, @@ -449,7 +451,6 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, struct drm_display_mode *mode) { - struct mtk_dpi_yc_limit limit; struct mtk_dpi_polarities dpi_pol; struct mtk_dpi_sync_param hsync; struct mtk_dpi_sync_param vsync_lodd = { 0 }; @@ -484,11 +485,6 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", pll_rate, vm.pixelclock); - limit.c_bottom = 0x0010; - limit.c_top = 0x0FE0; - limit.y_bottom = 0x0010; - limit.y_top = 0x0FE0; - dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING; dpi_pol.de_pol = MTK_DPI_POLARITY_RISING; dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? @@ -536,7 +532,7 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, else mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive); - mtk_dpi_config_channel_limit(dpi, &limit); + mtk_dpi_config_channel_limit(dpi); mtk_dpi_config_bit_num(dpi, dpi->bit_num); mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); mtk_dpi_config_yc_map(dpi, dpi->yc_map); @@ -790,12 +786,20 @@ static const u32 mt8183_output_fmts[] = { MEDIA_BUS_FMT_RGB888_2X12_BE, }; +static const struct mtk_dpi_yc_limit mtk_dpi_limit = { + .c_bottom = 0x0010, + .c_top = 0x0FE0, + .y_bottom = 0x0010, + .y_top = 0x0FE0, +}; + static const struct mtk_dpi_conf mt8173_conf = { .cal_factor = mt8173_calculate_factor, .reg_h_fre_con = 0xe0, .max_clock_khz = 300000, .output_fmts = mt8173_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), + .limit = &mtk_dpi_limit, }; static const struct mtk_dpi_conf mt2701_conf = { @@ -805,6 +809,7 @@ static const struct mtk_dpi_conf mt2701_conf = { .max_clock_khz = 150000, .output_fmts = mt8173_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), + .limit = &mtk_dpi_limit, }; static const struct mtk_dpi_conf mt8183_conf = { @@ -813,6 +818,7 @@ static const struct mtk_dpi_conf mt8183_conf = { .max_clock_khz = 100000, .output_fmts = mt8183_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), + .limit = &mtk_dpi_limit, }; static const struct mtk_dpi_conf mt8192_conf = { @@ -821,6 +827,7 @@ static const struct mtk_dpi_conf mt8192_conf = { .max_clock_khz = 150000, .output_fmts = mt8173_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), + .limit = &mtk_dpi_limit, }; static int mtk_dpi_probe(struct platform_device *pdev) From patchwork Mon May 23 10:47:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Ranquet X-Patchwork-Id: 575564 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E94C4C433FE for ; Mon, 23 May 2022 10:51:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234401AbiEWKvi (ORCPT ); Mon, 23 May 2022 06:51:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36216 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234426AbiEWKvB (ORCPT ); Mon, 23 May 2022 06:51:01 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0114C4D626 for ; Mon, 23 May 2022 03:50:56 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id t13so1581722wrg.9 for ; Mon, 23 May 2022 03:50:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9jP9dq0eqNju1JFK7hi0cYxaapGwnNAhPGRZeD+o+7w=; b=M1PApx6JO0ucI5ZRRlGl3kXqjmvvORDiFf9UkR8kuE9PiPMj6LBUsOXOQkYghTqWM6 Y42sddN4qCdj6Cc7brfNShxohE/SwqyqfOLeLv/zN7i4CeqEDu0/IrVGnghkWEatMuph 1lwMHmTxyavp/pTF6hk5EjgcSgP+Kz3zP5jgkEVbTLboSIVw++xZCi7NTOBqv5+bKIVv QL9/y/wZd9lzwop/5tkjaPlvmmFqgs/8W0qu77UmDJvIS55j3zJx+pgxdFe8GwqCcJQo 60IvuR05z6saM5V8DM4eI/hgCPbuj+ZMwVIj1R/1f7dFfIaLu+BjfsfnN+yXwBDedu2x lvXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9jP9dq0eqNju1JFK7hi0cYxaapGwnNAhPGRZeD+o+7w=; b=sw8sQhAIF10OcK+9KGCo1N+aOUofceVqMn6kpKEvfPJXqd5qBELu5XQS34F7iKh/Bw /SVnwqyLXQO69yhcKPxHTVgCfC/cORhJjf4MT0K3WO20Dqv7zAfa7ST15y+867A2FN/h cAB/rElsz4UOE5uqf6ZTzwmfokcbf29tqwtGINDYGzTxGjR3qug8cCXotC0aTgOhN0X2 WXZVIs3pTCkxW3wQRLy1Ge90xKsvedT3r484uoJu5ALD1sgAOoCnHz90EkE6NhAGva6L qqdf5Dbi1PsATM7aYbbquht5WM9F1iLyLCgZpzM633mPOoB7yxh6iE1X/Hksc1CRijKN 1UHw== X-Gm-Message-State: AOAM533QgylD4mZaTRSIdBvLQx2Ny5ESi8t3qpIs1ec1rX8sOJJD0Ogw MrOMT+sNsEhhwOQqYbanmFzy1g== X-Google-Smtp-Source: ABdhPJzFVsn52LLkc6F5P2MSaLKmhQPgvOfhCMFcPHG2HJ9CtCk4fi83gaSnITOg3ufjkMvUe7umaQ== X-Received: by 2002:a5d:6042:0:b0:20e:65c0:f69b with SMTP id j2-20020a5d6042000000b0020e65c0f69bmr18712524wrt.524.1653303056451; Mon, 23 May 2022 03:50:56 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-6141-9d1b-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.50.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:50:56 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: AngeloGioacchino Del Regno , Rex-BC Chen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 08/21] drm/mediatek: dpi: implement a swap_input toggle in SoC config Date: Mon, 23 May 2022 12:47:41 +0200 Message-Id: <20220523104758.29531-9-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Adds a bit of flexibility to support SoCs without swap_input support Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen --- drivers/gpu/drm/mediatek/mtk_dpi.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 545a1337cc89..454f8563efae 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -126,6 +126,7 @@ struct mtk_dpi_conf { const u32 *output_fmts; u32 num_output_fmts; bool is_ck_de_pol; + bool swap_input_support; const struct mtk_dpi_yc_limit *limit; }; @@ -378,18 +379,21 @@ static void mtk_dpi_config_color_format(struct mtk_dpi *dpi, (format == MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, true); - mtk_dpi_config_swap_input(dpi, false); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR); } else if ((format == MTK_DPI_COLOR_FORMAT_YCBCR_422) || (format == MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) { mtk_dpi_config_yuv422_enable(dpi, true); mtk_dpi_config_csc_enable(dpi, true); - mtk_dpi_config_swap_input(dpi, true); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, true); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); } else { mtk_dpi_config_yuv422_enable(dpi, false); mtk_dpi_config_csc_enable(dpi, false); - mtk_dpi_config_swap_input(dpi, false); + if (dpi->conf->swap_input_support) + mtk_dpi_config_swap_input(dpi, false); mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB); } } @@ -808,6 +812,7 @@ static const struct mtk_dpi_conf mt8173_conf = { .output_fmts = mt8173_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol = true, + .swap_input_support = true, .limit = &mtk_dpi_limit, }; @@ -819,6 +824,7 @@ static const struct mtk_dpi_conf mt2701_conf = { .output_fmts = mt8173_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol = true, + .swap_input_support = true, .limit = &mtk_dpi_limit, }; @@ -829,6 +835,7 @@ static const struct mtk_dpi_conf mt8183_conf = { .output_fmts = mt8183_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8183_output_fmts), .is_ck_de_pol = true, + .swap_input_support = true, .limit = &mtk_dpi_limit, }; @@ -839,6 +846,7 @@ static const struct mtk_dpi_conf mt8192_conf = { .output_fmts = mt8173_output_fmts, .num_output_fmts = ARRAY_SIZE(mt8173_output_fmts), .is_ck_de_pol = true, + .swap_input_support = true, .limit = &mtk_dpi_limit, }; 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[2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.51.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:51:09 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: AngeloGioacchino Del Regno , Rex-BC Chen , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 10/21] drm/mediatek: dpi: move hvsize_mask to SoC config Date: Mon, 23 May 2022 12:47:43 +0200 Message-Id: <20220523104758.29531-11-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add flexibility by moving the hvsize mask to SoC specific config Signed-off-by: Guillaume Ranquet Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rex-BC Chen Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index bf098f36a466..6eeda222a973 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -129,6 +129,8 @@ struct mtk_dpi_conf { bool swap_input_support; /* Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH (no shift) */ u32 dimension_mask; + /* HSIZE and VSIZE mask (no shift) */ + u32 hvsize_mask; const struct mtk_dpi_yc_limit *limit; }; @@ -243,8 +245,10 @@ static void mtk_dpi_config_interface(struct mtk_dpi *dpi, bool inter) static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height) { - mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, HSIZE_MASK); - mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK); + mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, + dpi->conf->hvsize_mask << HSIZE); + mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, + dpi->conf->hvsize_mask << VSIZE); } static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) @@ -816,6 +820,7 @@ static const struct mtk_dpi_conf mt8173_conf = { .is_ck_de_pol = true, .swap_input_support = true, .dimension_mask = HPW_MASK, + .hvsize_mask = HSIZE_MASK, .limit = &mtk_dpi_limit, }; @@ -829,6 +834,7 @@ static const struct mtk_dpi_conf mt2701_conf = { .is_ck_de_pol = true, .swap_input_support = true, .dimension_mask = HPW_MASK, + .hvsize_mask = HSIZE_MASK, .limit = &mtk_dpi_limit, }; @@ -841,6 +847,7 @@ static const struct mtk_dpi_conf mt8183_conf = { .is_ck_de_pol = true, .swap_input_support = true, .dimension_mask = HPW_MASK, + .hvsize_mask = HSIZE_MASK, .limit = &mtk_dpi_limit, }; @@ -853,6 +860,7 @@ static const struct mtk_dpi_conf mt8192_conf = { .is_ck_de_pol = true, .swap_input_support = true, .dimension_mask = HPW_MASK, + .hvsize_mask = HSIZE_MASK, .limit = &mtk_dpi_limit, }; From patchwork Mon May 23 10:47:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Ranquet X-Patchwork-Id: 575562 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69374C433EF for ; Mon, 23 May 2022 10:52:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234467AbiEWKv4 (ORCPT ); Mon, 23 May 2022 06:51:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234546AbiEWKvU (ORCPT ); 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[2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.51.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:51:15 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: Rex-BC Chen , AngeloGioacchino Del Regno , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 11/21] drm/mediatek: dpi: move swap_shift to SoC config Date: Mon, 23 May 2022 12:47:44 +0200 Message-Id: <20220523104758.29531-12-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add flexibility by moving the swap shift value to SoC specific config Signed-off-by: Guillaume Ranquet Reviewed-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 6eeda222a973..6d4d8c6ec47d 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -131,6 +131,7 @@ struct mtk_dpi_conf { u32 dimension_mask; /* HSIZE and VSIZE mask (no shift) */ u32 hvsize_mask; + u32 channel_swap_shift; const struct mtk_dpi_yc_limit *limit; }; @@ -349,7 +350,8 @@ static void mtk_dpi_config_channel_swap(struct mtk_dpi *dpi, break; } - mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << CH_SWAP, CH_SWAP_MASK); + mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << dpi->conf->channel_swap_shift, + CH_SWAP_MASK); } static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable) @@ -821,6 +823,7 @@ static const struct mtk_dpi_conf mt8173_conf = { .swap_input_support = true, .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, + .channel_swap_shift = CH_SWAP, .limit = &mtk_dpi_limit, }; @@ -835,6 +838,7 @@ static const struct mtk_dpi_conf mt2701_conf = { .swap_input_support = true, .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, + .channel_swap_shift = CH_SWAP, .limit = &mtk_dpi_limit, }; @@ -848,6 +852,7 @@ static const struct mtk_dpi_conf mt8183_conf = { .swap_input_support = true, .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, + .channel_swap_shift = CH_SWAP, .limit = &mtk_dpi_limit, }; @@ -861,6 +866,7 @@ static const struct mtk_dpi_conf mt8192_conf = { .swap_input_support = true, .dimension_mask = HPW_MASK, .hvsize_mask = HSIZE_MASK, + .channel_swap_shift = CH_SWAP, .limit = &mtk_dpi_limit, }; From patchwork Mon May 23 10:47:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Ranquet X-Patchwork-Id: 575561 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58D98C433FE for ; Mon, 23 May 2022 10:52:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234482AbiEWKwC (ORCPT ); Mon, 23 May 2022 06:52:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38592 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234643AbiEWKvk (ORCPT ); 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[2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.51.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:51:36 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: Markus Schneider-Pargmann , dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 14/21] drm/mediatek: dpi: Add dpintf support Date: Mon, 23 May 2022 12:47:47 +0200 Message-Id: <20220523104758.29531-15-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org dpintf is the displayport interface hardware unit. This unit is similar to dpi and can reuse most of the code. This patch adds support for mt8195-dpintf to this dpi driver. Main differences are: - Some features/functional components are not available for dpintf which are now excluded from code execution once is_dpintf is set - dpintf can and needs to choose between different clockdividers based on the clockspeed. This is done by choosing a different clock parent. - There are two additional clocks that need to be managed. These are only set for dpintf and will be set to NULL if not supplied. The clk_* calls handle these as normal clocks then. - Some register contents differ slightly between the two components. To work around this I added register bits/masks with a DPINTF_ prefix and use them where different. Based on a separate driver for dpintf created by Jason-JH.Lin . Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Guillaume Ranquet --- drivers/gpu/drm/mediatek/mtk_dpi.c | 126 +++++++++++++++++--- drivers/gpu/drm/mediatek/mtk_dpi_regs.h | 35 ++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +- include/linux/soc/mediatek/mtk-mmsys.h | 4 +- 6 files changed, 159 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index eb969c5c5c2e..763bfb700135 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -71,6 +71,7 @@ struct mtk_dpi { void __iomem *regs; struct device *dev; struct clk *engine_clk; + struct clk *dpi_ck_cg; struct clk *pixel_clk; struct clk *tvd_clk; int irq; @@ -126,6 +127,7 @@ struct mtk_dpi_conf { const u32 *output_fmts; u32 num_output_fmts; bool is_ck_de_pol; + bool is_dpintf; bool swap_input_support; /* Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PORCH (no shift) */ u32 dimension_mask; @@ -438,6 +440,8 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi) mtk_dpi_disable(dpi); clk_disable_unprepare(dpi->pixel_clk); clk_disable_unprepare(dpi->engine_clk); + clk_disable_unprepare(dpi->dpi_ck_cg); + clk_disable_unprepare(dpi->tvd_clk); } static int mtk_dpi_power_on(struct mtk_dpi *dpi) @@ -447,12 +451,24 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (++dpi->refcount != 1) return 0; + ret = clk_prepare_enable(dpi->tvd_clk); + if (ret) { + dev_err(dpi->dev, "Failed to enable tvd pll: %d\n", ret); + goto err_pixel; + } + ret = clk_prepare_enable(dpi->engine_clk); if (ret) { dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret); goto err_refcount; } + ret = clk_prepare_enable(dpi->dpi_ck_cg); + if (ret) { + dev_err(dpi->dev, "Failed to enable dpi_ck_cg clock: %d\n", ret); + goto err_ck_cg; + } + ret = clk_prepare_enable(dpi->pixel_clk); if (ret) { dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret); @@ -466,6 +482,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) return 0; err_pixel: + clk_disable_unprepare(dpi->dpi_ck_cg); +err_ck_cg: clk_disable_unprepare(dpi->engine_clk); err_refcount: dpi->refcount--; @@ -498,11 +516,11 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, vm.pixelclock = pll_rate / factor; if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) || - (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) + (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE)) { clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2); - else + } else { clk_set_rate(dpi->pixel_clk, vm.pixelclock); - + } vm.pixelclock = clk_get_rate(dpi->pixel_clk); @@ -515,9 +533,15 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; dpi_pol.vsync_pol = vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ? MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; - hsync.sync_width = vm.hsync_len; - hsync.back_porch = vm.hback_porch; - hsync.front_porch = vm.hfront_porch; + if (dpi->conf->is_dpintf) { + hsync.sync_width = vm.hsync_len / 4; + hsync.back_porch = vm.hback_porch / 4; + hsync.front_porch = vm.hfront_porch / 4; + } else { + hsync.sync_width = vm.hsync_len; + hsync.back_porch = vm.hback_porch; + hsync.front_porch = vm.hfront_porch; + } hsync.shift_half_line = false; vsync_lodd.sync_width = vm.vsync_len; vsync_lodd.back_porch = vm.vback_porch; @@ -559,13 +583,20 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, mtk_dpi_config_channel_limit(dpi); mtk_dpi_config_bit_num(dpi, dpi->bit_num); mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); - mtk_dpi_config_yc_map(dpi, dpi->yc_map); mtk_dpi_config_color_format(dpi, dpi->color_format); - mtk_dpi_config_2n_h_fre(dpi); - mtk_dpi_dual_edge(dpi); - mtk_dpi_config_disable_edge(dpi); + if (dpi->conf->is_dpintf) { + mtk_dpi_mask(dpi, DPI_CON, DPINTF_INPUT_2P_EN, + DPINTF_INPUT_2P_EN); + } else { + mtk_dpi_config_yc_map(dpi, dpi->yc_map); + mtk_dpi_config_2n_h_fre(dpi); + mtk_dpi_dual_edge(dpi); + mtk_dpi_config_disable_edge(dpi); + } mtk_dpi_sw_reset(dpi, false); + mtk_dpi_enable(dpi); + return 0; } @@ -608,7 +639,6 @@ static u32 *mtk_dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, u32 *input_fmts; *num_input_fmts = 0; - input_fmts = kcalloc(1, sizeof(*input_fmts), GFP_KERNEL); if (!input_fmts) @@ -634,15 +664,18 @@ static int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge, if (dpi->conf->num_output_fmts) out_bus_format = dpi->conf->output_fmts[0]; - dev_dbg(dpi->dev, "input format 0x%04x, output format 0x%04x\n", - bridge_state->input_bus_cfg.format, - bridge_state->output_bus_cfg.format); + dev_info(dpi->dev, "input format 0x%04x, output format 0x%04x\n", + bridge_state->input_bus_cfg.format, + bridge_state->output_bus_cfg.format); dpi->output_fmt = out_bus_format; dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS; dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB; dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB; - dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB; + if (out_bus_format == MEDIA_BUS_FMT_YUYV8_1X16) + dpi->color_format = MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL; + else + dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB; return 0; } @@ -687,7 +720,7 @@ mtk_dpi_bridge_mode_valid(struct drm_bridge *bridge, { struct mtk_dpi *dpi = bridge_to_dpi(bridge); - if (mode->clock > dpi->conf->max_clock_khz) + if (dpi->conf->max_clock_khz && mode->clock > dpi->conf->max_clock_khz) return MODE_CLOCK_HIGH; return MODE_OK; @@ -801,6 +834,16 @@ static unsigned int mt8183_calculate_factor(int clock) return 2; } +static unsigned int mt8195_dpintf_calculate_factor(int clock) +{ + if (clock < 70000) + return 4; + else if (clock < 200000) + return 2; + else + return 1; +} + static const u32 mt8173_output_fmts[] = { MEDIA_BUS_FMT_RGB888_1X24, }; @@ -810,6 +853,12 @@ static const u32 mt8183_output_fmts[] = { MEDIA_BUS_FMT_RGB888_2X12_BE, }; +static const u32 mt8195_output_fmts[] = { + MEDIA_BUS_FMT_RGB888_1X24, + MEDIA_BUS_FMT_YUV8_1X24, + MEDIA_BUS_FMT_YUYV8_1X16, +}; + static const struct mtk_dpi_yc_limit mtk_dpi_limit = { .c_bottom = 0x0010, .c_top = 0x0FE0, @@ -817,6 +866,13 @@ static const struct mtk_dpi_yc_limit mtk_dpi_limit = { .y_top = 0x0FE0, }; +static const struct mtk_dpi_yc_limit mtk_dpintf_limit = { + .c_bottom = 0x0000, + .c_top = 0xFFF, + .y_bottom = 0x0000, + .y_top = 0xFFF, +}; + static const struct mtk_dpi_conf mt8173_conf = { .cal_factor = mt8173_calculate_factor, .reg_h_fre_con = 0xe0, @@ -882,6 +938,19 @@ static const struct mtk_dpi_conf mt8192_conf = { .limit = &mtk_dpi_limit, }; +static const struct mtk_dpi_conf mt8195_dpintf_conf = { + .cal_factor = mt8195_dpintf_calculate_factor, + .output_fmts = mt8195_output_fmts, + .num_output_fmts = ARRAY_SIZE(mt8195_output_fmts), + .is_dpintf = true, + .dimension_mask = DPINTF_HPW_MASK, + .hvsize_mask = DPINTF_HSIZE_MASK, + .channel_swap_shift = DPINTF_CH_SWAP, + .yuv422_en_bit = DPINTF_YUV422_EN, + .csc_enable_bit = DPINTF_CSC_ENABLE, + .limit = &mtk_dpintf_limit, +}; + static int mtk_dpi_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -929,7 +998,27 @@ static int mtk_dpi_probe(struct platform_device *pdev) if (IS_ERR(dpi->engine_clk)) { ret = PTR_ERR(dpi->engine_clk); if (ret != -EPROBE_DEFER) - dev_err(dev, "Failed to get engine clock: %d\n", ret); + dev_err(dev, "Failed to get engine clock: %d\n", + ret); + + return ret; + } + + dpi->dpi_ck_cg = devm_clk_get_optional(dev, "ck_cg"); + if (IS_ERR(dpi->dpi_ck_cg)) { + ret = PTR_ERR(dpi->dpi_ck_cg); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get dpi ck cg clock: %d\n", + ret); + + return ret; + } + + dpi->dpi_ck_cg = devm_clk_get_optional(dev, "ck_cg"); + if (IS_ERR(dpi->dpi_ck_cg)) { + ret = PTR_ERR(dpi->dpi_ck_cg); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get dpi ck cg clock: %d\n", ret); return ret; } @@ -1004,6 +1093,9 @@ static const struct of_device_id mtk_dpi_of_ids[] = { { .compatible = "mediatek,mt8192-dpi", .data = &mt8192_conf, }, + { .compatible = "mediatek,mt8195-dpintf", + .data = &mt8195_dpintf_conf, + }, { }, }; MODULE_DEVICE_TABLE(of, mtk_dpi_of_ids); diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h index 3a02fabe1662..dd47dd3f2e4f 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_dpi_regs.h @@ -40,10 +40,15 @@ #define FAKE_DE_LEVEN BIT(21) #define FAKE_DE_RODD BIT(22) #define FAKE_DE_REVEN BIT(23) +#define DPINTF_YUV422_EN BIT(24) +#define DPINTF_CSC_ENABLE BIT(26) +#define DPINTF_INPUT_2P_EN BIT(29) #define DPI_OUTPUT_SETTING 0x14 #define CH_SWAP 0 +#define DPINTF_CH_SWAP BIT(1) #define CH_SWAP_MASK (0x7 << 0) +#define DPINTF_CH_SWAP_MASK (0x7 << 1) #define SWAP_RGB 0x00 #define SWAP_GBR 0x01 #define SWAP_BRG 0x02 @@ -80,8 +85,10 @@ #define DPI_SIZE 0x18 #define HSIZE 0 #define HSIZE_MASK (0x1FFF << 0) +#define DPINTF_HSIZE_MASK (0xFFFF << 0) #define VSIZE 16 #define VSIZE_MASK (0x1FFF << 16) +#define DPINTF_VSIZE_MASK (0xFFFF << 16) #define DPI_DDR_SETTING 0x1C #define DDR_EN BIT(0) @@ -93,24 +100,30 @@ #define DPI_TGEN_HWIDTH 0x20 #define HPW 0 #define HPW_MASK (0xFFF << 0) +#define DPINTF_HPW_MASK (0xFFFF << 0) #define DPI_TGEN_HPORCH 0x24 #define HBP 0 #define HBP_MASK (0xFFF << 0) +#define DPINTF_HBP_MASK (0xFFFF << 0) #define HFP 16 #define HFP_MASK (0xFFF << 16) +#define DPINTF_HFP_MASK (0xFFFF << 16) #define DPI_TGEN_VWIDTH 0x28 #define DPI_TGEN_VPORCH 0x2C #define VSYNC_WIDTH_SHIFT 0 #define VSYNC_WIDTH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_WIDTH_MASK (0xFFFF << 0) #define VSYNC_HALF_LINE_SHIFT 16 #define VSYNC_HALF_LINE_MASK BIT(16) #define VSYNC_BACK_PORCH_SHIFT 0 #define VSYNC_BACK_PORCH_MASK (0xFFF << 0) +#define DPINTF_VSYNC_BACK_PORCH_MASK (0xFFFF << 0) #define VSYNC_FRONT_PORCH_SHIFT 16 #define VSYNC_FRONT_PORCH_MASK (0xFFF << 16) +#define DPINTF_VSYNC_FRONT_PORCH_MASK (0xFFFF << 16) #define DPI_BG_HCNTL 0x30 #define BG_RIGHT (0x1FFF << 0) @@ -217,4 +230,26 @@ #define EDGE_SEL_EN BIT(5) #define H_FRE_2N BIT(25) + +#define RGB_TO_JPEG 0x00 +#define RGB_TO_FULL709 0x01 +#define RGB_TO_BT601 0x02 +#define RGB_TO_BT709 0x03 +#define JPEG_TO_RGB 0x04 +#define FULL709_TO_RGB 0x05 +#define BT601_TO_RGB 0x06 +#define BT709_TO_RGB 0x07 +#define JPEG_TO_BT601 0x08 +#define JPEG_TO_BT709 0x09 +#define BT601_TO_JPEG 0xA +#define BT709_TO_JPEG 0xB +#define BT709_TO_BT601 0xC +#define BT601_TO_BT709 0xD +#define JPEG_TO_CERGB 0x14 +#define FULL709_TO_CERGB 0x15 +#define BT601_TO_CERGB 0x16 +#define BT709_TO_CERGB 0x17 +#define RGB_TO_CERGB 0x1C +#define MATRIX_BIT BIT(8) +#define EXT_MATRIX_EN BIT(12) #endif /* __MTK_DPI_REGS_H */ diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 245d0074e12d..3738665a712e 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -419,6 +419,11 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { [MTK_DISP_WDMA] = "wdma", [MTK_DPI] = "dpi", [MTK_DSI] = "dsi", + [MTK_DP_INTF] = "dp-intf", + [MTK_DISP_PWM] = "pwm", + [MTK_DISP_MUTEX] = "mutex", + [MTK_DISP_OD] = "od", + [MTK_DISP_BLS] = "bls", }; struct mtk_ddp_comp_match { @@ -439,6 +444,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi }, [DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc }, [DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc }, + [DDP_COMPONENT_DP_INTF0] = { MTK_DP_INTF, 0, &ddp_dpi }, + [DDP_COMPONENT_DP_INTF1] = { MTK_DP_INTF, 1, &ddp_dpi }, [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi }, [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi }, [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi }, @@ -565,6 +572,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp, type == MTK_DISP_PWM || type == MTK_DISP_RDMA || type == MTK_DPI || + type == MTK_DP_INTF || type == MTK_DSI) return 0; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 825d763d2378..c4e683f46a95 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -37,6 +37,7 @@ enum mtk_ddp_comp_type { MTK_DISP_UFOE, MTK_DISP_WDMA, MTK_DPI, + MTK_DP_INTF, MTK_DSI, MTK_DDP_COMP_TYPE_MAX, }; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index a2a783fc580e..e25ac61aac08 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -690,6 +690,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DPI }, { .compatible = "mediatek,mt8183-dpi", .data = (void *)MTK_DPI }, + { .compatible = "mediatek,mt8195-dpintf", + .data = (void *)MTK_DP_INTF }, { .compatible = "mediatek,mt2701-dsi", .data = (void *)MTK_DSI }, { .compatible = "mediatek,mt8173-dsi", @@ -801,8 +803,9 @@ static int mtk_drm_probe(struct platform_device *pdev) comp_type == MTK_DISP_OVL_2L || comp_type == MTK_DISP_OVL_ADAPTOR || comp_type == MTK_DISP_RDMA || + comp_type == MTK_DSI || comp_type == MTK_DPI || - comp_type == MTK_DSI) { + comp_type == MTK_DP_INTF) { dev_info(dev, "Adding component match for %pOF\n", node); drm_of_component_match_add(dev, &match, component_compare_of, diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 3e998bfb795a..e4b84c347201 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -21,12 +21,12 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_COLOR0, DDP_COMPONENT_COLOR1, DDP_COMPONENT_DITHER, - DDP_COMPONENT_DP_INTF0, - DDP_COMPONENT_DP_INTF1, DDP_COMPONENT_DPI0, DDP_COMPONENT_DPI1, DDP_COMPONENT_DSC0, DDP_COMPONENT_DSC1, + DDP_COMPONENT_DP_INTF0, + DDP_COMPONENT_DP_INTF1, DDP_COMPONENT_DSI0, DDP_COMPONENT_DSI1, DDP_COMPONENT_DSI2, From patchwork Mon May 23 10:47:48 2022 Content-Type: text/plain; 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[2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.51.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:51:42 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 15/21] drm/mediatek: dpi: Only enable dpi after the bridge is enabled Date: Mon, 23 May 2022 12:47:48 +0200 Message-Id: <20220523104758.29531-16-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enabling the dpi too early causes glitches on screen. Move the call to mtk_dpi_enable() at the end of the bridge_enable callback to ensure everything is setup properly before enabling dpi. Signed-off-by: Guillaume Ranquet --- drivers/gpu/drm/mediatek/mtk_dpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c index 763bfb700135..a6b6d62a17e7 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -478,7 +478,6 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) if (dpi->pinctrl && dpi->pins_dpi) pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi); - mtk_dpi_enable(dpi); return 0; err_pixel: @@ -711,6 +710,7 @@ static void mtk_dpi_bridge_enable(struct drm_bridge *bridge) mtk_dpi_power_on(dpi); mtk_dpi_set_display_mode(dpi, &dpi->mode); + mtk_dpi_enable(dpi); } static enum drm_mode_status From patchwork Mon May 23 10:47:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Ranquet X-Patchwork-Id: 575559 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2991BC433F5 for ; Mon, 23 May 2022 10:53:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234529AbiEWKxC (ORCPT ); Mon, 23 May 2022 06:53:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45822 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234664AbiEWKw7 (ORCPT ); Mon, 23 May 2022 06:52:59 -0400 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 628A22FE7F for ; Mon, 23 May 2022 03:52:10 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id y24so744728wmq.5 for ; Mon, 23 May 2022 03:52:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TQgiy1XDkMEG62oOfcg26Pc/4FzYdvAn//3gC4/v5Zk=; b=LcJeSLll7b7XkxZOi6oFcPOcwisKrRD0mKGyBx9w1MSB6d6m5DWVFg+LaA0SincQow oyzfkP5EDVmZk0dtwla8VMOpO/tosI75OjowyRXVkOZe2MeBMDjxq+Zk8snOoEMjWg0Q e/QfpCSe2NvmjVZXesEBnQOJdrlPMpVDEmKuOkM9TfsNGHZ2CgnhA3FbJ3K0Pa3REJ2n 81sj5lHqvQ5iY3Jfe+4/6ff/SKGA7PY7FYnWMhhhZtZdS34UfthIjH4/hzLfy1Q/ZU1e TCTrXbKnVX1w/mcNDiB5mUgtpVDdBmNv20D1GoAsmV79HnLBHL06Bd4v926F+IGgF5TR jNoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TQgiy1XDkMEG62oOfcg26Pc/4FzYdvAn//3gC4/v5Zk=; b=3YSvZrFEsFIzckPOnZGkwNtzbKRBU8o6KoIJREiOvzoD1QYKCjg+yCupanwFxjd8qy sFJfDx8DKwLwVMXopdWW/Ok7YFk+XVBeI/ExbZGm4lPW2kTDa2ddQwR9mojp9rW7FSwF Tco60Al5Jc0MhAPgv0+kvBooy7zh24co8+DJX+YxyTEIYK6PXo6YGtBPc+owZeb4+BtW nvuKby+u+IHbIWPy5pK2aYGnThwf3d9xaUpcgBA2uL4QeD9AeDOxDaUn6moElJup7YHU nXj+LUQ1H+t0mR4RBRi1IsghhIDDdCzrbAizM9Ar6ONPfbzZ+1vpBjTlcqlGu9tlLR39 Vbaw== X-Gm-Message-State: AOAM533FshzSzE6cCwFoUkSVVA5ohxcuhfFcdUE1SQEAPX6z+Np5pYDP RnxiMWrFmCymcRXiXRg7zxWfdw== X-Google-Smtp-Source: ABdhPJzczxM2TesbfgdsrX4MxRcH1xman2Bx9FG8eZM/Ao5Fw16Apten6hubxh/MzctCsyR7U2x5rA== X-Received: by 2002:a05:600c:6015:b0:397:54e1:8279 with SMTP id az21-20020a05600c601500b0039754e18279mr1177859wmb.100.1653303129870; Mon, 23 May 2022 03:52:09 -0700 (PDT) Received: from localhost.localdomain (2a02-8440-6141-9d1b-3074-96af-9642-0003.rev.sfr.net. [2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.52.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:52:09 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 19/21] drm/mediatek: Add mt8195 External DisplayPort support Date: Mon, 23 May 2022 12:47:52 +0200 Message-Id: <20220523104758.29531-20-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds External DisplayPort support to the mt8195 eDP driver. Signed-off-by: Guillaume Ranquet --- drivers/gpu/drm/mediatek/mtk_dp.c | 104 +++++++++++++++++++++++------- 1 file changed, 81 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c index 8eb17ae82bfd..4789853ec5ff 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp.c +++ b/drivers/gpu/drm/mediatek/mtk_dp.c @@ -164,6 +164,11 @@ static struct regmap_config mtk_dp_regmap_config = { .name = "mtk-dp-registers", }; +static bool mtk_dp_is_edp(struct mtk_dp *mtk_dp) +{ + return mtk_dp->next_bridge; +} + static struct mtk_dp *mtk_dp_from_bridge(struct drm_bridge *b) { return container_of(b, struct mtk_dp, bridge); @@ -1054,26 +1059,49 @@ static int mtk_dp_get_calibration_data(struct mtk_dp *mtk_dp) if (!cal_data->ln_tx_impsel_pmos) return -ENOMEM; - cal_data->glb_bias_trim = - check_cal_data_valid(mtk_dp, 1, 0x1e, (buf[3] >> 27) & 0x1f, 0xf); - cal_data->clktx_impse = - check_cal_data_valid(mtk_dp, 1, 0xe, (buf[0] >> 9) & 0xf, 0x8); - cal_data->ln_tx_impsel_pmos[0] = - check_cal_data_valid(mtk_dp, 1, 0xe, (buf[2] >> 28) & 0xf, 0x8); - cal_data->ln_tx_impsel_nmos[0] = - check_cal_data_valid(mtk_dp, 1, 0xe, (buf[2] >> 24) & 0xf, 0x8); - cal_data->ln_tx_impsel_pmos[1] = - check_cal_data_valid(mtk_dp, 1, 0xe, (buf[2] >> 20) & 0xf, 0x8); - cal_data->ln_tx_impsel_nmos[1] = - check_cal_data_valid(mtk_dp, 1, 0xe, (buf[2] >> 16) & 0xf, 0x8); - cal_data->ln_tx_impsel_pmos[2] = - check_cal_data_valid(mtk_dp, 1, 0xe, (buf[2] >> 12) & 0xf, 0x8); - cal_data->ln_tx_impsel_nmos[2] = - check_cal_data_valid(mtk_dp, 1, 0xe, (buf[2] >> 8) & 0xf, 0x8); - cal_data->ln_tx_impsel_pmos[3] = - check_cal_data_valid(mtk_dp, 1, 0xe, (buf[2] >> 4) & 0xf, 0x8); - cal_data->ln_tx_impsel_nmos[3] = - check_cal_data_valid(mtk_dp, 1, 0xe, buf[2] & 0xf, 0x8); + if (mtk_dp_is_edp(mtk_dp)) { + cal_data->glb_bias_trim = + check_cal_data_valid(mtk_dp, 1, 0x1e, (buf[3] >> 27) & 0x1f, 0xf); + cal_data->clktx_impse = + check_cal_data_valid(mtk_dp, 1, 0xe, (buf[0] >> 9) & 0xf, 0x8); + cal_data->ln_tx_impsel_pmos[0] = + check_cal_data_valid(mtk_dp, 1, 0xe, (buf[2] >> 28) & 0xf, 0x8); + cal_data->ln_tx_impsel_nmos[0] = + check_cal_data_valid(mtk_dp, 1, 0xe, (buf[2] >> 24) & 0xf, 0x8); + cal_data->ln_tx_impsel_pmos[1] = + check_cal_data_valid(mtk_dp, 1, 0xe, (buf[2] >> 20) & 0xf, 0x8); + cal_data->ln_tx_impsel_nmos[1] = + check_cal_data_valid(mtk_dp, 1, 0xe, (buf[2] >> 16) & 0xf, 0x8); + cal_data->ln_tx_impsel_pmos[2] = + check_cal_data_valid(mtk_dp, 1, 0xe, (buf[2] >> 12) & 0xf, 0x8); + cal_data->ln_tx_impsel_nmos[2] = + check_cal_data_valid(mtk_dp, 1, 0xe, (buf[2] >> 8) & 0xf, 0x8); + cal_data->ln_tx_impsel_pmos[3] = + check_cal_data_valid(mtk_dp, 1, 0xe, (buf[2] >> 4) & 0xf, 0x8); + cal_data->ln_tx_impsel_nmos[3] = + check_cal_data_valid(mtk_dp, 1, 0xe, buf[2] & 0xf, 0x8); + } else { + cal_data->glb_bias_trim = + check_cal_data_valid(mtk_dp, 1, 0x1e, (buf[0] >> 27) & 0x1f, 0xf); + cal_data->clktx_impse = + check_cal_data_valid(mtk_dp, 1, 0xe, (buf[0] >> 13) & 0xf, 0x8); + cal_data->ln_tx_impsel_pmos[0] = + check_cal_data_valid(mtk_dp, 1, 0xe, (buf[1] >> 28) & 0xf, 0x8); + cal_data->ln_tx_impsel_nmos[0] = + check_cal_data_valid(mtk_dp, 1, 0xe, (buf[1] >> 24) & 0xf, 0x8); + cal_data->ln_tx_impsel_pmos[1] = + check_cal_data_valid(mtk_dp, 1, 0xe, (buf[1] >> 20) & 0xf, 0x8); + cal_data->ln_tx_impsel_nmos[1] = + check_cal_data_valid(mtk_dp, 1, 0xe, (buf[1] >> 16) & 0xf, 0x8); + cal_data->ln_tx_impsel_pmos[2] = + check_cal_data_valid(mtk_dp, 1, 0xe, (buf[1] >> 12) & 0xf, 0x8); + cal_data->ln_tx_impsel_nmos[2] = + check_cal_data_valid(mtk_dp, 1, 0xe, (buf[1] >> 8) & 0xf, 0x8); + cal_data->ln_tx_impsel_pmos[3] = + check_cal_data_valid(mtk_dp, 1, 0xe, (buf[1] >> 4) & 0xf, 0x8); + cal_data->ln_tx_impsel_nmos[3] = + check_cal_data_valid(mtk_dp, 1, 0xe, buf[1] & 0xf, 0x8); + } kfree(buf); @@ -1224,7 +1252,10 @@ static void mtk_dp_video_mute(struct mtk_dp *mtk_dp, bool enable) VIDEO_MUTE_SEL_DP_ENC0_P0_MASK | VIDEO_MUTE_SW_DP_ENC0_P0_MASK); - mtk_dp_sip_atf_call(MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE, enable); + if (mtk_dp_is_edp(mtk_dp)) + mtk_dp_sip_atf_call(MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE, enable); + else + mtk_dp_sip_atf_call(MTK_DP_SIP_ATF_VIDEO_UNMUTE, enable); } static int mtk_dp_power_enable(struct mtk_dp *mtk_dp) @@ -2066,6 +2097,24 @@ static int mtk_dp_dt_parse(struct mtk_dp *mtk_dp, return ret; } +static enum drm_connector_status mtk_dp_bdg_detect(struct drm_bridge *bridge) +{ + struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge); + enum drm_connector_status ret = connector_status_disconnected; + u8 sink_count = 0; + + if (mtk_dp_is_edp(mtk_dp)) + return connector_status_connected; + + if (mtk_dp_plug_state(mtk_dp)) { + drm_dp_dpcd_readb(&mtk_dp->aux, DP_SINK_COUNT, &sink_count); + if (DP_GET_SINK_COUNT(sink_count)) + ret = connector_status_connected; + } + + return ret; +} + static struct edid *mtk_dp_get_edid(struct drm_bridge *bridge, struct drm_connector *connector) { @@ -2422,6 +2471,7 @@ static const struct drm_bridge_funcs mtk_dp_bridge_funcs = { .atomic_disable = mtk_dp_bridge_atomic_disable, .mode_valid = mtk_dp_bridge_mode_valid, .get_edid = mtk_dp_get_edid, + .detect = mtk_dp_bdg_detect, }; static int mtk_dp_probe(struct platform_device *pdev) @@ -2443,7 +2493,11 @@ static int mtk_dp_probe(struct platform_device *pdev) mtk_dp->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0); - if (IS_ERR(mtk_dp->next_bridge)) { + if (IS_ERR(mtk_dp->next_bridge) && PTR_ERR(mtk_dp->next_bridge) == -ENODEV) { + dev_info(dev, + "No panel connected in devicetree, continuing as external DP\n"); + mtk_dp->next_bridge = NULL; + } else if (IS_ERR(mtk_dp->next_bridge)) { return dev_err_probe(dev, PTR_ERR(mtk_dp->next_bridge), "Failed to get bridge\n"); } @@ -2488,7 +2542,10 @@ static int mtk_dp_probe(struct platform_device *pdev) mtk_dp->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD; drm_bridge_add(&mtk_dp->bridge); - mtk_dp->bridge.type = DRM_MODE_CONNECTOR_eDP; + if (mtk_dp_is_edp(mtk_dp)) + mtk_dp->bridge.type = DRM_MODE_CONNECTOR_eDP; + else + mtk_dp->bridge.type = DRM_MODE_CONNECTOR_DisplayPort; pm_runtime_enable(dev); pm_runtime_get_sync(dev); @@ -2550,6 +2607,7 @@ static SIMPLE_DEV_PM_OPS(mtk_dp_pm_ops, mtk_dp_suspend, mtk_dp_resume); static const struct of_device_id mtk_dp_of_match[] = { { .compatible = "mediatek,mt8195-edp-tx" }, + { .compatible = "mediatek,mt8195-dp-tx" }, {}, }; MODULE_DEVICE_TABLE(of, mtk_dp_of_match); From patchwork Mon May 23 10:47:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Guillaume Ranquet X-Patchwork-Id: 575558 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C58B3C433EF for ; Mon, 23 May 2022 10:53:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234410AbiEWKxI (ORCPT ); Mon, 23 May 2022 06:53:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234656AbiEWKxA (ORCPT ); Mon, 23 May 2022 06:53:00 -0400 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66CF131DEE for ; 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[2a02:8440:6141:9d1b:3074:96af:9642:3]) by smtp.gmail.com with ESMTPSA id n11-20020a7bc5cb000000b003942a244f38sm8453607wmk.17.2022.05.23.03.52.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 03:52:22 -0700 (PDT) From: Guillaume Ranquet To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Matthias Brugger , Chunfeng Yun , Kishon Vijay Abraham I , Vinod Koul , Helge Deller , CK Hu , Jitao shi Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, linux-fbdev@vger.kernel.org Subject: [PATCH v10 21/21] drm/mediatek: DP audio support for mt8195 Date: Mon, 23 May 2022 12:47:54 +0200 Message-Id: <20220523104758.29531-22-granquet@baylibre.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220523104758.29531-1-granquet@baylibre.com> References: <20220523104758.29531-1-granquet@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds audio support to the DP driver for mt8195 with up to 8 channels. Signed-off-by: Guillaume Ranquet --- drivers/gpu/drm/mediatek/mtk_dp.c | 784 +++++++++++++++++++++++++++++- 1 file changed, 777 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c index c056bc3ca9f6..05da6565c7f9 100644 --- a/drivers/gpu/drm/mediatek/mtk_dp.c +++ b/drivers/gpu/drm/mediatek/mtk_dp.c @@ -108,9 +108,41 @@ enum mtk_dp_color_depth { MTK_DP_COLOR_DEPTH_UNKNOWN = 5, }; +enum mtk_dp_sdp_type { + MTK_DP_SDP_NONE = 0x00, + MTK_DP_SDP_ACM = 0x01, + MTK_DP_SDP_ISRC = 0x02, + MTK_DP_SDP_AVI = 0x03, + MTK_DP_SDP_AUI = 0x04, + MTK_DP_SDP_SPD = 0x05, + MTK_DP_SDP_MPEG = 0x06, + MTK_DP_SDP_NTSC = 0x07, + MTK_DP_SDP_VSP = 0x08, + MTK_DP_SDP_VSC = 0x09, + MTK_DP_SDP_EXT = 0x0A, + MTK_DP_SDP_PPS0 = 0x0B, + MTK_DP_SDP_PPS1 = 0x0C, + MTK_DP_SDP_PPS2 = 0x0D, + MTK_DP_SDP_PPS3 = 0x0E, + MTK_DP_SDP_DRM = 0x10, + MTK_DP_SDP_MAX_NUM +}; + +struct mtk_dp_sdp_packet { + enum mtk_dp_sdp_type type; + struct dp_sdp sdp; +}; + +struct mtk_dp_audio_cfg { + int sample_rate; + int word_length_bits; + int channels; +}; + struct mtk_dp_info { enum mtk_dp_color_depth depth; enum dp_pixelformat format; + struct mtk_dp_audio_cfg audio_caps; struct mtk_dp_timings timings; }; @@ -148,10 +180,22 @@ struct mtk_dp { struct clk *dp_tx_clk; bool enabled; + bool audio_enable; bool has_fec; /* Protects the mtk_dp struct */ struct mutex dp_lock; + /* Protects the plugged_cb as it's used in both bridge ops and audio */ + struct mutex update_plugged_status_lock; + /* Protects the eld data as it's used in both bridge ops and audio */ + struct mutex eld_lock; + /* Protects edid as it is used in both bridge ops and IRQ handler */ + struct mutex edid_lock; + struct edid *edid; + + hdmi_codec_plugged_cb plugged_cb; + struct device *codec_dev; + u8 connector_eld[MAX_ELD_BYTES]; struct drm_connector *conn; bool need_debounce; @@ -512,15 +556,363 @@ static int mtk_dp_pg_disable(struct mtk_dp *mtk_dp) return ret; } +static int mtk_dp_audio_setup_channels(struct mtk_dp *mtk_dp, + struct mtk_dp_audio_cfg *cfg) +{ + int ret; + u32 channel_enable_bits; + + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3324, + AUDIO_SOURCE_MUX_DP_ENC1_P0_DPRX, + AUDIO_SOURCE_MUX_DP_ENC1_P0_MASK); + if (ret) + return ret; + + /* audio channel count change reset */ + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_33F4, BIT(9), BIT(9)); + if (ret) + return ret; + + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3304, + AU_PRTY_REGEN_DP_ENC1_P0_MASK, + AU_PRTY_REGEN_DP_ENC1_P0_MASK); + if (ret) + return ret; + + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3304, + AU_CH_STS_REGEN_DP_ENC1_P0_MASK, + AU_CH_STS_REGEN_DP_ENC1_P0_MASK); + if (ret) + return ret; + + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3304, + AUDIO_SAMPLE_PRSENT_REGEN_DP_ENC1_P0_MASK, + AUDIO_SAMPLE_PRSENT_REGEN_DP_ENC1_P0_MASK); + if (ret) + return ret; + + switch (cfg->channels) { + case 2: + channel_enable_bits = AUDIO_2CH_SEL_DP_ENC0_P0_MASK | + AUDIO_2CH_EN_DP_ENC0_P0_MASK; + break; + case 8: + default: + channel_enable_bits = AUDIO_8CH_SEL_DP_ENC0_P0_MASK | + AUDIO_8CH_EN_DP_ENC0_P0_MASK; + break; + } + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3088, + channel_enable_bits | AU_EN_DP_ENC0_P0_MASK, + AUDIO_2CH_SEL_DP_ENC0_P0_MASK | AUDIO_2CH_EN_DP_ENC0_P0_MASK | + AUDIO_8CH_SEL_DP_ENC0_P0_MASK | + AUDIO_8CH_EN_DP_ENC0_P0_MASK | AU_EN_DP_ENC0_P0_MASK); + if (ret) + return ret; + + /* audio channel count change reset */ + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_33F4, 0, BIT(9)); + if (ret) + return ret; + + /* enable audio reset */ + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_33F4, BIT(0), BIT(0)); + + return ret; +} + +static int mtk_dp_audio_channel_status_set(struct mtk_dp *mtk_dp, + struct mtk_dp_audio_cfg *cfg) +{ + int ret; + struct snd_aes_iec958 iec = { 0 }; + + switch (cfg->sample_rate) { + case 32000: + iec.status[3] = IEC958_AES3_CON_FS_32000; + break; + case 44100: + iec.status[3] = IEC958_AES3_CON_FS_44100; + break; + case 48000: + iec.status[3] = IEC958_AES3_CON_FS_48000; + break; + case 88200: + iec.status[3] = IEC958_AES3_CON_FS_88200; + break; + case 96000: + iec.status[3] = IEC958_AES3_CON_FS_96000; + break; + case 192000: + iec.status[3] = IEC958_AES3_CON_FS_192000; + break; + default: + iec.status[3] = IEC958_AES3_CON_FS_NOTID; + break; + } + + switch (cfg->word_length_bits) { + case 16: + iec.status[4] = IEC958_AES4_CON_WORDLEN_20_16; + break; + case 20: + iec.status[4] = IEC958_AES4_CON_WORDLEN_20_16 | + IEC958_AES4_CON_MAX_WORDLEN_24; + break; + case 24: + iec.status[4] = IEC958_AES4_CON_WORDLEN_24_20 | + IEC958_AES4_CON_MAX_WORDLEN_24; + break; + default: + iec.status[4] = IEC958_AES4_CON_WORDLEN_NOTID; + } + + /* IEC 60958 consumer channel status bits */ + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_308C, + 0, + CH_STATUS_0_DP_ENC0_P0_MASK); + if (ret) + return ret; + + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3090, + iec.status[3] << 8, + CH_STATUS_1_DP_ENC0_P0_MASK); + if (ret) + return ret; + + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3094, iec.status[4], + CH_STATUS_2_DP_ENC0_P0_MASK); + + return ret; +} + +static int mtk_dp_audio_sdp_asp_set_channels(struct mtk_dp *mtk_dp, + int channels) +{ + if (channels != 2 && channels != 8) + channels = 8; + + return mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_312C, + (channels - 1) << ASP_HB3_DP_ENC0_P0_SHIFT, + ASP_HB2_DP_ENC0_P0_MASK | ASP_HB3_DP_ENC0_P0_MASK); +} + +static int mtk_dp_audio_set_divider(struct mtk_dp *mtk_dp) +{ + return mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30BC, + AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2, + AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK); +} + static bool mtk_dp_plug_state(struct mtk_dp *mtk_dp) { return !!(mtk_dp_read(mtk_dp, MTK_DP_TRANS_P0_3414) & HPD_DB_DP_TRANS_P0_MASK); } -static void mtk_dp_aux_irq_clear(struct mtk_dp *mtk_dp) +static int mtk_dp_sdp_trigger_packet(struct mtk_dp *mtk_dp, + enum mtk_dp_sdp_type type) +{ + int ret; + + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3280, type, + SDP_PACKET_TYPE_DP_ENC1_P0_MASK); + if (ret) + return ret; + + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3280, SDP_PACKET_W_DP_ENC1_P0, + SDP_PACKET_W_DP_ENC1_P0); + + return ret; +} + +static void mtk_dp_sdp_set_data(struct mtk_dp *mtk_dp, u8 *data_bytes) +{ + mtk_dp_bulk_16bit_write(mtk_dp, MTK_DP_ENC1_P0_3200, data_bytes, 0x10); +} + +static void mtk_dp_sdp_set_header(struct mtk_dp *mtk_dp, + enum mtk_dp_sdp_type type, + struct dp_sdp_header *header) +{ + u32 db_addr; + + switch (type) { + case MTK_DP_SDP_DRM: + db_addr = MTK_DP_ENC0_P0_3138; + break; + case MTK_DP_SDP_PPS0: + case MTK_DP_SDP_PPS1: + case MTK_DP_SDP_PPS2: + case MTK_DP_SDP_PPS3: + db_addr = MTK_DP_ENC0_P0_3130; + break; + default: + db_addr = MTK_DP_ENC0_P0_30D8 + (type - MTK_DP_SDP_ACM) * 8; + } + + mtk_dp_bulk_16bit_write(mtk_dp, db_addr, (u8 *)header, 4); +} + +static const u32 mtk_dp_sdp_type_to_reg[MTK_DP_SDP_MAX_NUM] = { + /* MTK_DP_SDP_NONE => */ 0x0, + /* MTK_DP_SDP_ACM => */ MTK_DP_ENC0_P0_30B4, + /* MTK_DP_SDP_ISRC => */ MTK_DP_ENC0_P0_30B4 + 1, + /* MTK_DP_SDP_AVI => */ MTK_DP_ENC0_P0_30A4 + 1, + /* MTK_DP_SDP_AUI => */ MTK_DP_ENC0_P0_30A8, + /* MTK_DP_SDP_SPD => */ MTK_DP_ENC0_P0_30A8 + 1, + /* MTK_DP_SDP_MPEG => */ MTK_DP_ENC0_P0_30AC, + /* MTK_DP_SDP_NTSC => */ MTK_DP_ENC0_P0_30AC + 1, + /* MTK_DP_SDP_VSP => */ MTK_DP_ENC0_P0_30B0, + /* MTK_DP_SDP_VSC => */ MTK_DP_ENC0_P0_30B8, + /* MTK_DP_SDP_EXT => */ MTK_DP_ENC0_P0_30B0 + 1, + /* MTK_DP_SDP_PPS0 => */ MTK_DP_ENC0_P0_31E8, + /* MTK_DP_SDP_PPS1 => */ MTK_DP_ENC0_P0_31E8, + /* MTK_DP_SDP_PPS2 => */ MTK_DP_ENC0_P0_31E8, + /* MTK_DP_SDP_PPS3 => */ MTK_DP_ENC0_P0_31E8, + /* MTK_DP_SDP_DRM => */ MTK_DP_ENC0_P0_31DC, +}; + +static int mtk_dp_disable_sdp(struct mtk_dp *mtk_dp, enum mtk_dp_sdp_type type) +{ + if (type == MTK_DP_SDP_NONE) + return -EINVAL; + + /* Disable periodic send */ + return mtk_dp_update_bits(mtk_dp, mtk_dp_sdp_type_to_reg[type] & 0xfffc, 0, + 0xFF << ((mtk_dp_sdp_type_to_reg[type] & 3) * 8)); +} + +static int mtk_dp_setup_sdp(struct mtk_dp *mtk_dp, + struct mtk_dp_sdp_packet *packet) +{ + int ret = -EINVAL; + + mtk_dp_sdp_set_data(mtk_dp, packet->sdp.db); + mtk_dp_sdp_set_header(mtk_dp, packet->type, &packet->sdp.sdp_header); + + mtk_dp_disable_sdp(mtk_dp, packet->type); + + switch (packet->type) { + case MTK_DP_SDP_NONE: + break; + case MTK_DP_SDP_ISRC: + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_31EC, + 0x1C << ISRC1_HB3_DP_ENC0_P0_SHIFT, + ISRC1_HB3_DP_ENC0_P0_MASK); + if (ret) + break; + + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3280, MTK_DP_SDP_ISRC, + SDP_PACKET_TYPE_DP_ENC1_P0_MASK); + if (ret) + break; + + if (packet->sdp.sdp_header.HB3 & BIT(2)) + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30BC, + BIT(ISRC_CONT_DP_ENC0_P0_SHIFT), + ISRC_CONT_DP_ENC0_P0_MASK); + else + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30BC, 0, + ISRC_CONT_DP_ENC0_P0_MASK); + + if (ret) + break; + + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3280, + SDP_PACKET_W_DP_ENC1_P0, + SDP_PACKET_W_DP_ENC1_P0); + if (ret) + break; + + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30B4, + 5 << ISRC_CFG_DP_ENC0_P0_SHIFT, + ISRC_CFG_DP_ENC0_P0_MASK); + break; + case MTK_DP_SDP_DRM: + mtk_dp_sdp_trigger_packet(mtk_dp, packet->type); + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_31DC, + 5 << HDR0_CFG_DP_ENC0_P0_SHIFT, + HDR0_CFG_DP_ENC0_P0_MASK); + if (ret) + break; + + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_31EC, + 0x1C << ISRC1_HB3_DP_ENC0_P0_SHIFT, + ISRC1_HB3_DP_ENC0_P0_MASK); + if (ret) + break; + + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3280, MTK_DP_SDP_ISRC, + SDP_PACKET_TYPE_DP_ENC1_P0_MASK); + if (ret) + break; + + if (packet->sdp.sdp_header.HB3 & BIT(2)) + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30BC, + BIT(ISRC_CONT_DP_ENC0_P0_SHIFT), + ISRC_CONT_DP_ENC0_P0_MASK); + else + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30BC, 0, + ISRC_CONT_DP_ENC0_P0_MASK); + + if (ret) + break; + + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3280, + SDP_PACKET_W_DP_ENC1_P0, + SDP_PACKET_W_DP_ENC1_P0); + if (ret) + break; + + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30B4, + 5 << ISRC_CFG_DP_ENC0_P0_SHIFT, + ISRC_CFG_DP_ENC0_P0_MASK); + break; + case MTK_DP_SDP_ACM: + case MTK_DP_SDP_AVI: + case MTK_DP_SDP_AUI: + case MTK_DP_SDP_SPD: + case MTK_DP_SDP_MPEG: + case MTK_DP_SDP_NTSC: + case MTK_DP_SDP_VSP: + case MTK_DP_SDP_VSC: + case MTK_DP_SDP_EXT: + case MTK_DP_SDP_PPS0: + case MTK_DP_SDP_PPS1: + case MTK_DP_SDP_PPS2: + case MTK_DP_SDP_PPS3: + mtk_dp_sdp_trigger_packet(mtk_dp, packet->type); + /* Enable periodic sending */ + ret = mtk_dp_update_bits(mtk_dp, + mtk_dp_sdp_type_to_reg[packet->type] & 0xfffc, + 0x05 << ((mtk_dp_sdp_type_to_reg[packet->type] & 3) * 8), + 0xff << ((mtk_dp_sdp_type_to_reg[packet->type] & 3) * 8)); + break; + default: + break; + } + + return ret; +} + +static int mtk_dp_sdp_vsc_ext_disable(struct mtk_dp *mtk_dp) +{ + int ret; + + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30A0, 0, + BIT(7) | BIT(8) | BIT(12)); + if (ret) + return ret; + + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_328C, 0, BIT(7)); + + return ret; +} + +static int mtk_dp_aux_irq_clear(struct mtk_dp *mtk_dp) { - mtk_dp_write(mtk_dp, MTK_DP_AUX_P0_3640, + return mtk_dp_write(mtk_dp, MTK_DP_AUX_P0_3640, BIT(AUX_400US_TIMEOUT_IRQ_AUX_TX_P0_SHIFT) | BIT(AUX_RX_DATA_RECV_IRQ_AUX_TX_P0_SHIFT) | BIT(AUX_RX_ADDR_RECV_IRQ_AUX_TX_P0_SHIFT) | @@ -1244,20 +1636,71 @@ static int mtk_dp_training_set_scramble(struct mtk_dp *mtk_dp, bool enable) DP_SCR_EN_DP_TRANS_P0_MASK); } -static void mtk_dp_video_mute(struct mtk_dp *mtk_dp, bool enable) +static int mtk_dp_video_mute(struct mtk_dp *mtk_dp, bool enable) { + int ret; u32 val = BIT(VIDEO_MUTE_SEL_DP_ENC0_P0_SHIFT); if (enable) val |= BIT(VIDEO_MUTE_SW_DP_ENC0_P0_SHIFT); - mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3000, val, - VIDEO_MUTE_SEL_DP_ENC0_P0_MASK | - VIDEO_MUTE_SW_DP_ENC0_P0_MASK); + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3000, val, + VIDEO_MUTE_SEL_DP_ENC0_P0_MASK | VIDEO_MUTE_SW_DP_ENC0_P0_MASK); + + if (ret) + return ret; if (mtk_dp_is_edp(mtk_dp)) mtk_dp_sip_atf_call(MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE, enable); else mtk_dp_sip_atf_call(MTK_DP_SIP_ATF_VIDEO_UNMUTE, enable); + + return 0; +} + +static int mtk_dp_audio_mute(struct mtk_dp *mtk_dp, bool mute) +{ + int ret; + + if (mute) { + ret = mtk_dp_update_bits(mtk_dp, + MTK_DP_ENC0_P0_3030, + BIT(VBID_AUDIO_MUTE_SW_DP_ENC0_P0_SHIFT) | + BIT(VBID_AUDIO_MUTE_SEL_DP_ENC0_P0_SHIFT), + VBID_AUDIO_MUTE_FLAG_SW_DP_ENC0_P0_MASK | + VBID_AUDIO_MUTE_FLAG_SEL_DP_ENC0_P0_MASK); + if (ret) + return ret; + + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3088, 0, + AU_EN_DP_ENC0_P0_MASK); + if (ret) + return ret; + + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30A4, 0, + AU_TS_CFG_DP_ENC0_P0_MASK); + if (ret) + return ret; + + } else { + ret = mtk_dp_update_bits(mtk_dp, + MTK_DP_ENC0_P0_3030, 0, + VBID_AUDIO_MUTE_FLAG_SW_DP_ENC0_P0_MASK | + VBID_AUDIO_MUTE_FLAG_SEL_DP_ENC0_P0_MASK); + if (ret) + return ret; + + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3088, + BIT(AU_EN_DP_ENC0_P0_SHIFT), + AU_EN_DP_ENC0_P0_MASK); + if (ret) + return ret; + + /* Send one every two frames */ + ret = mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30A4, 0x0F, + AU_TS_CFG_DP_ENC0_P0_MASK); + } + + return ret; } static int mtk_dp_power_enable(struct mtk_dp *mtk_dp) @@ -1327,6 +1770,83 @@ static void mtk_dp_initialize_priv_data(struct mtk_dp *mtk_dp) mtk_dp->info.timings.frame_rate = 60; mtk_dp->has_fec = false; + mtk_dp->audio_enable = false; +} + +static int mtk_dp_sdp_set_down_cnt_init(struct mtk_dp *mtk_dp, + u32 sram_read_start) +{ + u32 sdp_down_cnt_init = 0; + u32 dc_offset; + struct drm_display_mode mode; + struct mtk_dp_timings *timings = &mtk_dp->info.timings; + + drm_display_mode_from_videomode(&timings->vm, &mode); + + if (mtk_dp->info.timings.pix_rate_khz > 0) + sdp_down_cnt_init = sram_read_start * + mtk_dp->train_info.link_rate * 2700 * 8 / + (timings->pix_rate_khz * 4); + + switch (mtk_dp->train_info.lane_count) { + case 1: + sdp_down_cnt_init = sdp_down_cnt_init > 0x1A ? + sdp_down_cnt_init : + 0x1A; /* 26 */ + break; + case 2: + /* case for LowResolution && High Audio Sample Rate */ + dc_offset = mode.vtotal <= 525 ? 0x04 : 0x00; + sdp_down_cnt_init = sdp_down_cnt_init > 0x10 ? + sdp_down_cnt_init : + 0x10 + dc_offset; /* 20 or 16 */ + break; + case 4: + default: + sdp_down_cnt_init = + sdp_down_cnt_init > 0x06 ? sdp_down_cnt_init : 0x06; /*6 */ + break; + } + + return mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3040, + sdp_down_cnt_init + << SDP_DOWN_CNT_INIT_DP_ENC0_P0_SHIFT, + SDP_DOWN_CNT_INIT_DP_ENC0_P0_MASK); +} + +static int mtk_dp_sdp_set_down_cnt_init_in_hblank(struct mtk_dp *mtk_dp) +{ + int pix_clk_mhz; + u32 dc_offset; + u32 spd_down_cnt_init = 0; + struct drm_display_mode mode; + struct mtk_dp_timings *timings = &mtk_dp->info.timings; + + drm_display_mode_from_videomode(&timings->vm, &mode); + + pix_clk_mhz = mtk_dp->info.format == DP_PIXELFORMAT_YUV420 ? + mtk_dp->info.timings.pix_rate_khz / 2000 : + mtk_dp->info.timings.pix_rate_khz / 1000; + + switch (mtk_dp->train_info.lane_count) { + case 1: + spd_down_cnt_init = 0x20; + break; + case 2: + dc_offset = (mode.vtotal <= 525) ? 0x14 : 0x00; + spd_down_cnt_init = 0x18 + dc_offset; + break; + case 4: + default: + dc_offset = (mode.vtotal <= 525) ? 0x08 : 0x00; + if (pix_clk_mhz > mtk_dp->train_info.link_rate * 27) + spd_down_cnt_init = 0x8; + else + spd_down_cnt_init = 0x10 + dc_offset; + break; + } + return mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3364, spd_down_cnt_init, + SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_MASK); } static void mtk_dp_setup_tu(struct mtk_dp *mtk_dp) @@ -1343,6 +1863,8 @@ static void mtk_dp_setup_tu(struct mtk_dp *mtk_dp) } mtk_dp_setup_encoder(mtk_dp); + mtk_dp_sdp_set_down_cnt_init_in_hblank(mtk_dp); + mtk_dp_sdp_set_down_cnt_init(mtk_dp, sram_read_start); } static void mtk_dp_calculate_pixrate(struct mtk_dp *mtk_dp) @@ -1420,6 +1942,17 @@ static int mtk_dp_hpd_sink_event(struct mtk_dp *mtk_dp) return 0; } +static void mtk_dp_sdp_stop_sending(struct mtk_dp *mtk_dp) +{ + u8 packet_type; + + for (packet_type = MTK_DP_SDP_ACM; packet_type < MTK_DP_SDP_MAX_NUM; + packet_type++) + mtk_dp_disable_sdp(mtk_dp, packet_type); + + mtk_dp_sdp_vsc_ext_disable(mtk_dp); +} + static void mtk_dp_train_update_swing_pre(struct mtk_dp *mtk_dp, int lanes, u8 dpcd_adjust_req[2]) { @@ -1725,6 +2258,52 @@ static bool mtk_dp_parse_capabilities(struct mtk_dp *mtk_dp) return true; } +static int mtk_dp_edid_parse_audio_capabilities(struct mtk_dp *mtk_dp, + struct mtk_dp_audio_cfg *cfg) +{ + struct cea_sad *sads; + int sad_count; + int i; + int ret = 0; + + mutex_lock(&mtk_dp->edid_lock); + if (!mtk_dp->edid) { + mutex_unlock(&mtk_dp->edid_lock); + dev_err(mtk_dp->dev, "EDID not found!\n"); + return -EINVAL; + } + + sad_count = drm_edid_to_sad(mtk_dp->edid, &sads); + mutex_unlock(&mtk_dp->edid_lock); + if (sad_count <= 0) { + drm_info(mtk_dp->drm_dev, "The SADs is NULL\n"); + return 0; + } + + for (i = 0; i < sad_count; i++) { + int sample_rate; + int word_length; + /* Only PCM supported at the moment */ + if (sads[i].format != HDMI_AUDIO_CODING_TYPE_PCM) + continue; + + sample_rate = drm_cea_sad_get_sample_rate(&sads[i]); + word_length = + drm_cea_sad_get_uncompressed_word_length(&sads[i]); + if (sample_rate <= 0 || word_length <= 0) + continue; + + cfg->channels = sads[i].channels; + cfg->word_length_bits = word_length; + cfg->sample_rate = sample_rate; + ret = 1; + break; + } + kfree(sads); + + return ret; +} + static void mtk_dp_train_change_mode(struct mtk_dp *mtk_dp) { phy_reset(mtk_dp->phy); @@ -1830,6 +2409,48 @@ static void mtk_dp_video_enable(struct mtk_dp *mtk_dp, bool enable) } } +static void mtk_dp_audio_sdp_setup(struct mtk_dp *mtk_dp, + struct mtk_dp_audio_cfg *cfg) +{ + struct mtk_dp_sdp_packet packet; + struct hdmi_audio_infoframe frame; + + hdmi_audio_infoframe_init(&frame); + frame.coding_type = HDMI_AUDIO_CODING_TYPE_PCM; + frame.channels = cfg->channels; + frame.sample_frequency = cfg->sample_rate; + + switch (cfg->word_length_bits) { + case 16: + frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_16; + break; + case 20: + frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_20; + break; + case 24: + default: + frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_24; + break; + } + + packet.type = MTK_DP_SDP_AUI; + hdmi_audio_infoframe_pack_for_dp(&frame, &packet.sdp, + MTK_DP_DP_VERSION_11); + + mtk_dp_audio_sdp_asp_set_channels(mtk_dp, cfg->channels); + mtk_dp_setup_sdp(mtk_dp, &packet); +} + +static void mtk_dp_audio_setup(struct mtk_dp *mtk_dp, + struct mtk_dp_audio_cfg *cfg) +{ + mtk_dp_audio_sdp_setup(mtk_dp, cfg); + mtk_dp_audio_channel_status_set(mtk_dp, cfg); + + mtk_dp_audio_setup_channels(mtk_dp, cfg); + mtk_dp_audio_set_divider(mtk_dp); +} + static void mtk_dp_video_config(struct mtk_dp *mtk_dp) { mtk_dp_mn_overwrite_disable(mtk_dp); @@ -1845,6 +2466,7 @@ static void mtk_dp_state_handler(struct mtk_dp *mtk_dp) switch (mtk_dp->state) { case MTK_DP_STATE_INITIAL: mtk_dp_video_mute(mtk_dp, true); + mtk_dp_audio_mute(mtk_dp, true); mtk_dp->state = MTK_DP_STATE_IDLE; break; @@ -1857,12 +2479,19 @@ static void mtk_dp_state_handler(struct mtk_dp *mtk_dp) mtk_dp_video_config(mtk_dp); mtk_dp_video_enable(mtk_dp, true); + if (mtk_dp->audio_enable) { + mtk_dp_audio_setup(mtk_dp, &mtk_dp->info.audio_caps); + mtk_dp_audio_mute(mtk_dp, false); + } + mtk_dp->state = MTK_DP_STATE_NORMAL; break; case MTK_DP_STATE_NORMAL: if (mtk_dp->train_state != MTK_DP_TRAIN_STATE_NORMAL) { mtk_dp_video_mute(mtk_dp, true); + mtk_dp_audio_mute(mtk_dp, true); + mtk_dp_sdp_stop_sending(mtk_dp); mtk_dp->state = MTK_DP_STATE_IDLE; } break; @@ -1901,7 +2530,15 @@ static int mtk_dp_train_handler(struct mtk_dp *mtk_dp) } break; - case MTK_DP_TRAIN_STATE_CHECKEDID: + case MTK_DP_TRAIN_STATE_CHECKEDID: { + int caps_found = mtk_dp_edid_parse_audio_capabilities(mtk_dp, + &mtk_dp->info.audio_caps); + mtk_dp->audio_enable = caps_found > 0; + if (!mtk_dp->audio_enable) + memset(&mtk_dp->info.audio_caps, 0, + sizeof(mtk_dp->info.audio_caps)); + } + mtk_dp->train_state = MTK_DP_TRAIN_STATE_TRAINING_PRE; break; @@ -1914,6 +2551,7 @@ static int mtk_dp_train_handler(struct mtk_dp *mtk_dp) ret = mtk_dp_train_start(mtk_dp); if (ret == 0) { mtk_dp_video_mute(mtk_dp, true); + mtk_dp_audio_mute(mtk_dp, true); mtk_dp->train_state = MTK_DP_TRAIN_STATE_NORMAL; mtk_dp_fec_enable(mtk_dp, mtk_dp->has_fec); } else if (ret != -EAGAIN) { @@ -1988,11 +2626,13 @@ static irqreturn_t mtk_dp_hpd_event_thread(int hpd, void *dev) if (!mtk_dp->train_info.cable_plugged_in || !mtk_dp_plug_state(mtk_dp)) { mtk_dp_video_mute(mtk_dp, true); + mtk_dp_audio_mute(mtk_dp, true); mtk_dp_initialize_priv_data(mtk_dp); mtk_dp_set_idle_pattern(mtk_dp, true); if (mtk_dp->has_fec) mtk_dp_fec_enable(mtk_dp, false); + mtk_dp_sdp_stop_sending(mtk_dp); mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, DP_PWR_STATE_BANDGAP_TPLL, @@ -2107,6 +2747,18 @@ static int mtk_dp_dt_parse(struct mtk_dp *mtk_dp, return ret; } +static void mtk_dp_update_plugged_status(struct mtk_dp *mtk_dp) +{ + bool connected, has_audio; + + mutex_lock(&mtk_dp->update_plugged_status_lock); + connected = mtk_dp_plug_state(mtk_dp); + has_audio = drm_detect_monitor_audio(mtk_dp->edid); + if (mtk_dp->plugged_cb && mtk_dp->codec_dev) + mtk_dp->plugged_cb(mtk_dp->codec_dev, connected & has_audio); + mutex_unlock(&mtk_dp->update_plugged_status_lock); +} + static enum drm_connector_status mtk_dp_bdg_detect(struct drm_bridge *bridge) { struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge); @@ -2122,6 +2774,7 @@ static enum drm_connector_status mtk_dp_bdg_detect(struct drm_bridge *bridge) ret = connector_status_connected; } + mtk_dp_update_plugged_status(mtk_dp); return ret; } @@ -2308,6 +2961,7 @@ static void mtk_dp_bridge_atomic_disable(struct drm_bridge *bridge, struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge); mtk_dp_video_mute(mtk_dp, true); + mtk_dp_audio_mute(mtk_dp, true); mtk_dp->state = MTK_DP_STATE_IDLE; mtk_dp->train_state = MTK_DP_TRAIN_STATE_STARTUP; @@ -2345,6 +2999,10 @@ static void mtk_dp_bridge_atomic_enable(struct drm_bridge *bridge, return; } + mutex_lock(&mtk_dp->eld_lock); + memcpy(mtk_dp->connector_eld, mtk_dp->conn->eld, MAX_ELD_BYTES); + mutex_unlock(&mtk_dp->eld_lock); + mtk_dp->enabled = true; } @@ -2491,6 +3149,104 @@ static void mtk_dp_debounce_timer(struct timer_list *t) mtk_dp->need_debounce = true; } +/* + * HDMI audio codec callbacks + */ +static int mtk_dp_audio_hw_params(struct device *dev, void *data, + struct hdmi_codec_daifmt *daifmt, + struct hdmi_codec_params *params) +{ + struct mtk_dp *mtk_dp = dev_get_drvdata(dev); + struct mtk_dp_audio_cfg cfg; + + if (!mtk_dp->enabled) { + pr_err("%s, DP is not ready!\n", __func__); + return -ENODEV; + } + + cfg.channels = params->cea.channels; + cfg.sample_rate = params->sample_rate; + cfg.word_length_bits = 24; + + mtk_dp_audio_setup(mtk_dp, &cfg); + + return 0; +} + +static int mtk_dp_audio_startup(struct device *dev, void *data) +{ + struct mtk_dp *mtk_dp = dev_get_drvdata(dev); + + mtk_dp_audio_mute(mtk_dp, false); + + return 0; +} + +static void mtk_dp_audio_shutdown(struct device *dev, void *data) +{ + struct mtk_dp *mtk_dp = dev_get_drvdata(dev); + + mtk_dp_audio_mute(mtk_dp, true); +} + +static int mtk_dp_audio_get_eld(struct device *dev, void *data, uint8_t *buf, + size_t len) +{ + struct mtk_dp *mtk_dp = dev_get_drvdata(dev); + + if (mtk_dp->enabled) + memcpy(buf, mtk_dp->connector_eld, len); + else + memset(buf, 0, len); + + return 0; +} + +static int mtk_dp_audio_hook_plugged_cb(struct device *dev, void *data, + hdmi_codec_plugged_cb fn, + struct device *codec_dev) +{ + struct mtk_dp *mtk_dp = data; + + mutex_lock(&mtk_dp->update_plugged_status_lock); + mtk_dp->plugged_cb = fn; + mtk_dp->codec_dev = codec_dev; + mutex_unlock(&mtk_dp->update_plugged_status_lock); + + mtk_dp_update_plugged_status(mtk_dp); + + return 0; +} + +static const struct hdmi_codec_ops mtk_dp_audio_codec_ops = { + .hw_params = mtk_dp_audio_hw_params, + .audio_startup = mtk_dp_audio_startup, + .audio_shutdown = mtk_dp_audio_shutdown, + .get_eld = mtk_dp_audio_get_eld, + .hook_plugged_cb = mtk_dp_audio_hook_plugged_cb, + .no_capture_mute = 1, +}; + +static int mtk_dp_register_audio_driver(struct device *dev) +{ + struct mtk_dp *mtk_dp = dev_get_drvdata(dev); + struct hdmi_codec_pdata codec_data = { + .ops = &mtk_dp_audio_codec_ops, + .max_i2s_channels = 8, + .i2s = 1, + .data = mtk_dp, + }; + struct platform_device *pdev; + + pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, + PLATFORM_DEVID_AUTO, &codec_data, + sizeof(codec_data)); + if (IS_ERR(pdev)) + return PTR_ERR(pdev); + + return 0; +} + static int mtk_dp_probe(struct platform_device *pdev) { struct mtk_dp *mtk_dp; @@ -2534,9 +3290,21 @@ static int mtk_dp_probe(struct platform_device *pdev) return dev_err_probe(dev, -EPROBE_DEFER, "failed to request mediatek dptx irq\n"); mutex_init(&mtk_dp->dp_lock); + mutex_init(&mtk_dp->edid_lock); + mutex_init(&mtk_dp->eld_lock); + mutex_init(&mtk_dp->update_plugged_status_lock); platform_set_drvdata(pdev, mtk_dp); + if (!mtk_dp_is_edp(mtk_dp)) { + ret = mtk_dp_register_audio_driver(dev); + if (ret) { + dev_err(dev, "Failed to register audio driver: %d\n", + ret); + return ret; + } + } + mtk_dp->phy_dev = platform_device_register_data(dev, "mediatek-dp-phy", PLATFORM_DEVID_AUTO, &mtk_dp->regs, @@ -2579,6 +3347,7 @@ static int mtk_dp_remove(struct platform_device *pdev) platform_device_unregister(mtk_dp->phy_dev); mtk_dp_video_mute(mtk_dp, true); + mtk_dp_audio_mute(mtk_dp, true); del_timer_sync(&mtk_dp->debounce_timer); pm_runtime_disable(&pdev->dev);