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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id c16-20020a624e10000000b0050dc7628142sm7721788pfb.28.2022.05.23.13.47.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 13:47:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 01/18] target/arm: Allow raise_exception to handle finding target EL Date: Mon, 23 May 2022 13:47:25 -0700 Message-Id: <20220523204742.740932-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220523204742.740932-1-richard.henderson@linaro.org> References: <20220523204742.740932-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The work of finding the correct target EL for an exception is currently split between raise_exception and target_exception_el. Begin merging these by allowing the input to raise_exception to be zero and use exception_target_el for that case. Signed-off-by: Richard Henderson --- target/arm/internals.h | 11 ++++++----- target/arm/op_helper.c | 13 +++++++++---- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index b654bee468..03363b0f32 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -111,18 +111,19 @@ FIELD(DBGWCR, SSCE, 29, 1) /** * raise_exception: Raise the specified exception. * Raise a guest exception with the specified value, syndrome register - * and target exception level. This should be called from helper functions, - * and never returns because we will longjump back up to the CPU main loop. + * and the current or target exception level. This should be called from + * helper functions, and never returns because we will longjump back up + * to the CPU main loop. */ G_NORETURN void raise_exception(CPUARMState *env, uint32_t excp, - uint32_t syndrome, uint32_t target_el); + uint32_t syndrome, uint32_t cur_or_target_el); /* * Similarly, but also use unwinding to restore cpu state. */ G_NORETURN void raise_exception_ra(CPUARMState *env, uint32_t excp, - uint32_t syndrome, uint32_t target_el, - uintptr_t ra); + uint32_t syndrome, + uint32_t cur_or_target_el, uintptr_t ra); /* * For AArch64, map a given EL to an index in the banked_spsr array. diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index c4bd668870..6b9141b79a 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -28,10 +28,15 @@ #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) -void raise_exception(CPUARMState *env, uint32_t excp, - uint32_t syndrome, uint32_t target_el) +void raise_exception(CPUARMState *env, uint32_t excp, uint32_t syndrome, + uint32_t cur_or_target_el) { CPUState *cs = env_cpu(env); + int target_el = cur_or_target_el; + + if (cur_or_target_el == 0) { + target_el = exception_target_el(env); + } if (target_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { /* @@ -54,7 +59,7 @@ void raise_exception(CPUARMState *env, uint32_t excp, } void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, - uint32_t target_el, uintptr_t ra) + uint32_t cur_or_target_el, uintptr_t ra) { CPUState *cs = env_cpu(env); @@ -64,7 +69,7 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, * the caller passed us, and cannot use cpu_loop_exit_restore(). */ cpu_restore_state(cs, ra, true); - raise_exception(env, excp, syndrome, target_el); + raise_exception(env, excp, syndrome, cur_or_target_el); } uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc, From patchwork Mon May 23 20:47:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 575409 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:c603:0:0:0:0 with SMTP id jv3csp1730436mab; Mon, 23 May 2022 13:56:13 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy5arnZupylPv+PYmZcQkgkpNn1B4pzQv2NoHPCt2Qe/+vge5NhL4lIEp0JEfB/1e/Gxjo5 X-Received: by 2002:a05:620a:2586:b0:680:f3c1:9d4a with SMTP id x6-20020a05620a258600b00680f3c19d4amr14822640qko.619.1653339283640; Mon, 23 May 2022 13:54:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653339283; cv=none; d=google.com; s=arc-20160816; b=sW/noToJzMz0iG3SmwB0ARUJKEKui/Cpu1ah/eOYbckUfePpIvovG7wbTVop1D3pad OizoEwA3x2IYKjrch3fy8YWZEP6Z8Dq9Nvnv5/Sz9a7jBim4WemUimfhRzRuFP3/pdxg rCclfCn5Xa5cpfuUiV9bnS8QU1RSsvofK/YzSjjwp5FRSV5VvKgw9Fjyor8kMblkeA4U GRRsImEm3/vacsuN0ZlnknWhkZpeomOm2+FoUIPKgsRK0sYXdFBAB1vtBwOqu8kRND0o Pck4QpBMn87CudPWThl5glPUHdw0Coxgq8XGZpnMN65oBjZ2yYhdHB4pneXQUGGvMfSl o4ZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=CpC+VtE7S33sT1Hdq2TiErLR6SNR00Jn9wFnQN1e6KQ=; b=hrbj+zc9GBNc9gjuxtBvYWq9Pm4UB+C+PC+pmYKNBZcgUMPUU4+pGGUlPfIAqZSRdJ XllgX5Bq45JBwqfSvzM9xidNujRmESGM5oWQWoiCuoGuauA8SaFLqR5KVwwLRREOP1Bi xfr7byy9tbAJibA2pluPX8oHMKKZjk2JdnnQC1jq/gd0kEj2+EIasnILBK1xoQRZFu3s JMj/0CHM+2N7B379kE9cmQqlqnMMxFDta8P5C2705uxixGrtQXBEdtf2+c2d7CBujrR0 vu35BGuoVqSIUdP885YbS3yJHZlT1zhQWdraD8h+l7ADsBeHv0PErmgc5+iYa8KUKQsn nz1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iwltIlSJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id c16-20020a624e10000000b0050dc7628142sm7721788pfb.28.2022.05.23.13.47.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 13:47:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 02/18] target/arm: Use arm_current_el for simple exceptions Date: Mon, 23 May 2022 13:47:26 -0700 Message-Id: <20220523204742.740932-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220523204742.740932-1-richard.henderson@linaro.org> References: <20220523204742.740932-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For these cases, the syndrome does not depend on the origin or target EL, so we can simply defer selection of the target EL to raise_exception. Signed-off-by: Richard Henderson --- target/arm/helper-a64.c | 5 +++-- target/arm/helper.c | 10 +++------- target/arm/mte_helper.c | 7 +++---- target/arm/op_helper.c | 13 ++++++------- 4 files changed, 15 insertions(+), 20 deletions(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 77a8502b6b..22db213aab 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -70,12 +70,13 @@ static void daif_check(CPUARMState *env, uint32_t op, uint32_t imm, uintptr_t ra) { /* DAIF update to PSTATE. This is OK from EL0 only if UMA is set. */ - if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) { + int el = arm_current_el(env); + if (el == 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) { raise_exception_ra(env, EXCP_UDEF, syn_aa64_sysregtrap(0, extract32(op, 0, 3), extract32(op, 3, 3), 4, imm, 0x1f, 0), - exception_target_el(env), ra); + el, ra); } } diff --git a/target/arm/helper.c b/target/arm/helper.c index 40da63913c..e0be96b988 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3232,14 +3232,10 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, * Synchronous external aborts during a translation table walk * are taken as Data Abort exceptions. */ - if (fi.stage2) { - if (current_el == 3) { - target_el = 3; - } else { - target_el = 2; - } + if (fi.stage2 && current_el < 2) { + target_el = 2; } else { - target_el = exception_target_el(env); + target_el = current_el; } take_exc = true; } diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index d11a8c70d0..98f2a3215d 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -540,14 +540,13 @@ void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val) static void mte_sync_check_fail(CPUARMState *env, uint32_t desc, uint64_t dirty_ptr, uintptr_t ra) { - int is_write, syn; + int is_write, syn, el = arm_current_el(env); env->exception.vaddress = dirty_ptr; is_write = FIELD_EX32(desc, MTEDESC, WRITE); - syn = syn_data_abort_no_iss(arm_current_el(env) != 0, 0, 0, 0, 0, is_write, - 0x11); - raise_exception_ra(env, EXCP_DATA_ABORT, syn, exception_target_el(env), ra); + syn = syn_data_abort_no_iss(el != 0, 0, 0, 0, 0, is_write, 0x11); + raise_exception_ra(env, EXCP_DATA_ABORT, syn, el, ra); g_assert_not_reached(); } diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 6b9141b79a..61e9c1d903 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -503,7 +503,7 @@ uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) * Other UNPREDICTABLE and UNDEF cases were caught at translate time. */ raise_exception(env, EXCP_UDEF, syn_uncategorized(), - exception_target_el(env)); + arm_current_el(env)); } if ((env->uncached_cpsr & CPSR_M) == mode) { @@ -567,8 +567,7 @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode, return; undef: - raise_exception(env, EXCP_UDEF, syn_uncategorized(), - exception_target_el(env)); + raise_exception(env, EXCP_UDEF, syn_uncategorized(), arm_current_el(env)); } void HELPER(msr_banked)(CPUARMState *env, uint32_t value, uint32_t tgtmode, @@ -697,7 +696,7 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome, target_el = res & CP_ACCESS_EL_MASK; switch (target_el) { case 0: - target_el = exception_target_el(env); + target_el = arm_current_el(env); break; case 2: assert(arm_current_el(env) != 3); @@ -808,7 +807,7 @@ void HELPER(pre_hvc)(CPUARMState *env) if (undef) { raise_exception(env, EXCP_UDEF, syn_uncategorized(), - exception_target_el(env)); + arm_current_el(env)); } } @@ -870,7 +869,7 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) * This handles the very last line of the previous table. */ raise_exception(env, EXCP_UDEF, syn_uncategorized(), - exception_target_el(env)); + arm_current_el(env)); } if (cur_el == 1 && (arm_hcr_el2_eff(env) & HCR_TSC)) { @@ -889,7 +888,7 @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome) if (!arm_is_psci_call(cpu, EXCP_SMC) && (smd || !arm_feature(env, ARM_FEATURE_EL3))) { raise_exception(env, EXCP_UDEF, syn_uncategorized(), - exception_target_el(env)); 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id c16-20020a624e10000000b0050dc7628142sm7721788pfb.28.2022.05.23.13.47.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 13:47:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 03/18] target/arm: Move and expand parameters to exception_target_el Date: Mon, 23 May 2022 13:47:27 -0700 Message-Id: <20220523204742.740932-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220523204742.740932-1-richard.henderson@linaro.org> References: <20220523204742.740932-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move exception_target_el out of line. Add cur_el parameter, because 2 of 3 users already have that handy. Add psyn parameter in preparation for more code movement. Signed-off-by: Richard Henderson --- target/arm/internals.h | 15 +-------------- target/arm/op_helper.c | 17 ++++++++++++++++- target/arm/tlb_helper.c | 10 ++++++---- 3 files changed, 23 insertions(+), 19 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 03363b0f32..a71f795628 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1091,20 +1091,7 @@ typedef struct ARMVAParameters { ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data); -static inline int exception_target_el(CPUARMState *env) -{ - int target_el = MAX(1, arm_current_el(env)); - - /* - * No such thing as secure EL1 if EL3 is aarch32, - * so update the target EL to EL3 in this case. - */ - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { - target_el = 3; - } - - return target_el; -} +int exception_target_el(CPUARMState *env, int cur_el, uint32_t *psyn); /* Determine if allocation tags are available. */ static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 61e9c1d903..6858b8980d 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -28,6 +28,21 @@ #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) +int exception_target_el(CPUARMState *env, int cur_el, uint32_t *psyn) +{ + int target_el = MAX(1, cur_el); + + /* + * No such thing as secure EL1 if EL3 is aarch32, + * so update the target EL to EL3 in this case. + */ + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { + target_el = 3; + } + + return target_el; +} + void raise_exception(CPUARMState *env, uint32_t excp, uint32_t syndrome, uint32_t cur_or_target_el) { @@ -35,7 +50,7 @@ void raise_exception(CPUARMState *env, uint32_t excp, uint32_t syndrome, int target_el = cur_or_target_el; if (cur_or_target_el == 0) { - target_el = exception_target_el(env); + target_el = exception_target_el(env, 0, &syndrome); } if (target_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 6421e16202..573e18f830 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -85,11 +85,13 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, int mmu_idx, ARMMMUFaultInfo *fi) { CPUARMState *env = &cpu->env; - int target_el; + int cur_el, target_el; bool same_el; uint32_t syn, exc, fsr, fsc; - target_el = exception_target_el(env); + cur_el = arm_current_el(env); + target_el = exception_target_el(env, cur_el, NULL); + if (fi->stage2) { target_el = 2; env->cp15.hpfar_el2 = extract64(fi->s2addr, 12, 47) << 4; @@ -97,7 +99,7 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, env->cp15.hpfar_el2 |= HPFAR_NS; } } - same_el = (arm_current_el(env) == target_el); + same_el = cur_el == target_el; fsr = compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); @@ -139,7 +141,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc) { ARMMMUFaultInfo fi = { .type = ARMFault_Alignment }; - int target_el = exception_target_el(env); + int target_el = exception_target_el(env, arm_current_el(env), NULL); int mmu_idx = cpu_mmu_index(env, true); uint32_t fsc; From patchwork Mon May 23 20:47:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 575406 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:c603:0:0:0:0 with SMTP id jv3csp1728936mab; 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id c16-20020a624e10000000b0050dc7628142sm7721788pfb.28.2022.05.23.13.47.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 13:47:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 04/18] target/arm: Move HCR_TGE check into exception_target_el Date: Mon, 23 May 2022 13:47:28 -0700 Message-Id: <20220523204742.740932-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220523204742.740932-1-richard.henderson@linaro.org> References: <20220523204742.740932-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the TGE test from raise_exception into exception_target_el to consolidate tests in one place. Note that this ought to apply only to origin of EL0, but that cannot be confirmed at this time. Update the AdvSIMDFPAccessTrap doc reference to DDI0478H.a. Signed-off-by: Richard Henderson --- target/arm/op_helper.c | 47 +++++++++++++++++++++++++----------------- 1 file changed, 28 insertions(+), 19 deletions(-) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 6858b8980d..55440dfa84 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -30,17 +30,39 @@ int exception_target_el(CPUARMState *env, int cur_el, uint32_t *psyn) { - int target_el = MAX(1, cur_el); + /* + * FIXME: The following tests really apply to an EL0 origin, + * not to a target of EL1. However, the origin will never be + * EL1 for these cases (no aa32 secure EL1, can't enter EL1 + * with TGE set). Delay fixing this until all places that + * might perform MAX(cur_el, 1) are audited. + */ + if (cur_el >= 2) { + return 2; + } /* * No such thing as secure EL1 if EL3 is aarch32, * so update the target EL to EL3 in this case. */ - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { - target_el = 3; + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { + return 3; } - return target_el; + if (arm_hcr_el2_eff(env) & HCR_TGE) { + /* + * Redirect NS EL1 exceptions to NS EL2. These are reported with + * their original syndrome register value, with the exception of + * SIMD/FP access traps, which are reported as uncategorized + * (see DDI0487 H.a rule RJNBTN). + */ + if (psyn && syn_get_ec(*psyn) == EC_ADVSIMDFPACCESSTRAP) { + *psyn = syn_uncategorized(); + } + return 2; + } + + return 1; } void raise_exception(CPUARMState *env, uint32_t excp, uint32_t syndrome, @@ -49,21 +71,8 @@ void raise_exception(CPUARMState *env, uint32_t excp, uint32_t syndrome, CPUState *cs = env_cpu(env); int target_el = cur_or_target_el; - if (cur_or_target_el == 0) { - target_el = exception_target_el(env, 0, &syndrome); - } - - if (target_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) { - /* - * Redirect NS EL1 exceptions to NS EL2. These are reported with - * their original syndrome register value, with the exception of - * SIMD/FP access traps, which are reported as uncategorized - * (see DDI0478C.a D1.10.4) - */ - target_el = 2; - if (syn_get_ec(syndrome) == EC_ADVSIMDFPACCESSTRAP) { - syndrome = syn_uncategorized(); - } + if (cur_or_target_el <= 1) { + target_el = exception_target_el(env, cur_or_target_el, &syndrome); } assert(!excp_is_internal(excp)); From patchwork Mon May 23 20:47:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 575405 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:c603:0:0:0:0 with SMTP id jv3csp1727821mab; Mon, 23 May 2022 13:51:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwjbSNc1xX14Dqef3EVOJEVDoSGtzgNW2+2gAhm88XANxGuNI29JHVfX/77tXw8dSdE9IoY X-Received: by 2002:ac8:5982:0:b0:2f3:b838:cdda with SMTP id e2-20020ac85982000000b002f3b838cddamr17868707qte.119.1653339088819; Mon, 23 May 2022 13:51:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653339088; cv=none; d=google.com; s=arc-20160816; b=Zf+90h6unybJ7Lqerxy5a52xdjV5YGdRYadkskMnOjXQsqvLh2oLBy6CMaphZlBcKW 3BQm8kxJVoPomlk0Fc6TjKAFOaIYGee+0h/tZ0iQMp1iCL8j5TBEXqExYR/hy1LJVEHM 8Z9MFX14j+HRhhxUWiSOg2LWBbJ4fn04FfBnk/RC2pZLaiZJD0UaOw2LXO+/PGU8MhGy vhVwhreKWr9ZMXAAs3+5YvlUSLkm9Kfp715BQmVKwmunOQDM2X4Xbf3d/vLnmswmAG/k nipJe4WmmHpCeQUJPLDORfLQIjoXWREXoFEXMKea/jL5oYeMsXd4DYWkgDdsB3LvOlOo knkw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=vy83GOBaz0c9nFoZWpk3k7JL3LGlXb9nxH3dH76w/MM=; b=AzI7V7r8esoT1bEq+bjSYzRYquHKcIZYNo0/Z0jM7wJfNWHS7e2t28oNCoKtUrbNT7 vGSc27peOUC/mEVEA5e7vBIAzPSZA4BG5pVEKDbh1VhHZaJavIAIFO3a5xhaFK4RmPKu H5WqyAYn0aoqlWbYCpd4WIoeXNDwBd0L4872z62pPNEZU/deiOTLnX/DUYBnnxJNk2fH Rkuww51V8nB5dsHXr306xAvYMN+t/y8Ok1ItGd04YIMVOjZRAT8iAPuX8P66k1WVmBee iL+j87j0UxcLV8XuVvwkuFnmu4YImSfhX8FJwbDsOiaCushnFInccHm7qNpeHdskvuLb QeMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tvh5ypp1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id c16-20020a624e10000000b0050dc7628142sm7721788pfb.28.2022.05.23.13.47.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 13:47:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 05/18] target/arm: Move arm_singlestep_active out of line Date: Mon, 23 May 2022 13:47:29 -0700 Message-Id: <20220523204742.740932-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220523204742.740932-1-richard.henderson@linaro.org> References: <20220523204742.740932-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the function to debug_helper.c, and the declaration to internals.h. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 10 ---------- target/arm/internals.h | 1 + target/arm/debug_helper.c | 12 ++++++++++++ 3 files changed, 13 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c1865ad5da..2e115a0281 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3087,16 +3087,6 @@ static inline bool arm_generate_debug_exceptions(CPUARMState *env) } } -/* Is single-stepping active? (Note that the "is EL_D AArch64?" check - * implicitly means this always returns false in pre-v8 CPUs.) - */ -static inline bool arm_singlestep_active(CPUARMState *env) -{ - return extract32(env->cp15.mdscr_el1, 0, 1) - && arm_el_is_aa64(env, arm_debug_target_el(env)) - && arm_generate_debug_exceptions(env); -} - static inline bool arm_sctlr_b(CPUARMState *env) { return diff --git a/target/arm/internals.h b/target/arm/internals.h index a71f795628..b447d850ae 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1317,5 +1317,6 @@ void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); #endif void aa32_max_features(ARMCPU *cpu); +bool arm_singlestep_active(CPUARMState *env); #endif diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 46893697cc..1abf41c5f8 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -11,6 +11,18 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" + +/* + * Is single-stepping active? (Note that the "is EL_D AArch64?" check + * implicitly means this always returns false in pre-v8 CPUs.) + */ +bool arm_singlestep_active(CPUARMState *env) +{ + return extract32(env->cp15.mdscr_el1, 0, 1) + && arm_el_is_aa64(env, arm_debug_target_el(env)) + && arm_generate_debug_exceptions(env); +} + /* Return true if the linked breakpoint entry lbn passes its checks */ static bool linked_bp_matches(ARMCPU *cpu, int lbn) { From patchwork Mon May 23 20:47:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 575411 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:c603:0:0:0:0 with SMTP id jv3csp1733112mab; Mon, 23 May 2022 14:00:59 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwV/Gg6/2BQQCt2/5nRuDgvFZ93Q7T4Z1eXwzmpGITnWEgZhnUxeLZQp1sMvpZz7sPgyppM X-Received: by 2002:a05:6214:e6b:b0:45b:1ea:74d9 with SMTP id jz11-20020a0562140e6b00b0045b01ea74d9mr18920651qvb.22.1653339659085; Mon, 23 May 2022 14:00:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653339659; cv=none; d=google.com; s=arc-20160816; b=rDRsPRCTFXIHMYBSaDykEDWI9NFgoEqg1OcO1+Hc9tMenDRB0ez9yrvJtYsMihg8ld +RAqU0yGVaJS4h3p4aRvPOymC2JIW2KSnZeFPIFtI9tPtcnO9BnDMKeTTEIKS2LIYQBY uE24JwmkTnr2+/sOUWwsqtlda/1rHJoonAiZJd/RNqS8/v9gyhoBeevnWeq+qa/uD5zP LFtfvZhu3xs9RAIA5V8S2nuydK1VER7xz1jSqXtpu0aXmbks09i5lqTJm5/aYkXp9uFJ tm4lJ8tQcPZr7cg/FnBeFzOFK/ocpqESKB/N+1XT3sHamMFIMx2m4++vlpQNmQ5lqx3E RjRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=q+QZhQErKHUIz5Yukzx015BIaa2BxFp+5FYfWrFDsdE=; b=dDeBCqAv4bDZrWt/gaAr0fCs0C1nAFYouq8I5hPKfKxFgIcO91l8lj2GIcDHmA+25K CRit7XECcJ0w9z1dJ4CQDNxyaHyNl7u9Z8IxDCTxKkGOz3gfZ+K7E2ul/DydBLGNU6GU btaxJYo0V8Mx4bcvocUFKpdy93F4ljKws02uCd1jxupgVMjndl8R/7M2C7FA5KfRSMdJ Qqcw5I+kPaBR16t7Z8jNv9iLk5YaV3D+g8wCYAtciWrfrXUogX6zH+6VhctyYPoGzXDE ik8VFGqwKorlbSipwaBY7GNIxFuTE/DZwM6MoAxwl4WTE/dO2+yq8van95YUAu8ArgP3 IG/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="qsG06/1Y"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id c16-20020a624e10000000b0050dc7628142sm7721788pfb.28.2022.05.23.13.47.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 13:47:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 06/18] target/arm: Move arm_generate_debug_exceptions out of line Date: Mon, 23 May 2022 13:47:30 -0700 Message-Id: <20220523204742.740932-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220523204742.740932-1-richard.henderson@linaro.org> References: <20220523204742.740932-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move arm_generate_debug_exceptions and its two subroutines, {aa32,aa64}_generate_debug_exceptions into debug_helper.c, and the one interface declaration to internals.h. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 91 ------------------------------------- target/arm/internals.h | 1 + target/arm/debug_helper.c | 94 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 95 insertions(+), 91 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2e115a0281..92c9758e86 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2996,97 +2996,6 @@ static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) return (cpu->clidr & R_V7M_CLIDR_CTYPE_ALL_MASK) != 0; } -/* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ -static inline bool aa64_generate_debug_exceptions(CPUARMState *env) -{ - int cur_el = arm_current_el(env); - int debug_el; - - if (cur_el == 3) { - return false; - } - - /* MDCR_EL3.SDD disables debug events from Secure state */ - if (arm_is_secure_below_el3(env) - && extract32(env->cp15.mdcr_el3, 16, 1)) { - return false; - } - - /* - * Same EL to same EL debug exceptions need MDSCR_KDE enabled - * while not masking the (D)ebug bit in DAIF. - */ - debug_el = arm_debug_target_el(env); - - if (cur_el == debug_el) { - return extract32(env->cp15.mdscr_el1, 13, 1) - && !(env->daif & PSTATE_D); - } - - /* Otherwise the debug target needs to be a higher EL */ - return debug_el > cur_el; -} - -static inline bool aa32_generate_debug_exceptions(CPUARMState *env) -{ - int el = arm_current_el(env); - - if (el == 0 && arm_el_is_aa64(env, 1)) { - return aa64_generate_debug_exceptions(env); - } - - if (arm_is_secure(env)) { - int spd; - - if (el == 0 && (env->cp15.sder & 1)) { - /* SDER.SUIDEN means debug exceptions from Secure EL0 - * are always enabled. Otherwise they are controlled by - * SDCR.SPD like those from other Secure ELs. - */ - return true; - } - - spd = extract32(env->cp15.mdcr_el3, 14, 2); - switch (spd) { - case 1: - /* SPD == 0b01 is reserved, but behaves as 0b00. */ - case 0: - /* For 0b00 we return true if external secure invasive debug - * is enabled. On real hardware this is controlled by external - * signals to the core. QEMU always permits debug, and behaves - * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. - */ - return true; - case 2: - return false; - case 3: - return true; - } - } - - return el != 2; -} - -/* Return true if debugging exceptions are currently enabled. - * This corresponds to what in ARM ARM pseudocode would be - * if UsingAArch32() then - * return AArch32.GenerateDebugExceptions() - * else - * return AArch64.GenerateDebugExceptions() - * We choose to push the if() down into this function for clarity, - * since the pseudocode has it at all callsites except for the one in - * CheckSoftwareStep(), where it is elided because both branches would - * always return the same value. - */ -static inline bool arm_generate_debug_exceptions(CPUARMState *env) -{ - if (env->aarch64) { - return aa64_generate_debug_exceptions(env); - } else { - return aa32_generate_debug_exceptions(env); - } -} - static inline bool arm_sctlr_b(CPUARMState *env) { return diff --git a/target/arm/internals.h b/target/arm/internals.h index b447d850ae..91702b3ff7 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1318,5 +1318,6 @@ void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); void aa32_max_features(ARMCPU *cpu); bool arm_singlestep_active(CPUARMState *env); +bool arm_generate_debug_exceptions(CPUARMState *env); #endif diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 1abf41c5f8..20a0e4261a 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -12,6 +12,100 @@ #include "exec/helper-proto.h" +/* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ +static bool aa64_generate_debug_exceptions(CPUARMState *env) +{ + int cur_el = arm_current_el(env); + int debug_el; + + if (cur_el == 3) { + return false; + } + + /* MDCR_EL3.SDD disables debug events from Secure state */ + if (arm_is_secure_below_el3(env) + && extract32(env->cp15.mdcr_el3, 16, 1)) { + return false; + } + + /* + * Same EL to same EL debug exceptions need MDSCR_KDE enabled + * while not masking the (D)ebug bit in DAIF. + */ + debug_el = arm_debug_target_el(env); + + if (cur_el == debug_el) { + return extract32(env->cp15.mdscr_el1, 13, 1) + && !(env->daif & PSTATE_D); + } + + /* Otherwise the debug target needs to be a higher EL */ + return debug_el > cur_el; +} + +static bool aa32_generate_debug_exceptions(CPUARMState *env) +{ + int el = arm_current_el(env); + + if (el == 0 && arm_el_is_aa64(env, 1)) { + return aa64_generate_debug_exceptions(env); + } + + if (arm_is_secure(env)) { + int spd; + + if (el == 0 && (env->cp15.sder & 1)) { + /* + * SDER.SUIDEN means debug exceptions from Secure EL0 + * are always enabled. Otherwise they are controlled by + * SDCR.SPD like those from other Secure ELs. + */ + return true; + } + + spd = extract32(env->cp15.mdcr_el3, 14, 2); + switch (spd) { + case 1: + /* SPD == 0b01 is reserved, but behaves as 0b00. */ + case 0: + /* + * For 0b00 we return true if external secure invasive debug + * is enabled. On real hardware this is controlled by external + * signals to the core. QEMU always permits debug, and behaves + * as if DBGEN, SPIDEN, NIDEN and SPNIDEN are all tied high. + */ + return true; + case 2: + return false; + case 3: + return true; + } + } + + return el != 2; +} + +/* + * Return true if debugging exceptions are currently enabled. + * This corresponds to what in ARM ARM pseudocode would be + * if UsingAArch32() then + * return AArch32.GenerateDebugExceptions() + * else + * return AArch64.GenerateDebugExceptions() + * We choose to push the if() down into this function for clarity, + * since the pseudocode has it at all callsites except for the one in + * CheckSoftwareStep(), where it is elided because both branches would + * always return the same value. + */ +bool arm_generate_debug_exceptions(CPUARMState *env) +{ + if (env->aarch64) { + return aa64_generate_debug_exceptions(env); + } else { + return aa32_generate_debug_exceptions(env); + } +} + /* * Is single-stepping active? (Note that the "is EL_D AArch64?" check * implicitly means this always returns false in pre-v8 CPUs.) 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id c16-20020a624e10000000b0050dc7628142sm7721788pfb.28.2022.05.23.13.47.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 13:47:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 07/18] target/arm: Hoist arm_current_el in arm_generate_debug_exceptions Date: Mon, 23 May 2022 13:47:31 -0700 Message-Id: <20220523204742.740932-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220523204742.740932-1-richard.henderson@linaro.org> References: <20220523204742.740932-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Read this value once in the main function, and pass it around between the subroutines. Signed-off-by: Richard Henderson --- target/arm/debug_helper.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 20a0e4261a..2bbf065b3a 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -13,9 +13,8 @@ /* See AArch64.GenerateDebugExceptionsFrom() in ARM ARM pseudocode */ -static bool aa64_generate_debug_exceptions(CPUARMState *env) +static bool aa64_generate_debug_exceptions(CPUARMState *env, int cur_el) { - int cur_el = arm_current_el(env); int debug_el; if (cur_el == 3) { @@ -43,18 +42,16 @@ static bool aa64_generate_debug_exceptions(CPUARMState *env) return debug_el > cur_el; } -static bool aa32_generate_debug_exceptions(CPUARMState *env) +static bool aa32_generate_debug_exceptions(CPUARMState *env, int cur_el) { - int el = arm_current_el(env); - - if (el == 0 && arm_el_is_aa64(env, 1)) { - return aa64_generate_debug_exceptions(env); + if (cur_el == 0 && arm_el_is_aa64(env, 1)) { + return aa64_generate_debug_exceptions(env, cur_el); } if (arm_is_secure(env)) { int spd; - if (el == 0 && (env->cp15.sder & 1)) { + if (cur_el == 0 && (env->cp15.sder & 1)) { /* * SDER.SUIDEN means debug exceptions from Secure EL0 * are always enabled. Otherwise they are controlled by @@ -82,7 +79,7 @@ static bool aa32_generate_debug_exceptions(CPUARMState *env) } } - return el != 2; + return cur_el != 2; } /* @@ -99,10 +96,12 @@ static bool aa32_generate_debug_exceptions(CPUARMState *env) */ bool arm_generate_debug_exceptions(CPUARMState *env) { + int cur_el = arm_current_el(env); + if (env->aarch64) { - return aa64_generate_debug_exceptions(env); + return aa64_generate_debug_exceptions(env, cur_el); } else { - return aa32_generate_debug_exceptions(env); + return aa32_generate_debug_exceptions(env, cur_el); } } From patchwork Mon May 23 20:47:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 575414 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:c603:0:0:0:0 with SMTP id jv3csp1737821mab; Mon, 23 May 2022 14:07:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxth5AWDvJBselaAj7517nJUs89WVU5aHRuXl7x1UgPDEiRIyXEcPmjnflEOJAtksYDc1OI X-Received: by 2002:a37:a4c2:0:b0:6a3:4299:ba69 with SMTP id n185-20020a37a4c2000000b006a34299ba69mr12965330qke.493.1653340025844; Mon, 23 May 2022 14:07:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653340025; cv=none; d=google.com; s=arc-20160816; b=IGqcQeSzwB3VH12oItNOn1vaMprMbMU5YrE977l8kxShASC2VF03JbPWR56Z4edgB5 y6MHOvBn7CONdiEh7AGFx/QdPEqqpXUmZffgjqVqFiDV2pcPgNHOa2zpH+zmQpHgUZjw K3y3aVdgjqYCjb3ADxD5F167i6+v0gwRVUWXniTCop+1IqflCb1A4WFj17O9btrdzHos aL8VAiSUn3z8vTwWWlPe2nGf7meZ9gwsA3IDYO5nLkHJxcF7s12eQZKUzxNv70LhLN9L N/KmMQZOIM1MmUOABTcqn65FNJf7HYg0ErNP/xesE0rcdEPY5G5DDiQJLZVLt3HJB8ht 5tog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Dt8CbxTVDB+ShnUD/KaNguE181rKbT/m4QnA7xOaLPg=; b=YmYiZX3+sWwyETG5kIEbtqarYqPrWMNSAy2lHW2S3OHWZSzg7FmDCJMwg2dIPiJe1x D/s3dFo/LijlMMuybISsX4o7hYTYVsCi5V/JgkLFkVYn2WE4NgJMzAjlP3yXiiYx2TWc 8sTNK4mMCPGLQvmkcWFXa1NuOKTXYy/ezjUh5Jk01V5Ks5ISuDHQHWynNt7I+myNbOL/ i0jabnpTHe4Hfp93PWzUR3pGpN80RTc8h5RAe8nAntFYJY2du46O2m2OaHMbWGPuPbKR d1IDstKBJw0soHOkDynJMpmBEa+Vq5hjle8CtbRbY20HWvFzOOjyYK3gdnb7a9YEvPRz SlnQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fG4pX36Y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id c16-20020a624e10000000b0050dc7628142sm7721788pfb.28.2022.05.23.13.47.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 13:47:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 08/18] target/arm: Use is_a64 in arm_generate_debug_exceptions Date: Mon, 23 May 2022 13:47:32 -0700 Message-Id: <20220523204742.740932-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220523204742.740932-1-richard.henderson@linaro.org> References: <20220523204742.740932-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Use the accessor rather than the raw structure member. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/debug_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 2bbf065b3a..3a86901779 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -98,7 +98,7 @@ bool arm_generate_debug_exceptions(CPUARMState *env) { int cur_el = arm_current_el(env); - if (env->aarch64) { + if (is_a64(env)) { return aa64_generate_debug_exceptions(env, cur_el); } else { return aa32_generate_debug_exceptions(env, cur_el); From patchwork Mon May 23 20:47:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 575408 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:c603:0:0:0:0 with SMTP id jv3csp1730336mab; Mon, 23 May 2022 13:56:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzt+19itUPeKl3jZiCru++dbsOO66+0pzuJmpmBl8q8mpi95DtEXW4j93DU/NEwq6bi8Fdo X-Received: by 2002:a05:622a:190f:b0:2f6:61bf:ba38 with SMTP id w15-20020a05622a190f00b002f661bfba38mr17761049qtc.71.1653339361048; Mon, 23 May 2022 13:56:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653339361; cv=none; d=google.com; s=arc-20160816; b=CrZ8MRVBeDxtQrAWq8Lznz+2gnEdwtE9q7UpJWcPxQ0MzmLy2Gi/zYaNiRjrtyUOMo se3z1omPTaiaGJzFFvqrxN2PtNDfqZgH8+pcKHIr5NmiOjKIo9oaVx2l+biXpDmdANQI zn+ayw+noGmhkdrgY1qwuJ7y86VXITc0l10sCWoHa/sD+gPo8Ezq34EC8JNoqX+WbHwg x75gctNmqPcsBpB5IEh6U4yR6rsUzTWJnsQItsDo5HYpf8YehhW1+NihfLKmBloLP4Ky NQUtN8wWlhFd6vL9+pq81Kzmw2c1groe2fX5Z3Oq5IOw4OPR8OYBIXy3OzBNa1xEbwrW xEmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=EfHC5sh/pejKXX57jmwQUPJC/F0imk6n0vf48RAawTc=; b=ssPZpvOJWFVLB2QHIsOSY3lfh6bbJGmVscB9lAhikJQZp6WSCSrtix5JkKl5QVERn9 tiDK/Qsr1uA5qkXdUnX3OpFd5zpbcXFW41Zj7bv2FsyDvmN9LeADgYBjfBK5ldWj/pkR I5MbN2sqaDjqaGCdvbjj1c2bX5T0ycnYPNuAsXE4w3qZOE0gcxuz0dn6eTMViHoGPFVl XfbuRKSvs2Yift5RwlqWYIZRDPHzXunnxydGl+5eN/28hfhwQgOQDH38cut0ZeyKYMy+ EjGMBzA1OWJdL41tqZQPVUsZRjcwLZ8oVQbvdqoFbW4w9xRbqCyGwGgwFMrK2gSxp2gN 1iLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="eD9YlSJ/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id c16-20020a624e10000000b0050dc7628142sm7721788pfb.28.2022.05.23.13.47.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 13:47:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 09/18] target/arm: Move exception_bkpt_insn to debug_helper.c Date: Mon, 23 May 2022 13:47:33 -0700 Message-Id: <20220523204742.740932-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220523204742.740932-1-richard.henderson@linaro.org> References: <20220523204742.740932-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/debug_helper.c | 31 +++++++++++++++++++++++++++++++ target/arm/op_helper.c | 29 ----------------------------- 2 files changed, 31 insertions(+), 29 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 3a86901779..bdcd5f36d6 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -429,6 +429,37 @@ void arm_debug_excp_handler(CPUState *cs) } } +/* + * Raise an EXCP_BKPT with the specified syndrome register value, + * targeting the correct exception level for debug exceptions. + */ +void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) +{ + int debug_el = arm_debug_target_el(env); + int cur_el = arm_current_el(env); + + /* FSR will only be used if the debug target EL is AArch32. */ + env->exception.fsr = arm_debug_exception_fsr(env); + /* + * FAR is UNKNOWN: clear vaddress to avoid potentially exposing + * values to the guest that it shouldn't be able to see at its + * exception/security level. + */ + env->exception.vaddress = 0; + /* + * Other kinds of architectural debug exception are ignored if + * they target an exception level below the current one (in QEMU + * this is checked by arm_generate_debug_exceptions()). Breakpoint + * instructions are special because they always generate an exception + * to somewhere: if they can't go to the configured debug exception + * level they are taken to the current exception level. + */ + if (debug_el < cur_el) { + debug_el = cur_el; + } + raise_exception(env, EXCP_BKPT, syndrome, debug_el); +} + #if !defined(CONFIG_USER_ONLY) vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 55440dfa84..0a50dbf274 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -413,35 +413,6 @@ void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp, raise_exception(env, excp, syndrome, target_el); } -/* Raise an EXCP_BKPT with the specified syndrome register value, - * targeting the correct exception level for debug exceptions. - */ -void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) -{ - int debug_el = arm_debug_target_el(env); - int cur_el = arm_current_el(env); - - /* FSR will only be used if the debug target EL is AArch32. */ - env->exception.fsr = arm_debug_exception_fsr(env); - /* FAR is UNKNOWN: clear vaddress to avoid potentially exposing - * values to the guest that it shouldn't be able to see at its - * exception/security level. - */ - env->exception.vaddress = 0; - /* - * Other kinds of architectural debug exception are ignored if - * they target an exception level below the current one (in QEMU - * this is checked by arm_generate_debug_exceptions()). Breakpoint - * instructions are special because they always generate an exception - * to somewhere: if they can't go to the configured debug exception - * level they are taken to the current exception level. - */ - if (debug_el < cur_el) { - debug_el = cur_el; - } - raise_exception(env, EXCP_BKPT, syndrome, debug_el); -} - uint32_t HELPER(cpsr_read)(CPUARMState *env) { return cpsr_read(env) & ~CPSR_EXEC; From patchwork Mon May 23 20:47:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 575418 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:c603:0:0:0:0 with SMTP id jv3csp1741457mab; Mon, 23 May 2022 14:12:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy4CI5JrN5dTTDcapOiesgh+P2z3nGno9+kdvAMW4dob4GjsNqsxRK9nlWqx9ZVrTNBGGKj X-Received: by 2002:a05:620a:2052:b0:6a3:5387:6bf5 with SMTP id d18-20020a05620a205200b006a353876bf5mr9923014qka.575.1653340326003; Mon, 23 May 2022 14:12:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653340326; cv=none; d=google.com; s=arc-20160816; b=cyxEMXHeDbowiPd67jqzpFlN2R+N7EaHUknHkZ9A6uTtVH1lLl8stM9orwzGXKrYqx GCBfRTUKFFjjchPGIGpj8zutEuzZHaNnXy9KKPfmgPOLwVgd4WyGOr/+nabOh6kYAqpr USJOsALXQKhLXWooDr7NKe6QaImN70MQCN8VwEzuwah401FAg40wnSxmRVrFhepfaCht wu5uvQeWx4Lj6C2p7vnLcsy8k+xP/nfSs/5ewT61PQt0kUZfNkRsD26bETLDh02kH3K1 5OttsFbX2YbjjMafL5Do9k6m/YuU2rRc/dOj3djML44ffKo2mptVxtFU3NbwZBqcW1xV +ccw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=CpJpY6Zi7IyphD262mZyPHWMPDsMk1fOKGRcuezpDcQ=; b=diO+bQpRyjwLF/bLUvMItfeIC1A3vSgOrjfxJZI4+O/9MpLowPwzVdBqf9nJUsyJP7 gT6CRUuaI5NmJhQd6cLLTJ0cmhM4ywrFlpamrmYKczrymWenb+V1XelDnwxBxbJGx0Iy qcOlZNMuD6BW66m17TxaSGVHdccT6eADOjvvHJYV9YLpZ9jKjoVKIxuJ9R9PFh+AmAHB UnZBXB/gL1C85QIolq+lpOqlPKzqzUVTWpqfoHxszL+Uceu2ol4HG/fFjYKikWMJQgKj 2kz2ohKtt+t0Lt4J7bKYhMQlmsourrhwe/MGE2Uvzx+uXBEqVG8debXB1ssr1RgidTJg eazA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sb3JFY4u; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id c16-20020a624e10000000b0050dc7628142sm7721788pfb.28.2022.05.23.13.47.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 13:47:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 10/18] target/arm: Move arm_debug_exception_fsr to debug_helper.c Date: Mon, 23 May 2022 13:47:34 -0700 Message-Id: <20220523204742.740932-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220523204742.740932-1-richard.henderson@linaro.org> References: <20220523204742.740932-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function now now only used in debug_helper.c, so there is no reason to have a declaration in a header. Signed-off-by: Richard Henderson --- target/arm/internals.h | 25 ------------------------- target/arm/debug_helper.c | 26 ++++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 25 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 91702b3ff7..bb45100f06 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -794,31 +794,6 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) return &env->cp15.tcr_el[regime_el(env, mmu_idx)]; } -/* Return the FSR value for a debug exception (watchpoint, hardware - * breakpoint or BKPT insn) targeting the specified exception level. - */ -static inline uint32_t arm_debug_exception_fsr(CPUARMState *env) -{ - ARMMMUFaultInfo fi = { .type = ARMFault_Debug }; - int target_el = arm_debug_target_el(env); - bool using_lpae = false; - - if (target_el == 2 || arm_el_is_aa64(env, target_el)) { - using_lpae = true; - } else { - if (arm_feature(env, ARM_FEATURE_LPAE) && - (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { - using_lpae = true; - } - } - - if (using_lpae) { - return arm_fi_to_lfsc(&fi); - } else { - return arm_fi_to_sfsc(&fi); - } -} - /** * arm_num_brps: Return number of implemented breakpoints. * Note that the ID register BRPS field is "number of bps - 1", diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index bdcd5f36d6..08d461fd19 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -378,6 +378,32 @@ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) return check_watchpoints(cpu); } +/* + * Return the FSR value for a debug exception (watchpoint, hardware + * breakpoint or BKPT insn) targeting the specified exception level. + */ +static uint32_t arm_debug_exception_fsr(CPUARMState *env) +{ + ARMMMUFaultInfo fi = { .type = ARMFault_Debug }; + int target_el = arm_debug_target_el(env); + bool using_lpae = false; + + if (target_el == 2 || arm_el_is_aa64(env, target_el)) { + using_lpae = true; + } else { + if (arm_feature(env, ARM_FEATURE_LPAE) && + (env->cp15.tcr_el[target_el].raw_tcr & TTBCR_EAE)) { + using_lpae = true; + } + } + + if (using_lpae) { + return arm_fi_to_lfsc(&fi); + } else { + return arm_fi_to_sfsc(&fi); + } +} + void arm_debug_excp_handler(CPUState *cs) { /* From patchwork Mon May 23 20:47:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 575412 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:c603:0:0:0:0 with SMTP id jv3csp1734339mab; Mon, 23 May 2022 14:02:28 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz4fkP+AC3d7ktUkrpICXMO16XNOiK0l+2sVec7DIOZQ3m/C/FfbAiolOLa5HIOHA3njr0B X-Received: by 2002:a37:6548:0:b0:6a3:758b:1c2b with SMTP id z69-20020a376548000000b006a3758b1c2bmr5927279qkb.729.1653339748561; Mon, 23 May 2022 14:02:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653339748; cv=none; d=google.com; s=arc-20160816; b=Qzkd84xUdhTpPycplQ9vzAboQUWnBnhfqeocanwKSqSDrwqtEWCozMoKkQs+V1ZzeB 8E6Vtggs7m/lt3kd3QIQDRkDgpxiX5q7NkPZ6X+aUp+4lrAIdns8gc8q6G1oYpTq5egj /R6fxzkbogfKFwBZiDv4SeUVnIy7D7n+4QoDg7gmB7+mZH0MktKeCbHOfQ0GWF2Vz5et b4Ix1mS20oW247QHu1CzA49lplIHlZ0D27Z1n9Jn2QI5AmmP9x2hrEcRd4logkg3trTD XZL4aZmGBt9WGRLxB1PY+qLkUoyvdT938nWXeQ1hlX1FXLIP/yNmwqCV8ErWkVf8q32s KAFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=3bqX2hAe2Sjw2v5YRDxIGUXWsq30Bbv7KtpnLqEB4zE=; b=fIr+jDr2hzTvRT1MvTtLG6F+7/s437lfrs3CC7t1BGGqhbUNZ9f4b4cgp8d0ioy2+d oa1XhtnUscztgJjqMJeuyd2KHaBeWcXfVm9JOCpFSAjpqxIeAVFxE4SeWxvPX0YHgl2s KdKhoonyxNZGef9Stfyifh6e0SRiYHANfYnUmiCyXGil4tfpDvt7648FDyVwU28drkl9 0wm5B8SjxVqk0qpiu6ZNBRmgZMCCWtFkGJnmTqw9/TraD1QkQpD9nzYKORA9nKdxdPl5 Y/WlqyRVzJR7hdR0BsO4cCOhMop3ADm/V2FxVO5LiK3+mGJ9trn5p7LmMRmha6c35pfW kgDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FYGDDMhS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id c16-20020a624e10000000b0050dc7628142sm7721788pfb.28.2022.05.23.13.47.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 13:47:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 11/18] target/arm: Move arm_debug_target_el to internals.h Date: Mon, 23 May 2022 13:47:35 -0700 Message-Id: <20220523204742.740932-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220523204742.740932-1-richard.henderson@linaro.org> References: <20220523204742.740932-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This function is private to the implementation. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 21 --------------------- target/arm/internals.h | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 92c9758e86..90cdc7b1de 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2967,27 +2967,6 @@ typedef enum ARMASIdx { ARMASIdx_TagS = 3, } ARMASIdx; -/* Return the Exception Level targeted by debug exceptions. */ -static inline int arm_debug_target_el(CPUARMState *env) -{ - bool secure = arm_is_secure(env); - bool route_to_el2 = false; - - if (arm_is_el2_enabled(env)) { - route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || - env->cp15.mdcr_el2 & MDCR_TDE; - } - - if (route_to_el2) { - return 2; - } else if (arm_feature(env, ARM_FEATURE_EL3) && - !arm_el_is_aa64(env, 3) && secure) { - return 3; - } else { - return 1; - } -} - static inline bool arm_v7m_csselr_razwi(ARMCPU *cpu) { /* If all the CLIDR.Ctypem bits are 0 there are no caches, and diff --git a/target/arm/internals.h b/target/arm/internals.h index bb45100f06..685214503b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1068,6 +1068,27 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, int exception_target_el(CPUARMState *env, int cur_el, uint32_t *psyn); +/* Return the Exception Level targeted by debug exceptions. */ +static inline int arm_debug_target_el(CPUARMState *env) +{ + bool secure = arm_is_secure(env); + bool route_to_el2 = false; + + if (arm_is_el2_enabled(env)) { + route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || + env->cp15.mdcr_el2 & MDCR_TDE; + } + + if (route_to_el2) { + return 2; + } else if (arm_feature(env, ARM_FEATURE_EL3) && + !arm_el_is_aa64(env, 3) && secure) { + return 3; + } else { + return 1; + } +} + /* Determine if allocation tags are available. */ static inline bool allocation_tag_access_enabled(CPUARMState *env, int el, uint64_t sctlr) From patchwork Mon May 23 20:47:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 575415 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:c603:0:0:0:0 with SMTP id jv3csp1737994mab; Mon, 23 May 2022 14:07:20 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy4H0/Ft1npnN+yODphzgjdqlPbWcTo0imaHMwfMwJHVw1Y32pdqjDeFRN5EwaZMhZyQsU5 X-Received: by 2002:a05:622a:ca:b0:2f9:3f2c:c463 with SMTP id p10-20020a05622a00ca00b002f93f2cc463mr1350889qtw.386.1653340040074; Mon, 23 May 2022 14:07:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653340040; cv=none; d=google.com; s=arc-20160816; b=gCCo9I6JdfFYN7nwK88lGJSXzt16d8ReEan2hquP8J1BU6ELZEp9rw9+qyNa1HQ45F cfyGjyMyuQ2O1rfnO4+gNR+YY+JoOocTN/AmImYK3JhecWkLjPObgJ87MUTHkiaN2Mp7 05VE/n9IOyfTLDcwKZtUuF760I/5lSZoDlFk+WGqAyxXCkZt7th+gXyV6AtayC+GNLfh DAwlZmJbMwXnEEZTfhjHuOwrhR7rlXZLrHUbsqygJY4IRfmfvaWQ5UWj9pX4E9+AycJC VwuqG0fnonl32GwA/fbjGinqXx70+vAVEh/Nj0SqoC7BMmmIhoZTbQxuxso91gZD7/Fv sKWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=YgXeFZJ++svyGxcNWIu+V+WtRKFzNHxuY5DM2JGZ0B0=; b=UyHNRiLq2ds61TwV/u2Zd5LO9MxH7ualL3pUX/KXe/VJfVERdY6KZwP5oFeiJ4aLbi 52G+YwaTkesgBaj/tingy9UcZZ0r4QUMHZei9JqRnu5PMh/b8PUZesV52tthyfrOTf3G YX/CVXVFHLC83Kw3uarSKQ7gyQ3Fzs9PAPllrRFsMabzQ/h5PiejjhjVOb7A18GAvsJC PQkmX+58mSi7Wys0Q4Pw/FOSVnku7AFzUvSq26PyG2ZCfEEjGKAnabiEbETY9eRfZmZR y7YJ4sV7Rt1SQNA5O50rL8Bgs8mvC9Vr4xnDMadeIbUqj99RPyyF1jqa2E1vxlkq2Go1 TgYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nOpxxtlZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id c16-20020a624e10000000b0050dc7628142sm7721788pfb.28.2022.05.23.13.47.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 13:47:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 12/18] target/arm: Create raise_exception_debug Date: Mon, 23 May 2022 13:47:36 -0700 Message-Id: <20220523204742.740932-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220523204742.740932-1-richard.henderson@linaro.org> References: <20220523204742.740932-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Handle EL testing for debug exceptions in a single place. Split out raise_exception_int as a common helper. Signed-off-by: Richard Henderson --- target/arm/internals.h | 8 ++++++++ target/arm/debug_helper.c | 27 ++++-------------------- target/arm/op_helper.c | 43 ++++++++++++++++++++++++++++++++------- 3 files changed, 48 insertions(+), 30 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 685214503b..6df38db836 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -125,6 +125,14 @@ G_NORETURN void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, uint32_t cur_or_target_el, uintptr_t ra); +/** + * raise_exception_debug: + * Similarly. If @excp != EXCPBKPT, modify syndrome to indicate + * when origin and target EL are the same. + */ +G_NORETURN void raise_exception_debug(CPUARMState *env, uint32_t excp, + uint32_t syndrome); + /* * For AArch64, map a given EL to an index in the banked_spsr array. * Note that this mapping and the AArch32 mapping defined in bank_number() diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 08d461fd19..181ba7b042 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -417,19 +417,16 @@ void arm_debug_excp_handler(CPUState *cs) if (wp_hit) { if (wp_hit->flags & BP_CPU) { bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0; - bool same_el = arm_debug_target_el(env) == arm_current_el(env); cs->watchpoint_hit = NULL; env->exception.fsr = arm_debug_exception_fsr(env); env->exception.vaddress = wp_hit->hitaddr; - raise_exception(env, EXCP_DATA_ABORT, - syn_watchpoint(same_el, 0, wnr), - arm_debug_target_el(env)); + raise_exception_debug(env, EXCP_DATA_ABORT, + syn_watchpoint(0, 0, wnr)); } } else { uint64_t pc = is_a64(env) ? env->pc : env->regs[15]; - bool same_el = (arm_debug_target_el(env) == arm_current_el(env)); /* * (1) GDB breakpoints should be handled first. @@ -449,9 +446,7 @@ void arm_debug_excp_handler(CPUState *cs) * exception/security level. */ env->exception.vaddress = 0; - raise_exception(env, EXCP_PREFETCH_ABORT, - syn_breakpoint(same_el), - arm_debug_target_el(env)); + raise_exception_debug(env, EXCP_PREFETCH_ABORT, syn_breakpoint(0)); } } @@ -461,9 +456,6 @@ void arm_debug_excp_handler(CPUState *cs) */ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) { - int debug_el = arm_debug_target_el(env); - int cur_el = arm_current_el(env); - /* FSR will only be used if the debug target EL is AArch32. */ env->exception.fsr = arm_debug_exception_fsr(env); /* @@ -472,18 +464,7 @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) * exception/security level. */ env->exception.vaddress = 0; - /* - * Other kinds of architectural debug exception are ignored if - * they target an exception level below the current one (in QEMU - * this is checked by arm_generate_debug_exceptions()). Breakpoint - * instructions are special because they always generate an exception - * to somewhere: if they can't go to the configured debug exception - * level they are taken to the current exception level. - */ - if (debug_el < cur_el) { - debug_el = cur_el; - } - raise_exception(env, EXCP_BKPT, syndrome, debug_el); + raise_exception_debug(env, EXCP_BKPT, syndrome); } #if !defined(CONFIG_USER_ONLY) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 0a50dbf274..c4988b6c41 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -65,15 +65,11 @@ int exception_target_el(CPUARMState *env, int cur_el, uint32_t *psyn) return 1; } -void raise_exception(CPUARMState *env, uint32_t excp, uint32_t syndrome, - uint32_t cur_or_target_el) +G_NORETURN static +void raise_exception_int(CPUARMState *env, uint32_t excp, + uint32_t syndrome, uint32_t target_el) { CPUState *cs = env_cpu(env); - int target_el = cur_or_target_el; - - if (cur_or_target_el <= 1) { - target_el = exception_target_el(env, cur_or_target_el, &syndrome); - } assert(!excp_is_internal(excp)); cs->exception_index = excp; @@ -82,6 +78,39 @@ void raise_exception(CPUARMState *env, uint32_t excp, uint32_t syndrome, cpu_loop_exit(cs); } +void raise_exception(CPUARMState *env, uint32_t excp, uint32_t syndrome, + uint32_t cur_or_target_el) +{ + int target_el = cur_or_target_el; + if (cur_or_target_el <= 1) { + target_el = exception_target_el(env, cur_or_target_el, &syndrome); + } + raise_exception_int(env, excp, syndrome, target_el); +} + +void raise_exception_debug(CPUARMState *env, uint32_t excp, uint32_t syndrome) +{ + int cur_el = arm_current_el(env); + int debug_el = arm_debug_target_el(env); + + /* + * Most kinds of architectural debug exception are ignored if + * they target an exception level below the current (in QEMU + * this is checked by arm_generate_debug_exceptions()). + * Breakpoint instructions are special because they always generate + * an exception to somewhere: if they can't go to the configured + * debug exception level they are taken to the current exception level. + */ + if (excp == EXCP_BKPT) { + debug_el = MAX(cur_el, debug_el); + } else { + assert(debug_el >= cur_el); + syndrome |= (debug_el == cur_el) << ARM_EL_EC_SHIFT; + } + + raise_exception_int(env, excp, syndrome, debug_el); +} + void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, uint32_t cur_or_target_el, uintptr_t ra) { From patchwork Mon May 23 20:47:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 575420 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:c603:0:0:0:0 with SMTP id jv3csp1746147mab; Mon, 23 May 2022 14:19:30 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyfFKTWvnSLMZ2708NEpJKiDzcmpMahK3jLLt2Rmczk8WWHsg5uV0zE/Z6P7Y5W2SDkKSyy X-Received: by 2002:a05:622a:311:b0:2f3:ddb0:4ae6 with SMTP id q17-20020a05622a031100b002f3ddb04ae6mr18115485qtw.140.1653340770273; Mon, 23 May 2022 14:19:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653340770; cv=none; d=google.com; s=arc-20160816; b=KLGHpgVft4SfKIbbntNgXVxYLwQYL2L71Da4CCrQCPa7BezBjsKvrVNwSZizlrpmvA AnmgpHCCUJb7ZFmGrpeMxwtcM1GDN2e7bSua7hM5nwfnngHOylho9cU8HW4mgmxxc1+R 4z5Ywnvd/VM8yIcq2ucKCrUosDob1wnnfEgXHWv+B0C2Dh4dIExtPZDo/+D85FeurHO4 agyLN/y8yMFzEeywqkYtN7LQJWYUf6VO/0riCHCl4JtsX9lAWiM1BS/wlOP7K69Qz3cH lHXg5SNUtHP1j5dp6d6dsaaOI8l+QroohU6fMXHVATmpuRb+Mavu1n2b3KIGOe/EWM6f I1bw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=0l/HYM1MzYvxmgSMUeS6CVNkTdoldvUQuoyQcBcw45w=; b=ifBLcxGIKdi1aBjQBlFYFFjpXhBo0XCeRy/Zg0IfpGbUHMdefvbQC1gM9BUEqYhJOl QHs1rhyqgOK0/XhHTCUS9GvnPo9wyvnBIVNk77NqlfnQkDm/kSlcFz/355yVIM1Lak87 IoxtCeuJE756udfz5zCqjhDnPUm3w/ksZ4EjDo4jGx3gmePI4YC1fK2n7JH1utjM1e5r Fyt/1qz33hAvpxmEVIvbe+aNNsRDV4dlSz1LjbkPftIfo6iw1Xw/nZZ0oBfwWQtHuOpu Cq5RsG0cr/HMTq0AhtepGO6rDpj2gFUsMRTd2Ib5TDy3IPJaH4V73NlSdURVJnNQf6mL eDjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WuVnQgDb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id c16-20020a624e10000000b0050dc7628142sm7721788pfb.28.2022.05.23.13.47.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 13:47:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 13/18] target/arm: Move MDCR_TDE test into exception_target_el Date: Mon, 23 May 2022 13:47:37 -0700 Message-Id: <20220523204742.740932-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220523204742.740932-1-richard.henderson@linaro.org> References: <20220523204742.740932-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add a debug parameter, and when true test MDCR_EL2.TDE. Use this in arm_debug_target_el. Signed-off-by: Richard Henderson --- target/arm/internals.h | 20 +++----------------- target/arm/op_helper.c | 12 ++++++++++-- target/arm/tlb_helper.c | 4 ++-- 3 files changed, 15 insertions(+), 21 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 6df38db836..fbb69e6919 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1074,27 +1074,13 @@ typedef struct ARMVAParameters { ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data); -int exception_target_el(CPUARMState *env, int cur_el, uint32_t *psyn); +int exception_target_el(CPUARMState *env, int cur_el, + uint32_t *psyn, bool debug); /* Return the Exception Level targeted by debug exceptions. */ static inline int arm_debug_target_el(CPUARMState *env) { - bool secure = arm_is_secure(env); - bool route_to_el2 = false; - - if (arm_is_el2_enabled(env)) { - route_to_el2 = env->cp15.hcr_el2 & HCR_TGE || - env->cp15.mdcr_el2 & MDCR_TDE; - } - - if (route_to_el2) { - return 2; - } else if (arm_feature(env, ARM_FEATURE_EL3) && - !arm_el_is_aa64(env, 3) && secure) { - return 3; - } else { - return 1; - } + return exception_target_el(env, 0, NULL, true); } /* Determine if allocation tags are available. */ diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index c4988b6c41..9fc9ab3d20 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -28,7 +28,8 @@ #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) -int exception_target_el(CPUARMState *env, int cur_el, uint32_t *psyn) +int exception_target_el(CPUARMState *env, int cur_el, + uint32_t *psyn, bool debug) { /* * FIXME: The following tests really apply to an EL0 origin, @@ -62,6 +63,12 @@ int exception_target_el(CPUARMState *env, int cur_el, uint32_t *psyn) return 2; } + if (debug + && (env->cp15.mdcr_el2 & MDCR_TDE) + && arm_is_el2_enabled(env)) { + return 2; + } + return 1; } @@ -83,7 +90,8 @@ void raise_exception(CPUARMState *env, uint32_t excp, uint32_t syndrome, { int target_el = cur_or_target_el; if (cur_or_target_el <= 1) { - target_el = exception_target_el(env, cur_or_target_el, &syndrome); + target_el = exception_target_el(env, cur_or_target_el, + &syndrome, false); } raise_exception_int(env, excp, syndrome, target_el); } diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 573e18f830..3bf4107faa 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -90,7 +90,7 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, uint32_t syn, exc, fsr, fsc; cur_el = arm_current_el(env); - target_el = exception_target_el(env, cur_el, NULL); + target_el = exception_target_el(env, cur_el, NULL, false); if (fi->stage2) { target_el = 2; @@ -141,7 +141,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, void helper_exception_pc_alignment(CPUARMState *env, target_ulong pc) { ARMMMUFaultInfo fi = { .type = ARMFault_Alignment }; - int target_el = exception_target_el(env, arm_current_el(env), NULL); + int target_el = exception_target_el(env, arm_current_el(env), NULL, false); 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id c16-20020a624e10000000b0050dc7628142sm7721788pfb.28.2022.05.23.13.47.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 13:47:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 14/18] target/arm: Mark exception helpers as noreturn Date: Mon, 23 May 2022 13:47:38 -0700 Message-Id: <20220523204742.740932-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220523204742.740932-1-richard.henderson@linaro.org> References: <20220523204742.740932-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index b1334e0c42..5161cdf73d 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -44,9 +44,9 @@ DEF_HELPER_FLAGS_2(usad8, TCG_CALL_NO_RWG_SE, i32, i32, i32) DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) -DEF_HELPER_2(exception_internal, void, env, i32) -DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32) -DEF_HELPER_2(exception_bkpt_insn, void, env, i32) +DEF_HELPER_2(exception_internal, noreturn, env, i32) +DEF_HELPER_4(exception_with_syndrome, noreturn, env, i32, i32, i32) +DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) DEF_HELPER_1(setend, void, env) DEF_HELPER_2(wfi, void, env, i32) From patchwork Mon May 23 20:47:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 575410 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:c603:0:0:0:0 with SMTP id jv3csp1732708mab; Mon, 23 May 2022 14:00:25 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyIUZuaiRqcIvpahQWycvSiOmqf/mUVtWVTFvPSBQ5XENZYND1wmV8O8mGXkFY/1BTyjsod X-Received: by 2002:a05:620a:2546:b0:680:f744:5bc6 with SMTP id s6-20020a05620a254600b00680f7445bc6mr15197766qko.113.1653339625170; Mon, 23 May 2022 14:00:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653339625; cv=none; d=google.com; s=arc-20160816; b=kbyvYg7OQQDT6nQ5S/3G8arYGoDd0yKeorj/sc5BcIyTG++4c+oYDEr26+x8BeWi9C npADzEch6x3pPm+k1kcEylo1uOXWJPnKJvnCoUESW/qhU573Fudd4Xjr8YeIvUr1qLj8 78E3uvi2Y5MLPtPTBQWLMmYbBI6+vPLVYofXb1EutH5Y9aTWaOlLA8sI1OnPNpmgkVCA UCxXHAxmDD/ONYVxan8hZoRNfzDcPE6QfTqZaBreEs6SnUfMlF1bKOmUO8YeAZudvcEB RLf46msp8dqmPA1nqgdhYYE6TrL8h2LaPfBhFmS2a9paoN7vjZPLkV77H3sr3uLX5EGs m4zg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=jD6P95boxWaFHWGjo6mmW0PDhuVHQHt7cpvcaNfyIzM=; b=npLIZIkk3i5DoQBGq5H5gylYzCr3LHlfjy9kZtsf28jF7+/OVhixdTrzBkkX/u3Qqq SYqM9ZxGYxyjJOR0t1ttlTWJXf0Q28kHYgiXdG3asHerpczOu53vHdrYeSfXhSngmKmF aeQkfXOZPI3baTigKkypbIriDxkAeCniVoMdgAmwM+XEkKln2/Y/oEKBcXQLKyKzmf1Q 6Ndt4QrqeFvDz+EAP9iJGApVDbnDLFvmJ+qbdSptOQmJEPl2jPUK+HKzbzdpkgdQsW0p weqN9j/BbC2INYnXNrGAsJVkFK0nRTjyuDI6wfLoPYYwR8PdeEZC1bOiQs4W7tYH4ytp px/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AGLnsTiu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id c16-20020a624e10000000b0050dc7628142sm7721788pfb.28.2022.05.23.13.47.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 13:47:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 15/18] target/arm: Create helper_exception_swstep Date: Mon, 23 May 2022 13:47:39 -0700 Message-Id: <20220523204742.740932-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220523204742.740932-1-richard.henderson@linaro.org> References: <20220523204742.740932-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Move the computation from gen_swstep_exception into a helper. The assert removed here is present in raise_exception_debug. Signed-off-by: Richard Henderson --- target/arm/helper.h | 1 + target/arm/translate.h | 12 +++--------- target/arm/debug_helper.c | 5 +++++ 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 5161cdf73d..f3fd53f3f9 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -47,6 +47,7 @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, DEF_HELPER_2(exception_internal, noreturn, env, i32) DEF_HELPER_4(exception_with_syndrome, noreturn, env, i32, i32, i32) DEF_HELPER_2(exception_bkpt_insn, noreturn, env, i32) +DEF_HELPER_2(exception_swstep, noreturn, env, i32) DEF_HELPER_2(exception_pc_alignment, noreturn, env, tl) DEF_HELPER_1(setend, void, env) DEF_HELPER_2(wfi, void, env, i32) diff --git a/target/arm/translate.h b/target/arm/translate.h index 6f0ebdc88e..c03dbfb618 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -340,15 +340,9 @@ static inline void gen_exception(int excp, uint32_t syndrome, /* Generate an architectural singlestep exception */ static inline void gen_swstep_exception(DisasContext *s, int isv, int ex) { - bool same_el = (s->debug_target_el == s->current_el); - - /* - * If singlestep is targeting a lower EL than the current one, - * then s->ss_active must be false and we can never get here. - */ - assert(s->debug_target_el >= s->current_el); - - gen_exception(EXCP_UDEF, syn_swstep(same_el, isv, ex), s->debug_target_el); + /* Fill in the same_el field of the syndrome in the helper. */ + uint32_t syn = syn_swstep(false, isv, ex); + gen_helper_exception_swstep(cpu_env, tcg_constant_i32(syn)); } /* diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 181ba7b042..8d87b65a8d 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -467,6 +467,11 @@ void HELPER(exception_bkpt_insn)(CPUARMState *env, uint32_t syndrome) raise_exception_debug(env, EXCP_BKPT, syndrome); } +void HELPER(exception_swstep)(CPUARMState *env, uint32_t syndrome) +{ + raise_exception_debug(env, EXCP_UDEF, syndrome); +} + #if !defined(CONFIG_USER_ONLY) vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) From patchwork Mon May 23 20:47:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 575417 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:c603:0:0:0:0 with SMTP id jv3csp1741455mab; Mon, 23 May 2022 14:12:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJykRBWznPOGwXQHu8DIzxulHbrJt8xawkBeEBZORROnMo4bRKCXOoaOx8loBzQ0UU6347et X-Received: by 2002:a05:622a:5d1:b0:2f9:3e89:4e3b with SMTP id d17-20020a05622a05d100b002f93e894e3bmr2064083qtb.398.1653340325773; Mon, 23 May 2022 14:12:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653340325; cv=none; d=google.com; s=arc-20160816; b=KahQzGI1zxJjDW3/a94+qx+QiyOJK+8BOoaM9kd9BYGOoXCjztZf7eSqQJ4S+pPYYs zZvyt5RQpTQ86wWgaD6cfoLdSiKFK57TKDwvbt9S5lJ7QE1K1cjIKStFhDwxXQ10N7Xf LygAVGo5Ce8RiJIl87VC10xqKYMZe+i9jm4qgBVLIoKxEaTVhJDPhI4XiN4NojOE7rqE xK84O5afC33R93tG99oxfuCruafDCCfgVS3F1zGfOC2O7jNEjNTGWgo9A2+k2ZnHWYjd Rv/Earo+WZ4J0w+go7sdUyq5tP6wZWL2hkmdhy1b0b/vU9AyX3bDbXt5CBtQDCGvFYNl 5zog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=UXDNe7UAiSjLL81qtpI/xgpK//7QQXPJ6zCsJfDQpFw=; b=xiuXXDJ1y0zOsRnpTNIot4JkRNweebjN49bAkIIrW245iSyzbd7XfXBiKkr3i66ncN l70K72CWv/2PfqFxYq0GO5x0FL4lG+wwgDsV69vREJeadg981CW3wO84L7cl8g2tyDDJ ZVjxunbluftZBAv+e9ewPqBX4L2CTFqjngfGfI9755/5/BHpj15uzxhXVHlfaUd55+zY z+nysaBt8pvN9nK0V4bI62zOOzCZTcn602lS381/3b69CEWkL2I4Pnp9r+tLI3zinjOv oF8IXj9J2qDVtic1PYQMSpmBfkPrEvvarlgbeZVmQ8fea6S1eznSYPYhKH9/YTAC2Jg1 ahfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=z3petxkL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id c16-20020a624e10000000b0050dc7628142sm7721788pfb.28.2022.05.23.13.47.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 13:48:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 16/18] target/arm: Remove TBFLAG_ANY.DEBUG_TARGET_EL Date: Mon, 23 May 2022 13:47:40 -0700 Message-Id: <20220523204742.740932-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220523204742.740932-1-richard.henderson@linaro.org> References: <20220523204742.740932-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We no longer need this value during translation, as it is now handled within the helpers. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 6 ++---- target/arm/translate.h | 2 -- target/arm/helper.c | 12 ++---------- target/arm/translate-a64.c | 1 - target/arm/translate.c | 1 - 5 files changed, 4 insertions(+), 18 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 90cdc7b1de..5bc6382fce 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3064,11 +3064,9 @@ FIELD(TBFLAG_ANY, BE_DATA, 3, 1) FIELD(TBFLAG_ANY, MMUIDX, 4, 4) /* Target EL if we take a floating-point-disabled exception */ FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2) -/* For A-profile only, target EL for debug exceptions. */ -FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2) /* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */ -FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1) -FIELD(TBFLAG_ANY, PSTATE__IL, 13, 1) +FIELD(TBFLAG_ANY, ALIGN_MEM, 10, 1) +FIELD(TBFLAG_ANY, PSTATE__IL, 11, 1) /* * Bit usage when in AArch32 state, both A- and M-profile. diff --git a/target/arm/translate.h b/target/arm/translate.h index c03dbfb618..cd9ee41bbd 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -59,8 +59,6 @@ typedef struct DisasContext { */ uint32_t svc_imm; int current_el; - /* Debug target exception level for single-step exceptions */ - int debug_target_el; GHashTable *cp_regs; uint64_t features; /* CPU features bits */ bool aarch64; diff --git a/target/arm/helper.c b/target/arm/helper.c index e0be96b988..63c3fee5ff 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13626,18 +13626,10 @@ static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el, return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } -static CPUARMTBFlags rebuild_hflags_aprofile(CPUARMState *env) -{ - CPUARMTBFlags flags = {}; - - DP_TBFLAG_ANY(flags, DEBUG_TARGET_EL, arm_debug_target_el(env)); - return flags; -} - static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx) { - CPUARMTBFlags flags = rebuild_hflags_aprofile(env); + CPUARMTBFlags flags = {}; int el = arm_current_el(env); if (arm_sctlr(env, el) & SCTLR_A) { @@ -13663,7 +13655,7 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, ARMMMUIdx mmu_idx) { - CPUARMTBFlags flags = rebuild_hflags_aprofile(env); + CPUARMTBFlags flags = {}; ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr; uint64_t sctlr; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f502545307..cc9344b015 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14645,7 +14645,6 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->ss_active = EX_TBFLAG_ANY(tb_flags, SS_ACTIVE); dc->pstate_ss = EX_TBFLAG_ANY(tb_flags, PSTATE__SS); dc->is_ldex = false; - dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL); /* Bound the number of insns to execute to those left on the page. */ bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; diff --git a/target/arm/translate.c b/target/arm/translate.c index 87a899d638..59d7542a48 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9354,7 +9354,6 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->v7m_lspact = EX_TBFLAG_M32(tb_flags, LSPACT); dc->mve_no_pred = EX_TBFLAG_M32(tb_flags, MVE_NO_PRED); } else { - dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL); dc->sctlr_b = EX_TBFLAG_A32(tb_flags, SCTLR__B); dc->hstr_active = EX_TBFLAG_A32(tb_flags, HSTR_ACTIVE); dc->ns = EX_TBFLAG_A32(tb_flags, NS); From patchwork Mon May 23 20:47:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 575413 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:c603:0:0:0:0 with SMTP id jv3csp1737062mab; Mon, 23 May 2022 14:06:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyhXHSlQ9ibR+PN33dJaJhMq20NAClRIjsxy7LMKm0lRWuel45ZwcVnBe4HYLXLqnSxzhZI X-Received: by 2002:ac8:58c3:0:b0:2f9:2356:d21f with SMTP id u3-20020ac858c3000000b002f92356d21fmr10981215qta.265.1653339967415; Mon, 23 May 2022 14:06:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653339967; cv=none; d=google.com; s=arc-20160816; b=yLTl7Vz72W+x2s59gAZMmrQswqxZ+8zMOd7d++OroMUJXw9Tgh6LVRQCwVslVLnCl0 Lm/IQx8+Xfvj8rFHxkVz2ZGYpzvYHSpuJL2HaWYPpgDaHYE6aJhgh5xanQTVD+XTdH8K EMRh1LIL1rpWfUSUANSPQKMq0HlC45fBN2nXNq034ErUIWJSKDMPhXJXJwGQbyiKPp/+ fjCGOW927VBrjyF6UsZ0/7F3Qj4fEsOcgDzZH/E1SZVzhBCRq/JjoxCyU6tBFfmdYFpt DvK/kCEoOBgGsRaMmfSIZg0lMFujAl9nxYLfQIU2dTzj27WmgzQ8SHDqCqLWPNtzWjcT /pNQ== ARC-Message-Signature: i=1; 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id c16-20020a624e10000000b0050dc7628142sm7721788pfb.28.2022.05.23.13.48.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 13:48:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 17/18] target/arm: Add cur_el parameter to arm_generate_debug_exceptions Date: Mon, 23 May 2022 13:47:41 -0700 Message-Id: <20220523204742.740932-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220523204742.740932-1-richard.henderson@linaro.org> References: <20220523204742.740932-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We often have this value already handy in the caller. Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 +- target/arm/debug_helper.c | 11 +++++------ target/arm/helper-a64.c | 2 +- 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index fbb69e6919..09d25612af 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1308,6 +1308,6 @@ void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); void aa32_max_features(ARMCPU *cpu); bool arm_singlestep_active(CPUARMState *env); -bool arm_generate_debug_exceptions(CPUARMState *env); +bool arm_generate_debug_exceptions(CPUARMState *env, int cur_el); #endif diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 8d87b65a8d..a5363a5048 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -94,10 +94,8 @@ static bool aa32_generate_debug_exceptions(CPUARMState *env, int cur_el) * CheckSoftwareStep(), where it is elided because both branches would * always return the same value. */ -bool arm_generate_debug_exceptions(CPUARMState *env) +bool arm_generate_debug_exceptions(CPUARMState *env, int cur_el) { - int cur_el = arm_current_el(env); - if (is_a64(env)) { return aa64_generate_debug_exceptions(env, cur_el); } else { @@ -111,9 +109,10 @@ bool arm_generate_debug_exceptions(CPUARMState *env) */ bool arm_singlestep_active(CPUARMState *env) { + int cur_el = arm_current_el(env); return extract32(env->cp15.mdscr_el1, 0, 1) && arm_el_is_aa64(env, arm_debug_target_el(env)) - && arm_generate_debug_exceptions(env); + && arm_generate_debug_exceptions(env, cur_el); } /* Return true if the linked breakpoint entry lbn passes its checks */ @@ -309,7 +308,7 @@ static bool check_watchpoints(ARMCPU *cpu) * exceptions here then watchpoint firings are ignored. */ if (extract32(env->cp15.mdscr_el1, 15, 1) == 0 - || !arm_generate_debug_exceptions(env)) { + || !arm_generate_debug_exceptions(env, arm_current_el(env))) { return false; } @@ -333,7 +332,7 @@ bool arm_debug_check_breakpoint(CPUState *cs) * exceptions here then breakpoint firings are ignored. */ if (extract32(env->cp15.mdscr_el1, 15, 1) == 0 - || !arm_generate_debug_exceptions(env)) { + || !arm_generate_debug_exceptions(env, arm_current_el(env))) { return false; } diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 22db213aab..fe2a0aa261 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -924,7 +924,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) * We check 1 here and 2 after we've done the pstate/cpsr write() to * transition to the EL we're going to. */ - if (arm_generate_debug_exceptions(env)) { + if (arm_generate_debug_exceptions(env, cur_el)) { spsr &= ~PSTATE_SS; } From patchwork Mon May 23 20:47:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 575416 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:c603:0:0:0:0 with SMTP id jv3csp1738303mab; Mon, 23 May 2022 14:07:42 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxmAkRb6N7admQf5V2MRgIYIykQ/m55lqq0JprF9JWWgo+lIBnYJc0t5NrKZY5KNl9NKyIe X-Received: by 2002:a05:6214:c8a:b0:462:3b0a:992d with SMTP id r10-20020a0562140c8a00b004623b0a992dmr5634151qvr.107.1653340062249; Mon, 23 May 2022 14:07:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1653340062; cv=none; d=google.com; s=arc-20160816; b=Eh/juAmOB01aFLhNOb+9BjAuKjGhbRX8mJQvmegOC0dKbEtbMHczSTHj1QnHjj6lqR McmMxUMoniuPUhLKzdUqFxksy2USaisQ/5sPcFShL4rDOKGkhxWXA8Of4J8+H1pR42Al S362quqTBH9Z+kvNBX5b68BHl4tuvp3zOPXJ9F24xy9gXqd9Y+QXjh2MFrGG9KB1HhRc IKQfoQ6yP0/nZneztPot3S74pjbvPMBSeTGecAQ3K+ZpBRDiNAXLuIpuTam+kLxB/zze YtYV0kxAsaYAh1WYngHI666Zq1h/idwyLnxCs4yG3TFQDzlkqxtQT2lsk2X59pkwHsMi 0kiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=WRIXhi2sPFQ8say7R+yvzgVuvHNeZiRuu0E48iydKNc=; b=tFNBpM0qUhM5qX6nfvP+j+FQmPClTCvVVQgrom4ZRaEdhEad0uj3DU1/PA5lq880BV 7H4miZ7h5yOJQRdFZ+FJ+NyFJbjWyGfwsh/QEBn8ezMqshfpjcZ/jhiV/IbxD2YIUrYr G3yxpwtX2MRXWjQX6/qJ5Mm8paUywDXyMgyn7u02lTXhwaJPS67Dvg0/BtTcd6jroWE7 hMGvJYfO23+3FKOSzxHTDFVrJWGKJEoad6VbwvS0yfVU+sQ/ecB1xEZPHRUWa1m4hNF5 yVf2I3J1SAH5ZkXpdSdsV7f5VZ9jtsfBK6oxOh87XlPSbO4e30wfweLekzxw19rqW26E XNRw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HoP9xXt9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id c16-20020a624e10000000b0050dc7628142sm7721788pfb.28.2022.05.23.13.48.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 May 2022 13:48:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 18/18] target/arm: Remove route_to_el2 case from sve_exception_el Date: Mon, 23 May 2022 13:47:42 -0700 Message-Id: <20220523204742.740932-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220523204742.740932-1-richard.henderson@linaro.org> References: <20220523204742.740932-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This adjustment is handled by exception_target_el. Signed-off-by: Richard Henderson --- target/arm/helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 63c3fee5ff..5c875927cf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6155,8 +6155,7 @@ int sve_exception_el(CPUARMState *env, int el) /* fall through */ case 0: case 2: - /* route_to_el2 */ - return hcr_el2 & HCR_TGE ? 2 : 1; + return 1; } /* Check CPACR.FPEN. */