From patchwork Fri May 20 20:06:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuogee Hsieh X-Patchwork-Id: 574576 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3F0BC433EF for ; Fri, 20 May 2022 20:06:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353398AbiETUGX (ORCPT ); Fri, 20 May 2022 16:06:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353356AbiETUGW (ORCPT ); Fri, 20 May 2022 16:06:22 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 04571186FC; Fri, 20 May 2022 13:06:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1653077181; x=1684613181; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=EIsTc115xZd3zTecmkqFCaqqIlt79MVWLqqDXZzAgBQ=; b=Gfdu2nU4UY/4QaBtZ+2WgpyNYw5RrtdHBDm3dj4Wrs4HHKKwEXbDtvdB uepB66RyzFOWtssQ7ilpMYiITXhksncPvqIDrsN775+yDXP/mChs26HjR IbO9OXGsrw6xDEp+514C2aEYsf8Ux8VBZSf0BYhH8CuxoMpAyw1k6jDjg w=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-02.qualcomm.com with ESMTP; 20 May 2022 13:06:20 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg02-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2022 13:06:20 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 20 May 2022 13:06:19 -0700 Received: from khsieh-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 20 May 2022 13:06:18 -0700 From: Kuogee Hsieh To: , , , , , , , , , , CC: Kuogee Hsieh , , , , , , Subject: [PATCH v9 1/3] phy: qcom-edp: add regulator_set_load to edp phy Date: Fri, 20 May 2022 13:06:05 -0700 Message-ID: <1653077167-16684-2-git-send-email-quic_khsieh@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1653077167-16684-1-git-send-email-quic_khsieh@quicinc.com> References: <1653077167-16684-1-git-send-email-quic_khsieh@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch add regulator_set_load() before enable regulator at eDP phy driver. Signed-off-by: Kuogee Hsieh --- drivers/phy/qualcomm/phy-qcom-edp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c index cacd32f..0b7f318 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -639,6 +639,9 @@ static int qcom_edp_phy_probe(struct platform_device *pdev) if (ret) return ret; + regulator_set_load(edp->supplies[0].consumer, 21800); /* 1.2 V vdda-phy */ + regulator_set_load(edp->supplies[1].consumer, 36000); /* 0.9 V vdda-pll */ + ret = qcom_edp_clks_register(edp, pdev->dev.of_node); if (ret) return ret; From patchwork Fri May 20 20:06:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuogee Hsieh X-Patchwork-Id: 574575 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B83EC433F5 for ; Fri, 20 May 2022 20:06:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353383AbiETUG1 (ORCPT ); Fri, 20 May 2022 16:06:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353414AbiETUGY (ORCPT ); Fri, 20 May 2022 16:06:24 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D2F621E36; Fri, 20 May 2022 13:06:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1653077183; x=1684613183; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=PUvRDpvZT9v/W/ZNUZCWbBBqz/jvGvrHkHApZBnQyGA=; b=tOeKaN6TRLuVlnZtSCsox/gM5vYcwLWQAiHrfNGoBvJKfrGnYVCEj1Jm CZ5bwzl4ouMdbuGkUiBoJsYrGELv1YfZimZkSwqqw3tdOocIQOE7hmscW ynGnzewPat8NSX1Ii+PKWFJjDgNtNxQHgq3BmcFDLLP56LWtqejcx37K1 U=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 20 May 2022 13:06:22 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2022 13:06:21 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 20 May 2022 13:06:21 -0700 Received: from khsieh-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 20 May 2022 13:06:20 -0700 From: Kuogee Hsieh To: , , , , , , , , , , CC: Kuogee Hsieh , , , , , , Subject: [PATCH v9 2/3] phy: qcom-qmp: add regulator_set_load to dp phy Date: Fri, 20 May 2022 13:06:06 -0700 Message-ID: <1653077167-16684-3-git-send-email-quic_khsieh@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1653077167-16684-1-git-send-email-quic_khsieh@quicinc.com> References: <1653077167-16684-1-git-send-email-quic_khsieh@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This patch add regulator_set_load() before enable regulator at DP phy driver. Signed-off-by: Kuogee Hsieh Reviewed-by: Stephen Boyd --- drivers/phy/qualcomm/phy-qcom-qmp.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index b144ae1..bd267c7 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -3130,6 +3130,7 @@ struct qmp_phy_cfg { int num_resets; /* regulators to be requested */ const char * const *vreg_list; + const unsigned int *vreg_enable_load; int num_vregs; /* array of registers with different offsets */ @@ -3346,6 +3347,10 @@ static const char * const qmp_phy_vreg_l[] = { "vdda-phy", "vdda-pll", }; +static const unsigned int qmp_phy_vreg_enable_load[] = { + 21800, 36000 +}; + static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { .type = PHY_TYPE_USB3, .nlanes = 1, @@ -3711,6 +3716,7 @@ static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { .reset_list = sc7180_usb3phy_reset_l, .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), .vreg_list = qmp_phy_vreg_l, + .vreg_enable_load = qmp_phy_vreg_enable_load, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = qmp_v3_usb3phy_regs_layout, @@ -3749,6 +3755,7 @@ static const struct qmp_phy_cfg sc7180_dpphy_cfg = { .reset_list = sc7180_usb3phy_reset_l, .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), .vreg_list = qmp_phy_vreg_l, + .vreg_enable_load = qmp_phy_vreg_enable_load, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = qmp_v3_usb3phy_regs_layout, @@ -3940,6 +3947,7 @@ static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { .reset_list = msm8996_usb3phy_reset_l, .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), .vreg_list = qmp_phy_vreg_l, + .vreg_enable_load = qmp_phy_vreg_enable_load, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = qmp_v4_usb3phy_regs_layout, @@ -4009,6 +4017,7 @@ static const struct qmp_phy_cfg sc8180x_dpphy_cfg = { .reset_list = sc7180_usb3phy_reset_l, .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), .vreg_list = qmp_phy_vreg_l, + .vreg_enable_load = qmp_phy_vreg_enable_load, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = qmp_v3_usb3phy_regs_layout, @@ -4072,6 +4081,7 @@ static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { .reset_list = msm8996_usb3phy_reset_l, .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), .vreg_list = qmp_phy_vreg_l, + .vreg_enable_load = qmp_phy_vreg_enable_load, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = qmp_v4_usb3phy_regs_layout, @@ -4139,6 +4149,7 @@ static const struct qmp_phy_cfg sm8250_dpphy_cfg = { .reset_list = msm8996_usb3phy_reset_l, .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), .vreg_list = qmp_phy_vreg_l, + .vreg_enable_load = qmp_phy_vreg_enable_load, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), .regs = qmp_v4_usb3phy_regs_layout, @@ -6107,7 +6118,7 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) const struct qmp_phy_cfg *usb_cfg = NULL; const struct qmp_phy_cfg *dp_cfg = NULL; int num, id, expected_phys; - int ret; + int ret, i; qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); if (!qmp) @@ -6175,6 +6186,12 @@ static int qcom_qmp_phy_probe(struct platform_device *pdev) return ret; } + if (cfg->vreg_enable_load) { + for (i = 0; i < cfg->num_vregs; i++) + regulator_set_load(qmp->vregs[i].consumer, + cfg->vreg_enable_load[i]); + } + num = of_get_available_child_count(dev->of_node); /* do we have a rogue child node ? */ if (num > expected_phys) From patchwork Fri May 20 20:06:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kuogee Hsieh X-Patchwork-Id: 575007 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA66DC433F5 for ; Fri, 20 May 2022 20:06:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353417AbiETUG0 (ORCPT ); Fri, 20 May 2022 16:06:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43662 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353415AbiETUGZ (ORCPT ); Fri, 20 May 2022 16:06:25 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9CD472228D; Fri, 20 May 2022 13:06:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1653077183; x=1684613183; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=rI5ZKSOJKM0Bcjv9f134lRqpnioCEqKK1pNus30VpcY=; b=GBElwX6UDWDIOEjDh88lPM9EVLj5CRi6NFQZ0vWqrvyBdyX2QVA7kWWD leDjng2XFGhMQTqcdN39V3IC/hfy1lQC4Bg6vbu2h9mRNl5LX+S+/YhQ4 q7fRRpiRCgzsAccCtNT2yIfgK/CETcj1nDai7rwOOKtnB/6bLXNWb3mta c=; Received: from unknown (HELO ironmsg03-sd.qualcomm.com) ([10.53.140.143]) by alexa-out-sd-02.qualcomm.com with ESMTP; 20 May 2022 13:06:23 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg03-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 May 2022 13:06:23 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 20 May 2022 13:06:22 -0700 Received: from khsieh-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 20 May 2022 13:06:21 -0700 From: Kuogee Hsieh To: , , , , , , , , , , CC: Kuogee Hsieh , , , , , , Subject: [PATCH v9 3/3] drm/msm/dp: delete vdda regulator related functions from eDP/DP controller Date: Fri, 20 May 2022 13:06:07 -0700 Message-ID: <1653077167-16684-4-git-send-email-quic_khsieh@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1653077167-16684-1-git-send-email-quic_khsieh@quicinc.com> References: <1653077167-16684-1-git-send-email-quic_khsieh@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Vdda regulators are related to both eDP and DP phy so that it should be managed at eDP and DP phy driver instead of controller. This patch removes vdda regulators related functions out of eDP/DP controller. Signed-off-by: Kuogee Hsieh Reviewed-by: Stephen Boyd Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_parser.c | 14 ------ drivers/gpu/drm/msm/dp/dp_parser.h | 6 --- drivers/gpu/drm/msm/dp/dp_power.c | 95 +------------------------------------- 3 files changed, 2 insertions(+), 113 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c index 8f9fed9..4ef2130 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.c +++ b/drivers/gpu/drm/msm/dp/dp_parser.c @@ -22,14 +22,6 @@ #define DP_DEFAULT_P0_OFFSET 0x1000 #define DP_DEFAULT_P0_SIZE 0x0400 -static const struct dp_regulator_cfg sdm845_dp_reg_cfg = { - .num = 2, - .regs = { - {"vdda-1p2", 21800, 4 }, /* 1.2 V */ - {"vdda-0p9", 36000, 32 }, /* 0.9 V */ - }, -}; - static void __iomem *dp_ioremap(struct platform_device *pdev, int idx, size_t *len) { struct resource *res; @@ -298,12 +290,6 @@ static int dp_parser_parse(struct dp_parser *parser) if (rc) return rc; - /* Map the corresponding regulator information according to - * version. Currently, since we only have one supported platform, - * mapping the regulator directly. - */ - parser->regulator_cfg = &sdm845_dp_reg_cfg; - return 0; } diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h b/drivers/gpu/drm/msm/dp/dp_parser.h index 3a4d797..b56b4d7 100644 --- a/drivers/gpu/drm/msm/dp/dp_parser.h +++ b/drivers/gpu/drm/msm/dp/dp_parser.h @@ -101,11 +101,6 @@ struct dp_reg_entry { int disable_load; }; -struct dp_regulator_cfg { - int num; - struct dp_reg_entry regs[DP_DEV_REGULATOR_MAX]; -}; - /** * struct dp_parser - DP parser's data exposed to clients * @@ -121,7 +116,6 @@ struct dp_parser { struct dp_pinctrl pinctrl; struct dp_io io; struct dp_display_data disp_data; - const struct dp_regulator_cfg *regulator_cfg; u32 max_dp_lanes; struct drm_bridge *next_bridge; diff --git a/drivers/gpu/drm/msm/dp/dp_power.c b/drivers/gpu/drm/msm/dp/dp_power.c index d9e0117..b52ac1d 100644 --- a/drivers/gpu/drm/msm/dp/dp_power.c +++ b/drivers/gpu/drm/msm/dp/dp_power.c @@ -20,82 +20,10 @@ struct dp_power_private { struct clk *link_clk_src; struct clk *pixel_provider; struct clk *link_provider; - struct regulator_bulk_data supplies[DP_DEV_REGULATOR_MAX]; struct dp_power dp_power; }; -static void dp_power_regulator_disable(struct dp_power_private *power) -{ - struct regulator_bulk_data *s = power->supplies; - const struct dp_reg_entry *regs = power->parser->regulator_cfg->regs; - int num = power->parser->regulator_cfg->num; - int i; - - DBG(""); - for (i = num - 1; i >= 0; i--) - if (regs[i].disable_load >= 0) - regulator_set_load(s[i].consumer, - regs[i].disable_load); - - regulator_bulk_disable(num, s); -} - -static int dp_power_regulator_enable(struct dp_power_private *power) -{ - struct regulator_bulk_data *s = power->supplies; - const struct dp_reg_entry *regs = power->parser->regulator_cfg->regs; - int num = power->parser->regulator_cfg->num; - int ret, i; - - DBG(""); - for (i = 0; i < num; i++) { - if (regs[i].enable_load >= 0) { - ret = regulator_set_load(s[i].consumer, - regs[i].enable_load); - if (ret < 0) { - pr_err("regulator %d set op mode failed, %d\n", - i, ret); - goto fail; - } - } - } - - ret = regulator_bulk_enable(num, s); - if (ret < 0) { - pr_err("regulator enable failed, %d\n", ret); - goto fail; - } - - return 0; - -fail: - for (i--; i >= 0; i--) - regulator_set_load(s[i].consumer, regs[i].disable_load); - return ret; -} - -static int dp_power_regulator_init(struct dp_power_private *power) -{ - struct regulator_bulk_data *s = power->supplies; - const struct dp_reg_entry *regs = power->parser->regulator_cfg->regs; - struct platform_device *pdev = power->pdev; - int num = power->parser->regulator_cfg->num; - int i, ret; - - for (i = 0; i < num; i++) - s[i].supply = regs[i].name; - - ret = devm_regulator_bulk_get(&pdev->dev, num, s); - if (ret < 0) { - pr_err("%s: failed to init regulator, ret=%d\n", - __func__, ret); - return ret; - } - - return 0; -} - static int dp_power_clk_init(struct dp_power_private *power) { int rc = 0; @@ -318,21 +246,10 @@ int dp_power_client_init(struct dp_power *dp_power) pm_runtime_enable(&power->pdev->dev); - rc = dp_power_regulator_init(power); - if (rc) { - DRM_ERROR("failed to init regulators %d\n", rc); - goto error; - } - rc = dp_power_clk_init(power); - if (rc) { + if (rc) DRM_ERROR("failed to init clocks %d\n", rc); - goto error; - } - return 0; -error: - pm_runtime_disable(&power->pdev->dev); return rc; } @@ -365,22 +282,15 @@ int dp_power_init(struct dp_power *dp_power, bool flip) power = container_of(dp_power, struct dp_power_private, dp_power); pm_runtime_get_sync(&power->pdev->dev); - rc = dp_power_regulator_enable(power); - if (rc) { - DRM_ERROR("failed to enable regulators, %d\n", rc); - goto exit; - } rc = dp_power_clk_enable(dp_power, DP_CORE_PM, true); if (rc) { DRM_ERROR("failed to enable DP core clocks, %d\n", rc); - goto err_clk; + goto exit; } return 0; -err_clk: - dp_power_regulator_disable(power); exit: pm_runtime_put_sync(&power->pdev->dev); return rc; @@ -393,7 +303,6 @@ int dp_power_deinit(struct dp_power *dp_power) power = container_of(dp_power, struct dp_power_private, dp_power); dp_power_clk_enable(dp_power, DP_CORE_PM, false); - dp_power_regulator_disable(power); pm_runtime_put_sync(&power->pdev->dev); return 0; }