From patchwork Mon May 16 00:54:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ChiaWei Wang X-Patchwork-Id: 573139 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE374C433FE for ; Mon, 16 May 2022 00:55:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238707AbiEPAzQ (ORCPT ); Sun, 15 May 2022 20:55:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53152 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235210AbiEPAzO (ORCPT ); Sun, 15 May 2022 20:55:14 -0400 Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC9BD2A258; Sun, 15 May 2022 17:55:09 -0700 (PDT) Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 24G0eWss022582; Mon, 16 May 2022 08:40:32 +0800 (GMT-8) (envelope-from chiawei_wang@aspeedtech.com) Received: from Chiawei-PC03.aspeed.com (192.168.2.66) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 16 May 2022 08:54:05 +0800 From: Chia-Wei Wang To: , , , , , , , , , , , CC: Subject: [PATCH v5 1/4] dt-bindings: aspeed: Add eSPI controller Date: Mon, 16 May 2022 08:54:09 +0800 Message-ID: <20220516005412.4844-2-chiawei_wang@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220516005412.4844-1-chiawei_wang@aspeedtech.com> References: <20220516005412.4844-1-chiawei_wang@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.2.66] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 24G0eWss022582 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add dt-bindings for Aspeed eSPI controller Signed-off-by: Chia-Wei Wang --- .../devicetree/bindings/soc/aspeed/espi.yaml | 162 ++++++++++++++++++ 1 file changed, 162 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/aspeed/espi.yaml diff --git a/Documentation/devicetree/bindings/soc/aspeed/espi.yaml b/Documentation/devicetree/bindings/soc/aspeed/espi.yaml new file mode 100644 index 000000000000..aa91ec8caf6a --- /dev/null +++ b/Documentation/devicetree/bindings/soc/aspeed/espi.yaml @@ -0,0 +1,162 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# # Copyright (c) 2021 Aspeed Technology Inc. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/aspeed/espi.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Aspeed eSPI Controller + +maintainers: + - Chia-Wei Wang + - Ryan Chen + +description: + Aspeed eSPI controller implements a slave side eSPI endpoint device + supporting the four eSPI channels, namely peripheral, virtual wire, + out-of-band, and flash. + +properties: + compatible: + items: + - enum: + - aspeed,ast2500-espi + - aspeed,ast2600-espi + - const: simple-mfd + - const: syscon + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + +patternProperties: + "^espi-ctrl@[0-9a-f]+$": + type: object + + description: Control of the four basic eSPI channels + + properties: + compatible: + items: + - enum: + - aspeed,ast2500-espi-ctrl + - aspeed,ast2600-espi-ctrl + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + perif,memcyc-enable: + type: boolean + description: Enable memory cycle over eSPI peripheral channel + + perif,memcyc-src-addr: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The Host side address to be decoded into the memory cycle over eSPI peripheral channel + + perif,memcyc-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The size of the memory region allocated for the memory cycle over eSPI peripheral channel + minimum: 65536 + + perif,dma-mode: + type: boolean + description: Enable DMA support for eSPI peripheral channel + + oob,dma-mode: + type: boolean + description: Enable DMA support for eSPI out-of-band channel + + oob,dma-tx-desc-num: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 2 + maximum: 1023 + description: The number of TX descriptors available for eSPI OOB DMA engine + + oob,dma-rx-desc-num: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 2 + maximum: 1023 + description: The number of RX descriptors available for eSPI OOB DMA engine + + flash,dma-mode: + type: boolean + description: Enable DMA support for eSPI flash channel + + flash,safs-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2 ] + default: 0 + description: Slave-Attached-Sharing-Flash mode, 0->Mix, 1->SW, 2->HW + + dependencies: + perif,memcyc-src-addr: [ "perif,memcyc-enable" ] + perif,memcyc-size: [ "perif,memcyc-enable" ] + oob,dma-tx-desc-num: [ "oob,dma-mode" ] + oob,dma-rx-desc-num: [ "oob,dma-mode" ] + + required: + - compatible + - interrupts + - clocks + + "^espi-mmbi@[0-9a-f]+$": + type: object + + description: Control of the PCH-BMC data exchange over eSPI peripheral memory cycle + + properties: + compatible: + const: aspeed,ast2600-espi-mmbi + + interrupts: + maxItems: 1 + + required: + - compatible + - interrupts + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: false + +examples: + - | + #include + #include + + espi: espi@1e6ee000 { + compatible = "aspeed,ast2600-espi", "simple-mfd", "syscon"; + reg = <0x1e6ee000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e6ee000 0x1000>; + + espi_ctrl: espi-ctrl@0 { + compatible = "aspeed,ast2600-espi-ctrl"; + reg = <0x0 0x800>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_ESPICLK>; + }; + + espi_mmbi: espi-mmbi@800 { + compatible = "aspeed,ast2600-espi-mmbi"; + reg = <0x800 0x50>; + interrupts = ; + }; + }; From patchwork Mon May 16 00:54:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: ChiaWei Wang X-Patchwork-Id: 573140 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82B50C433EF for ; Mon, 16 May 2022 00:55:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238587AbiEPAzP (ORCPT ); Sun, 15 May 2022 20:55:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234471AbiEPAzO (ORCPT ); Sun, 15 May 2022 20:55:14 -0400 Received: from twspam01.aspeedtech.com (twspam01.aspeedtech.com [211.20.114.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B95772A256; Sun, 15 May 2022 17:55:09 -0700 (PDT) Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 24G0eXN3022584; Mon, 16 May 2022 08:40:33 +0800 (GMT-8) (envelope-from chiawei_wang@aspeedtech.com) Received: from Chiawei-PC03.aspeed.com (192.168.2.66) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 16 May 2022 08:54:05 +0800 From: Chia-Wei Wang To: , , , , , , , , , , , CC: Subject: [PATCH v5 4/4] ARM: dts: aspeed: Add eSPI node Date: Mon, 16 May 2022 08:54:12 +0800 Message-ID: <20220516005412.4844-5-chiawei_wang@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220516005412.4844-1-chiawei_wang@aspeedtech.com> References: <20220516005412.4844-1-chiawei_wang@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.2.66] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 24G0eXN3022584 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add eSPI to the device tree for Aspeed 5/6th generation SoCs. Signed-off-by: Chia-Wei Wang --- arch/arm/boot/dts/aspeed-g5.dtsi | 17 +++++++++++++++++ arch/arm/boot/dts/aspeed-g6.dtsi | 17 +++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 4147b397c883..4b5bb91a0219 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -289,6 +289,23 @@ adc: adc@1e6e9000 { status = "disabled"; }; + espi: espi@1e6ee000 { + compatible = "aspeed,ast2500-espi", "simple-mfd", "syscon"; + reg = <0x1e6ee000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e6ee000 0x1000>; + + espi_ctrl: espi-ctrl@0 { + compatible = "aspeed,ast2500-espi-ctrl"; + reg = <0x0 0x800>; + interrupts = <23>; + clocks = <&syscon ASPEED_CLK_GATE_ESPICLK>; + status = "disabled"; + }; + }; + video: video@1e700000 { compatible = "aspeed,ast2500-video-engine"; reg = <0x1e700000 0x1000>; diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 3d5ce9da42c3..1f14ecad51af 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -384,6 +384,23 @@ adc1: adc@1e6e9100 { status = "disabled"; }; + espi: espi@1e6ee000 { + compatible = "aspeed,ast2600-espi", "simple-mfd", "syscon"; + reg = <0x1e6ee000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e6ee000 0x1000>; + + espi_ctrl: espi-ctrl@0 { + compatible = "aspeed,ast2600-espi-ctrl"; + reg = <0x0 0x800>; + interrupts = ; + clocks = <&syscon ASPEED_CLK_GATE_ESPICLK>; + status = "disabled"; + }; + }; + sbc: secure-boot-controller@1e6f2000 { compatible = "aspeed,ast2600-sbc"; reg = <0x1e6f2000 0x1000>;