From patchwork Mon May 16 17:38:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anand Gore X-Patchwork-Id: 573066 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED658C433EF for ; Mon, 16 May 2022 17:38:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344324AbiEPRi2 (ORCPT ); Mon, 16 May 2022 13:38:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344319AbiEPRi1 (ORCPT ); Mon, 16 May 2022 13:38:27 -0400 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6000BFD3A for ; Mon, 16 May 2022 10:38:26 -0700 (PDT) Received: by mail-pf1-x42a.google.com with SMTP id y41so14643036pfw.12 for ; Mon, 16 May 2022 10:38:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version; bh=G3oFqG4QxOUL08eaC4tKO5BtkO5rCFTyUhzmAtGWkZM=; b=bVnGiIOq9WUaeLyoTh1KZOKAWgsL4EXKSM3g/J/AC71pglFiWQwRrRip7SFg4pVmr1 kRxgaEqhuFUqjsOk1XKHLHU3XZKXG16hpE87qdwFQIBBID3zsnKyK8oZY0Z52ehA/qcJ 32PiptGtRQyT1bEWJkFYIGf7mD0PSAYlhkEU0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version; bh=G3oFqG4QxOUL08eaC4tKO5BtkO5rCFTyUhzmAtGWkZM=; b=hCIPShT3bpvkSQv2bGEtzVB2fksnVtrFltw0wXEMvm9/rYTkpXCtye5xHcYjmeuXRd 0XM2sy/sEgZdZLmJ/0AuJsrOWxIapfg0/zq00+eYtiCCp8x82/TAD3E/5dKx8KsVIjvv ZCv97mCJeZdTPcvGuhrtGNWSy2sTZbo1AvInlXw9cstzoPgSjx8cLnCjjidz7ASQpVxP HAewvG8KsM7vykW3ZMdP+4BzislKI8M7dCWdBrRbpUss+SVimk8S34kuvbiFeSJoEV+j IwPrO13oexHcHd0dzE5ceFNw55MvMsUMt+i9c7hKrlohlFhQL8DZq9UHmnpbQbGLGWos Gl9Q== X-Gm-Message-State: AOAM532lZULdSZL2ujt22W+mKxu/JQ7EP/kBSC2xYohO9dnjxh70WH02 A4IOE6JHVZeQRkm+7igTNde5Sw== X-Google-Smtp-Source: ABdhPJwEmlVI+Q+CVgX+AAv/xUDw6Ld78C2JfKCZIPVTVSiCjmWQuvA9SoSv6yMuSHV31oxqe2+Vxg== X-Received: by 2002:a05:6a00:198f:b0:50e:7e6:6d5c with SMTP id d15-20020a056a00198f00b0050e07e66d5cmr18282559pfl.20.1652722705773; Mon, 16 May 2022 10:38:25 -0700 (PDT) Received: from linuxpc-ThinkServer-TS140.dhcp.broadcom.net ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id 129-20020a620487000000b0050dc76281e0sm7075344pfe.186.2022.05.16.10.38.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 May 2022 10:38:25 -0700 (PDT) From: Anand Gore To: linux-arm-kernel@lists.infradead.org Cc: dan.beygelman@broadcom.com, joel.peshkin@broadcom.com, florian.fainelli@broadcom.com, Broadcom Kernel List , kursad.oney@broadcom.com, William Zhang , Anand Gore , Arnd Bergmann , Krzysztof Kozlowski , Olof Johansson , Rob Herring , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, soc@kernel.org Subject: [PATCH 1/3] ARM: dts: add dts files for bcmbca soc 63178 Date: Mon, 16 May 2022 10:38:06 -0700 Message-Id: <20220516103801.1.If6875f219ec3c728983c6aec498ef67b43cef8b7@changeid> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220516173808.1391482-1-anand.gore@broadcom.com> References: <20220516173808.1391482-1-anand.gore@broadcom.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add dts for ARMv7 based broadband SoC BCM63178. bcm63178.dtsi is the SoC description dts header and bcm963178.dts is a simple dts file for Broadcom BCM963178 Reference board that only enable the UART port. Signed-off-by: Anand Gore --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/bcm63178.dtsi | 118 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/bcm963178.dts | 30 ++++++++ 3 files changed, 150 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/bcm63178.dtsi create mode 100644 arch/arm/boot/dts/bcm963178.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f9f6fa4f4825..d9ac59524408 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -182,7 +182,8 @@ dtb-$(CONFIG_ARCH_BERLIN) += \ dtb-$(CONFIG_ARCH_BRCMSTB) += \ bcm7445-bcm97445svmb.dtb dtb-$(CONFIG_ARCH_BCMBCA) += \ - bcm947622.dtb + bcm947622.dtb \ + bcm963178.dtb dtb-$(CONFIG_ARCH_CLPS711X) += \ ep7211-edb7211.dtb dtb-$(CONFIG_ARCH_DAVINCI) += \ diff --git a/arch/arm/boot/dts/bcm63178.dtsi b/arch/arm/boot/dts/bcm63178.dtsi new file mode 100644 index 000000000000..5463443f0762 --- /dev/null +++ b/arch/arm/boot/dts/bcm63178.dtsi @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Broadcom Ltd. + */ + +#include +#include + +/ { + compatible = "brcm,bcm63178", "brcm,bcmbca"; + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CA7_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + + CA7_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + CA7_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + next-level-cache = <&L2_0>; + enable-method = "psci"; + }; + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + arm,cpu-registers-not-fw-configured; + }; + + pmu: pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + ; + interrupt-affinity = <&CA7_0>, <&CA7_1>, + <&CA7_2>; + }; + + clocks: clocks { + periph_clk: periph-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&periph_clk>; + clock-div = <4>; + clock-mult = <1>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + cpu_off = <1>; + cpu_on = <2>; + }; + + axi@81000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x81000000 0x4000>; + + gic: interrupt-controller@1000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1000 0x1000>, + <0x2000 0x2000>; + }; + }; + + bus@ff800000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff800000 0x800000>; + + uart0: serial@12000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x12000 0x1000>; + interrupts = ; + clocks = <&uart_clk>, <&uart_clk>; + clock-names = "uartclk", "apb_pclk"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm963178.dts b/arch/arm/boot/dts/bcm963178.dts new file mode 100644 index 000000000000..fa096e9cde23 --- /dev/null +++ b/arch/arm/boot/dts/bcm963178.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 Broadcom Ltd. + */ + +/dts-v1/; + +#include "bcm63178.dtsi" + +/ { + model = "Broadcom BCM963178 Reference Board"; + compatible = "brcm,bcm963178", "brcm,bcm63178", "brcm,bcmbca"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x08000000>; + }; +}; + +&uart0 { + status = "okay"; +};