From patchwork Sun May 15 20:45:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 572807 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B00FC433EF for ; Sun, 15 May 2022 20:45:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233094AbiEOUpr (ORCPT ); Sun, 15 May 2022 16:45:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230175AbiEOUpp (ORCPT ); Sun, 15 May 2022 16:45:45 -0400 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB62F101CF; Sun, 15 May 2022 13:45:43 -0700 (PDT) Received: by mail-ed1-x52b.google.com with SMTP id j28so1942400eda.13; Sun, 15 May 2022 13:45:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=tU6uMaYficFOXva4xeM/4aLqe2TPDWlHeWmOttB+92A=; b=P7TMK03vc1TChbgogl3ipw55D51VjwvKdAuihPqDCO8UPPVh9Hc0+K5hf9Qd33/Mpt //OL49uwGwZj8lWj1IMXNYKWboerFDDcdcewQ9+JoiJYwQanBfr5NEgUKSxZOdWKf6Wr eKobsDqGALNdzY2YV6d1nx3uqui1Snzyab+zeDVy2F94uUeHxkhKJWgnT5fFRvnqTYDm UdCSzE53aVfkag8SZGOaDxyzQyi53579I1wwdyN4NFNQXwKcu9yXSfUOdPozgjThn22+ 3DfnrqeqV9+i05AQq9wWJMkrvhhlHugZCypqqBsA59IAFmacAgcIJdsdAiNHnx+L4K8D FDZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=tU6uMaYficFOXva4xeM/4aLqe2TPDWlHeWmOttB+92A=; b=ZcpvOvx6XsAv+zwHmK6IwDE5dAR7NccupoC7p705AHHuuq6W05IYXrSqkxGox3SCR7 RdiJg+6ugyTelWmIGLh6g1A0ag3WGe/coJRcktHD4eXhR0d66qyDTiIO3d+Q0VxSZS7p +T5l7zlLKEipT1DYF4qO3VTQrQdnLlBKTovQGU2QESkYfet8ubs+x1c26cUzrKMv3VLU XL0rCxZ8+X+/tQC98g1OAtB3CPHJY5Y1zBKZU1MsJp9u23YGHXSGtKZKgMOqLAtZAd3H rT7oGBmBgmMiRP78K0n7DF1RYWwDHwg7FKtNfkGT1hn/TwSkomYG3QMiVEZxK5A8VkVV bgBQ== X-Gm-Message-State: AOAM532d2dXqCmXyEaXbcHT1LHYdTUK1wK8gAFKZwKiDKwej2cuctssg vUN7ACaZMgr6xCdudk/mJMG0z/Bqn2Gp9w== X-Google-Smtp-Source: ABdhPJwYZFDmvGmQVM5BvZuDSpnC/dP7nbjdio7lY6LzlTi8nCBgbLC9fjqP2uJkwsFacO3oCVqxzg== X-Received: by 2002:a05:6402:b3a:b0:42a:a6de:e533 with SMTP id bo26-20020a0564020b3a00b0042aa6dee533mr5513937edb.100.1652647542371; Sun, 15 May 2022 13:45:42 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-98-105.xnet.hr. [88.207.98.105]) by smtp.googlemail.com with ESMTPSA id i10-20020a50870a000000b0042617ba63cdsm4174156edb.87.2022.05.15.13.45.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 May 2022 13:45:41 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, jassisinghbrar@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Cc: Robert Marko Subject: [PATCH v4 1/6] clk: qcom: clk-alpha-pll: add support for APSS PLL Date: Sun, 15 May 2022 22:45:35 +0200 Message-Id: <20220515204540.477711-1-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org APSS PLL type will be used by the IPQ8074 APSS driver for providing the CPU core clocks and enabling CPU Frequency scaling. This is ported from the downstream 5.4 kernel. Signed-off-by: Robert Marko --- drivers/clk/qcom/clk-alpha-pll.c | 12 ++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 1 + 2 files changed, 13 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 4406cf609aae..8270363ff98e 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -154,6 +154,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_TEST_CTL_U] = 0x30, [PLL_OFF_TEST_CTL_U1] = 0x34, }, + [CLK_ALPHA_PLL_TYPE_APSS] = { + [PLL_OFF_L_VAL] = 0x08, + [PLL_OFF_ALPHA_VAL] = 0x10, + [PLL_OFF_ALPHA_VAL_U] = 0xff, + [PLL_OFF_USER_CTL] = 0x18, + [PLL_OFF_USER_CTL_U] = 0xff, + [PLL_OFF_CONFIG_CTL] = 0x20, + [PLL_OFF_CONFIG_CTL_U] = 0x24, + [PLL_OFF_TEST_CTL] = 0x30, + [PLL_OFF_TEST_CTL_U] = 0x34, + [PLL_OFF_STATUS] = 0x28, + }, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 6e9907deaf30..626fdf80336d 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -18,6 +18,7 @@ enum { CLK_ALPHA_PLL_TYPE_AGERA, CLK_ALPHA_PLL_TYPE_ZONDA, CLK_ALPHA_PLL_TYPE_LUCID_EVO, + CLK_ALPHA_PLL_TYPE_APSS, CLK_ALPHA_PLL_TYPE_MAX, }; From patchwork Sun May 15 20:45:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 573535 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35689C4332F for ; Sun, 15 May 2022 20:45:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234280AbiEOUpt (ORCPT ); Sun, 15 May 2022 16:45:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41644 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233965AbiEOUpr (ORCPT ); Sun, 15 May 2022 16:45:47 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FCE3237CE; Sun, 15 May 2022 13:45:45 -0700 (PDT) Received: by mail-ej1-x62e.google.com with SMTP id ch13so25153067ejb.12; Sun, 15 May 2022 13:45:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CVJmMjKSGPsdpVl5B7dwM8pbpVk/e6e/YzA6OtxjZig=; b=P7dGGjdNUaA0IqLlqPADFrdhjN+QY+65AfnxxdOJ92BG17pe0Db6F1DK+0XbfT9x56 sTXlhvcXcZE7U66UusoiJZrmSpN86bzHgnSj4BaHbSBPXRWOdzRj2wCChSapmcsbvNEC T3GHb9ULoHbo9tZfLuA+TcDCAgbxvDsXeVRAUEVRSDhNTjScb+D52apg3gOEEIblnV20 t66dmMgXZExdyTzO14up9vEVKwjRfS4H6z53voEUCxRw6WxPIzaugRijlrIUtvmQkxEZ IBKXqZrhlYijJ/EteeglkPZl4V7bdaX7HTzfBC7AYJfL/wUeA7lA9X4EInAzNYY/XODh x1qQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CVJmMjKSGPsdpVl5B7dwM8pbpVk/e6e/YzA6OtxjZig=; b=UGOcJnIbbMi2EGetrm5XzcaBCW/gPU8ai6QV55VwrkyCTv189DHp9GN/4APzEO7W4B LsXwqUV/4SCUBa7gNivLNDZLafCHrp16End5+LRUQeiSemR3GqQvmfNChAwRF1ugEKkC 2t0py2UFbIJJ1h4sLF7VTcXqHFt8FTkoAPdVg4lJIAJFMHZvIGdKZxAfJc1Xzg81EsaC nJBwtxyiaBbsKcjMmpnjhrYyH06uET9+7dcRp8wI4HgSI7xj5K1nicEFRlvs7+heZzhv kWfIlySNLFKFRSjQ0+zXHcrhL2qwpemdqzYsSpGekeaF2IZUotsgdPQ6JBaHFBV8Ap0v 7aiQ== X-Gm-Message-State: AOAM531z91+SNxWFm8jpcr6wEltrh03xX+2UAEArbWddcARFny5/vKPX Y3F2VJEaRxULIhflB6gR2rI= X-Google-Smtp-Source: ABdhPJwzqJKxcby/qor1KpG+PZmQynhtAuF4IqryADP1xTGOxUowbSTR18nsvDEKYxIzbfRIAlgKRg== X-Received: by 2002:a17:907:6d22:b0:6f4:85c1:5a07 with SMTP id sa34-20020a1709076d2200b006f485c15a07mr12613313ejc.733.1652647543951; Sun, 15 May 2022 13:45:43 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-98-105.xnet.hr. [88.207.98.105]) by smtp.googlemail.com with ESMTPSA id i10-20020a50870a000000b0042617ba63cdsm4174156edb.87.2022.05.15.13.45.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 May 2022 13:45:43 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, jassisinghbrar@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Cc: Robert Marko , Krzysztof Kozlowski Subject: [PATCH v4 2/6] dt-bindings: clock: Add support for IPQ8074 APSS clock controller Date: Sun, 15 May 2022 22:45:36 +0200 Message-Id: <20220515204540.477711-2-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220515204540.477711-1-robimarko@gmail.com> References: <20220515204540.477711-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add dt-binding for the IPQ8074 APSS clock controller which provides clocks to the CPU cores. Signed-off-by: Robert Marko Acked-by: Krzysztof Kozlowski --- Changes in v4: * Dual license the bindings * Update the copyright year Changes in v2: * Correct subject --- include/dt-bindings/clock/qcom,apss-ipq8074.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,apss-ipq8074.h diff --git a/include/dt-bindings/clock/qcom,apss-ipq8074.h b/include/dt-bindings/clock/qcom,apss-ipq8074.h new file mode 100644 index 000000000000..32538c9311ff --- /dev/null +++ b/include/dt-bindings/clock/qcom,apss-ipq8074.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLOCK_QCA_APSS_IPQ8074_H +#define _DT_BINDINGS_CLOCK_QCA_APSS_IPQ8074_H + +#define APSS_PLL_EARLY 0 +#define APSS_PLL 1 +#define APCS_ALIAS0_CLK_SRC 2 +#define APCS_ALIAS0_CORE_CLK 3 + +#endif From patchwork Sun May 15 20:45:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 572806 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E3A5C4321E for ; Sun, 15 May 2022 20:45:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238704AbiEOUpv (ORCPT ); Sun, 15 May 2022 16:45:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236889AbiEOUpt (ORCPT ); Sun, 15 May 2022 16:45:49 -0400 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4A46D237E3; Sun, 15 May 2022 13:45:47 -0700 (PDT) Received: by mail-ej1-x62b.google.com with SMTP id kq17so25236301ejb.4; Sun, 15 May 2022 13:45:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z4yqHabd5CdFPeT9f5nmAl+CrDATY8pyW6w/Lrkuj98=; b=aUJ9KqHDVOOuDz2nB5BMgxSxCHgO2cIv9slCWZs7RR2TMTZDwImJ9dgidaL5Y6FVXH Bh2tDpCcGXfB/BQ2h+M67P7jr268sQ2EDEGP0wKmcA+8VIX49tiZP75fBlVmP5X+iHzc e8RlN33Mwp15eZlyn6aRwgff6yDk3C0njESgFNXj+sbk2v/71edLHGbeojiGe8i9zYho T5mEsYxu8/8cbXCLL0ZMtzs9B97lOErPGZAVfxDoKuqKGN7rr8XlsDNCyjk1tLsRlwZS wTQZ1XG2ea6tpc3j8HcLZaGT9FkzKLSTByoT2kkO6VOA8cYTE3RNTEGUo4Kj8pwrMaSd vEfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z4yqHabd5CdFPeT9f5nmAl+CrDATY8pyW6w/Lrkuj98=; b=bAdaW7V+z1maxc4vU+F20jRJhu/qvd8WJO8eHkf/Ro1t3eCVWjq954FxkZY9E+xZaL 0fRWfA638VFHeuCT32CqvxqFmTVr9EOoZPn+kKBd26K4/or7hVRozP5nnRPq10tJpuyk 3RsgV1luE3GAUtpTs0ACpzcSN97tzhGbsJAQXNNoIgPeBCY9Sz0Wia6R7bLVAdUj0kui 5JajEl2HWlGhZj2EcEQIZ4ttOLkQfWDFcVA0HyrIr0V35wmx+CGL7pI4coDpiozBmgW3 xaEURWSnUhjWmBVyHKcfWivOiYi/vIJ4AVod5nqLN1cr5BS2Re1Ba/q4C7iagomIZCK6 JTsQ== X-Gm-Message-State: AOAM532WvilDPusSvO/T5wnDKOVxBTqdjcUZghP8ZWaK5fnBkMbiC0OD pK6H51UyL33tuGCQpBABjEo= X-Google-Smtp-Source: ABdhPJxtFM0rwoV6GkeSgdYjJllLtlFqhnW5QQ+C/jJUo3leaO6fNyR6TZecfRWm+VdNSOMI1m/eGQ== X-Received: by 2002:a17:907:8a0e:b0:6f5:a48:e04e with SMTP id sc14-20020a1709078a0e00b006f50a48e04emr12640412ejc.228.1652647545611; Sun, 15 May 2022 13:45:45 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-98-105.xnet.hr. [88.207.98.105]) by smtp.googlemail.com with ESMTPSA id i10-20020a50870a000000b0042617ba63cdsm4174156edb.87.2022.05.15.13.45.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 May 2022 13:45:45 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, jassisinghbrar@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Cc: Robert Marko , Ansuel Smith Subject: [PATCH v4 3/6] clk: qcom: Add IPQ8074 APSS clock controller Date: Sun, 15 May 2022 22:45:37 +0200 Message-Id: <20220515204540.477711-3-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220515204540.477711-1-robimarko@gmail.com> References: <20220515204540.477711-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org IPQ8074 APSS clock controller provides the clock for the IPQ8074 CPU cores, thus also providing support for CPU frequency scaling. It looks like they are clocked by the XO and a custom APSS type PLL. Co-developed-by: Ansuel Smith Signed-off-by: Ansuel Smith Signed-off-by: Robert Marko --- Changes in v2: * Convert to using parent-data instead of parent-names --- drivers/clk/qcom/Kconfig | 11 +++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/apss-ipq8074.c | 170 ++++++++++++++++++++++++++++++++ 3 files changed, 182 insertions(+) create mode 100644 drivers/clk/qcom/apss-ipq8074.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 00fe5f066de5..9494eb74374a 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -134,6 +134,17 @@ config IPQ_APSS_6018 Say Y if you want to support CPU frequency scaling on ipq based devices. +config IPQ_APSS_8074 + tristate "IPQ8074 APSS Clock Controller" + select IPQ_GCC_8074 + depends on QCOM_APCS_IPC || COMPILE_TEST + help + Support for APSS clock controller on IPQ8074 platforms. The + APSS clock controller manages the Mux and enable block that feeds the + CPUs. + Say Y if you want to support CPU frequency scaling on + IPQ8074 based devices. + config IPQ_GCC_4019 tristate "IPQ4019 Global Clock Controller" help diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 671cf5821af1..7b2da6dd570c 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o +obj-$(CONFIG_IPQ_APSS_8074) += apss-ipq8074.o obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o diff --git a/drivers/clk/qcom/apss-ipq8074.c b/drivers/clk/qcom/apss-ipq8074.c new file mode 100644 index 000000000000..38d03cd0ff76 --- /dev/null +++ b/drivers/clk/qcom/apss-ipq8074.c @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "clk-regmap.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-branch.h" +#include "clk-alpha-pll.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" + +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } + +enum { + P_XO, + P_GPLL0, + P_GPLL2, + P_GPLL4, + P_APSS_PLL_EARLY, + P_APSS_PLL +}; + +static struct clk_alpha_pll apss_pll_early = { + .offset = 0x5000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_APSS], + .clkr = { + .enable_reg = 0x5000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "apss_pll_early", + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xo", .name = "xo" + }, + .num_parents = 1, + .ops = &clk_alpha_pll_huayra_ops, + }, + }, +}; + +static struct clk_alpha_pll_postdiv apss_pll = { + .offset = 0x5000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_APSS], + .width = 2, + .clkr.hw.init = &(struct clk_init_data){ + .name = "apss_pll", + .parent_hws = (const struct clk_hw *[]){ + &apss_pll_early.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + }, +}; + +static const struct clk_parent_data parents_apcs_alias0_clk_src[] = { + { .fw_name = "xo", .name = "xo" }, + { .fw_name = "gpll0", .name = "gpll0" }, + { .fw_name = "gpll2", .name = "gpll2" }, + { .fw_name = "gpll4", .name = "gpll4" }, + { .hw = &apss_pll.clkr.hw }, + { .hw = &apss_pll_early.clkr.hw }, +}; + +static const struct parent_map parents_apcs_alias0_clk_src_map[] = { + { P_XO, 0 }, + { P_GPLL0, 4 }, + { P_GPLL2, 2 }, + { P_GPLL4, 1 }, + { P_APSS_PLL, 3 }, + { P_APSS_PLL_EARLY, 5 }, +}; + +struct freq_tbl ftbl_apcs_alias0_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(403200000, P_APSS_PLL_EARLY, 1, 0, 0), + F(806400000, P_APSS_PLL_EARLY, 1, 0, 0), + F(1017600000, P_APSS_PLL_EARLY, 1, 0, 0), + F(1382400000, P_APSS_PLL_EARLY, 1, 0, 0), + F(1651200000, P_APSS_PLL_EARLY, 1, 0, 0), + F(1843200000, P_APSS_PLL_EARLY, 1, 0, 0), + F(1920000000, P_APSS_PLL_EARLY, 1, 0, 0), + F(2208000000UL, P_APSS_PLL_EARLY, 1, 0, 0), + { } +}; + +struct clk_rcg2 apcs_alias0_clk_src = { + .cmd_rcgr = 0x0050, + .freq_tbl = ftbl_apcs_alias0_clk_src, + .hid_width = 5, + .parent_map = parents_apcs_alias0_clk_src_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "apcs_alias0_clk_src", + .parent_data = parents_apcs_alias0_clk_src, + .num_parents = ARRAY_SIZE(parents_apcs_alias0_clk_src), + .ops = &clk_rcg2_ops, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_branch apcs_alias0_core_clk = { + .halt_reg = 0x0058, + .halt_bit = 31, + .clkr = { + .enable_reg = 0x0058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "apcs_alias0_core_clk", + .parent_hws = (const struct clk_hw *[]){ + &apcs_alias0_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | + CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *apss_ipq8074_clks[] = { + [APSS_PLL_EARLY] = &apss_pll_early.clkr, + [APSS_PLL] = &apss_pll.clkr, + [APCS_ALIAS0_CLK_SRC] = &apcs_alias0_clk_src.clkr, + [APCS_ALIAS0_CORE_CLK] = &apcs_alias0_core_clk.clkr, +}; + +static const struct regmap_config apss_ipq8074_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x5ffc, + .fast_io = true, +}; + +static const struct qcom_cc_desc apss_ipq8074_desc = { + .config = &apss_ipq8074_regmap_config, + .clks = apss_ipq8074_clks, + .num_clks = ARRAY_SIZE(apss_ipq8074_clks), +}; + +static int apss_ipq8074_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!regmap) + return -ENODEV; + + return qcom_cc_really_probe(pdev, &apss_ipq8074_desc, regmap); +} + +static struct platform_driver apss_ipq8074_driver = { + .probe = apss_ipq8074_probe, + .driver = { + .name = "qcom,apss-ipq8074-clk", + }, +}; + +module_platform_driver(apss_ipq8074_driver); + +MODULE_DESCRIPTION("Qualcomm IPQ8074 APSS clock driver"); +MODULE_LICENSE("GPL"); From patchwork Sun May 15 20:45:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 573534 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0842FC433F5 for ; Sun, 15 May 2022 20:45:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238721AbiEOUpw (ORCPT ); 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[88.207.98.105]) by smtp.googlemail.com with ESMTPSA id i10-20020a50870a000000b0042617ba63cdsm4174156edb.87.2022.05.15.13.45.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 May 2022 13:45:47 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, jassisinghbrar@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Cc: Robert Marko Subject: [PATCH v4 4/6] mailbox: qcom-apcs-ipc: add IPQ8074 APSS clock controller support Date: Sun, 15 May 2022 22:45:38 +0200 Message-Id: <20220515204540.477711-4-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220515204540.477711-1-robimarko@gmail.com> References: <20220515204540.477711-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org IPQ8074 has the APSS clock controller utilizing the same register space as the APCS, so provide access to the APSS utilizing a child device like IPQ6018 does as well, but just by utilizing the IPQ8074 specific APSS clock driver. Also, APCS register space in IPQ8074 is 0x6000 so max_register needs to be updated to 0x5FFC. Signed-off-by: Robert Marko --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index 80a54d81412e..b3b9debf5673 100644 --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c @@ -33,6 +33,10 @@ static const struct qcom_apcs_ipc_data ipq6018_apcs_data = { .offset = 8, .clk_name = "qcom,apss-ipq6018-clk" }; +static const struct qcom_apcs_ipc_data ipq8074_apcs_data = { + .offset = 8, .clk_name = "qcom,apss-ipq8074-clk" +}; + static const struct qcom_apcs_ipc_data msm8916_apcs_data = { .offset = 8, .clk_name = "qcom-apcs-msm8916-clk" }; @@ -57,7 +61,7 @@ static const struct regmap_config apcs_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, - .max_register = 0x1008, + .max_register = 0x5FFC, .fast_io = true, }; @@ -142,7 +146,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev) /* .data is the offset of the ipc register within the global block */ static const struct of_device_id qcom_apcs_ipc_of_match[] = { { .compatible = "qcom,ipq6018-apcs-apps-global", .data = &ipq6018_apcs_data }, - { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &msm8994_apcs_data }, + { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq8074_apcs_data }, { .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data }, { .compatible = "qcom,msm8939-apcs-kpss-global", .data = &msm8916_apcs_data }, { .compatible = "qcom,msm8953-apcs-kpss-global", .data = &msm8994_apcs_data }, From patchwork Sun May 15 20:45:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 572805 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49CA0C433F5 for ; Sun, 15 May 2022 20:46:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238742AbiEOUp5 (ORCPT ); Sun, 15 May 2022 16:45:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238711AbiEOUpw (ORCPT ); Sun, 15 May 2022 16:45:52 -0400 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0CF3237F7; Sun, 15 May 2022 13:45:50 -0700 (PDT) Received: by mail-ed1-x52f.google.com with SMTP id ba17so15978626edb.5; Sun, 15 May 2022 13:45:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kTqxGKRaQ+4R4vGFv2ndzSh2OvA6/IVMbt55ouGGu20=; b=MSt+yA9UObHIij1xVVg4RTUH2jMag/OwB28Wu8QfsAQNaTK5nf1ksC/oYINGPWVSqV mfi6QMLICcODgE3o6MD4Tb/eJcUwC4eoP/dbUIiJzBAin1m9tD+0zUFHHKNRnKp1BrG0 JCJkXDvKaOMuhCCtjDS3h/p/v9SvjfdADcoTv757ggs3OUtzlsyG9gV/SC+WYWeCjWYv 2CPi4zA6PCyNNAoMI5Ok++98pHxe69ywYrkFiVW6J3F3d0sKTlKNTeJib1ZyEvICd4zY mB5W+3V02/NNgqxBZ47FeKMBx0LMFuRIOFn130aCdx5J6pVkK0JJXuKcO+hJy+vj5zXT sv5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kTqxGKRaQ+4R4vGFv2ndzSh2OvA6/IVMbt55ouGGu20=; b=jOAZ2GMKwn4sgxtDF7OsYwi002lZwQSjXztXss34tZuPUvobjS1BHsSZYDrUQGdDaX IPrmFjViCa6YhOrEdm9fPG/f+hGnkRwfAvc+KHqp+TYAG867TL+I7dSzWPzMnEMc4mYq nmT1uf2IoIDZdqUsB/xSIASktuInS0X5eClrKBg5/31AlAkrLRpHYCCUMHzM21Tag79f bO863zF1Yque1qf0v225ubjXp4C/sx0ozeNIw/3hyh0raNwxTeFngvFDz3I51JHvWZtm Fdy7BHwKiwbgjwMIjY9M9zpVj9wWl1VyzUzM+OAharVEZqKbETPDDA4lVFBcvF0DPSuU GqNQ== X-Gm-Message-State: AOAM532Tx6ODwdDrKsnlbdVcwirJXy6taSROKE/u2oXL6aqEjFALqihW x2QMWByGOttukIMc68CtGDY= X-Google-Smtp-Source: ABdhPJyOhpjy4y4MN973lMI8n7XZxjzdpJA17yIuMf1aZuyrIVc8kWO1k5snlIzepWrct8pGphQsOg== X-Received: by 2002:a05:6402:1910:b0:428:1817:6f2f with SMTP id e16-20020a056402191000b0042818176f2fmr9839144edz.354.1652647549502; Sun, 15 May 2022 13:45:49 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-98-105.xnet.hr. [88.207.98.105]) by smtp.googlemail.com with ESMTPSA id i10-20020a50870a000000b0042617ba63cdsm4174156edb.87.2022.05.15.13.45.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 May 2022 13:45:49 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, jassisinghbrar@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Cc: Robert Marko , Krzysztof Kozlowski Subject: [PATCH v4 5/6] dt-bindings: mailbox: qcom: set correct #clock-cells Date: Sun, 15 May 2022 22:45:39 +0200 Message-Id: <20220515204540.477711-5-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220515204540.477711-1-robimarko@gmail.com> References: <20220515204540.477711-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org IPQ6018 and IPQ8074 require #clock-cells to be set to 1 as their APSS clock driver provides multiple clock outputs. So allow setting 1 as #clock-cells and check that its set to 1 for IPQ6018 and IPQ8074, check others for 0 as its currently. Signed-off-by: Robert Marko Reviewed-by: Krzysztof Kozlowski --- Changes in v3: * Drop not needed blank line Changes in v2: * Correct subject name --- .../bindings/mailbox/qcom,apcs-kpss-global.yaml | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index 3b5ba7ecc19d..95ecb84e3278 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -50,7 +50,7 @@ properties: const: 1 '#clock-cells': - const: 0 + enum: [0, 1] clock-names: minItems: 2 @@ -96,6 +96,21 @@ allOf: properties: clocks: maxItems: 3 + - if: + properties: + compatible: + enum: + - qcom,ipq6018-apcs-apps-global + - qcom,ipq8074-apcs-apps-global + then: + properties: + '#clock-cells': + const: 1 + else: + properties: + '#clock-cells': + const: 0 + examples: # Example apcs with msm8996 From patchwork Sun May 15 20:45:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 573533 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32004C43217 for ; Sun, 15 May 2022 20:46:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237847AbiEOUqG (ORCPT ); Sun, 15 May 2022 16:46:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238731AbiEOUpy (ORCPT ); Sun, 15 May 2022 16:45:54 -0400 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9817237DE; Sun, 15 May 2022 13:45:52 -0700 (PDT) Received: by mail-ed1-x534.google.com with SMTP id i40so967481eda.7; Sun, 15 May 2022 13:45:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=u5JzkCm9MWsKf/jb76u0rZ0O4lmlB8YYfn5r9Xj1Czg=; b=E1eKjexHxIwNHIOp7Cu3KTyTWAzm0tXz9Tyqdzx6ZHWdhg5YjSVhuu5yAwANvZa2K+ V4I+JwrkJGo6tYyb+D7UdVEl/6Hiqw29nKDgx6UAhwg1zSuP1pjyTjjLdjQeVJnoLKnv +S9st70jRSFgJ7z/bNrzChhqWHaptKGQ2vd9mgZ9Ic0SbqgOv+c/L0vHctNP0F6BWCST xx98E8HeFY8SXdPdb5qbnZhV04Fqu/j8zy9J9HNViFnsIvV7G4TZR+k4fhSo9ZNo0NkK JSD6NmFCCxCLhEYJyQsM2hYq7ew2mACcK7hnTanyWaNhnCIqmOCRNaF68U/j/FHE0B3l ni4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u5JzkCm9MWsKf/jb76u0rZ0O4lmlB8YYfn5r9Xj1Czg=; b=eO4UocOllntrmFWclAsDh8WwFuf07WGtzjvfelJ3ZjTVLz8VAViO+RIoj0QUW7Vxzd xvin67GdoSObmAut9xdws7HEolikyPBm8JBkka0GaxjVhl/4ippX+9y1gCa+vvFxxgOV d3YWeAELkYb0XuBBSdzdi42NO1R3f0Q4Ry0h9S1qlj4bu7pe0z3FIKivrmcF2Oqw828r O7UKXLGIJMsBGyg9kACdTFT99vuEatPo8P7GLzr8kUjIf+ju2wPl+Cxptgu+1vUM6R75 ukGFUF2grryOsT9LYSyHtgzSgZ+qSCrBtXgjy1Gr7Q/cQLaYBenas5vVqxSf6vK5S53g gaBQ== X-Gm-Message-State: AOAM533JZGKzEveV+Hc+Ac7NNxJaHO0krPtKlblOIgFVe5B+V8U8K2kh ndLhjJaaMFJaJZHX2QdIAgA= X-Google-Smtp-Source: ABdhPJyNjp9vI45/J9yukuOOdF6/Ay9N0jvqseMulDkHBqImglINKegNZN33wTcc2jZiQWJTbFrp7g== X-Received: by 2002:a05:6402:2753:b0:423:3895:7031 with SMTP id z19-20020a056402275300b0042338957031mr9779158edd.170.1652647551248; Sun, 15 May 2022 13:45:51 -0700 (PDT) Received: from fedora.robimarko.hr (dh207-98-105.xnet.hr. [88.207.98.105]) by smtp.googlemail.com with ESMTPSA id i10-20020a50870a000000b0042617ba63cdsm4174156edb.87.2022.05.15.13.45.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 May 2022 13:45:50 -0700 (PDT) From: Robert Marko To: agross@kernel.org, bjorn.andersson@linaro.org, jassisinghbrar@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Cc: Robert Marko Subject: [PATCH v4 6/6] arm64: dts: ipq8074: add APCS node Date: Sun, 15 May 2022 22:45:40 +0200 Message-Id: <20220515204540.477711-6-robimarko@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220515204540.477711-1-robimarko@gmail.com> References: <20220515204540.477711-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org APCS now has support for providing the APSS clocks as the child device for IPQ8074. So, add the required DT node for it as it will later be used as the CPU clocksource. Signed-off-by: Robert Marko --- Changes in v3: * Node does not currently exist in the upstream kernel, so add it instead of modifying. --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 0bc21b0c177f..271eb733f2c8 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -886,5 +886,13 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ "axi_m_sticky"; status = "disabled"; }; + + apcs_glb: mailbox@b111000 { + compatible = "qcom,ipq8074-apcs-apps-global"; + reg = <0x0b111000 0x6000>; + + #clock-cells = <1>; + #mbox-cells = <1>; + }; }; };