From patchwork Sat May 14 14:10:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 572567 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 281DBC43217 for ; Sat, 14 May 2022 14:10:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232929AbiENOKr (ORCPT ); Sat, 14 May 2022 10:10:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232920AbiENOKq (ORCPT ); Sat, 14 May 2022 10:10:46 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20209140DD for ; Sat, 14 May 2022 07:10:45 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id u23so18948972lfc.1 for ; Sat, 14 May 2022 07:10:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/VZ6iM+D39eVdWgv1scNQubHpBETElEybwIos3+NtQM=; b=kl2Uu8Hbp0i49wimsGghozN+dxlgQ1xIvgKS9zI+59VYaViK5frBfXArPAQY0DArf+ pPwwVBvzNZdcLbHEHe2LZo/Oe+oZLlo7w1NvB5nKTq30igDQ+7yehd8YCJv5osYx0QXh zBo6ssOA6GMy8JSm1OWc/8mbmMSlggdttFr9thpk4Ppsq/QLWRlZ9+YpOwpU9mqYnEsL uuKfDMTZX25IYaEXCr+GHoYzdfwuwuCxCQqYWAWDNbwd4LwcHwtvvnCo2xWg5EZFmmaB EkgImV3tNl3Nz/y9P7qdbqso7E7LJGcJtiODd/eZX70dqvK/fKtzT5K5JiaBWqQynPYe hQaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/VZ6iM+D39eVdWgv1scNQubHpBETElEybwIos3+NtQM=; b=F8vSuPgcTDqPgYT0gYnh2LTlhF7X3+ijWl0PfI9eB8/4G4q12Nb73IQzFMgAnXqWR6 ebjxVe0Z5a7UeN6ies1UpB9XaLUNqTZpoj97xPLudwBBfFGbey18mEtnOm/WqwTyNW7E ZWC7bMeVwsCp1nJJTYiVCVDbdSqd4i3C9tE97UG0mNxwkEThbsnNQPNA885666tbmaau lQWXuvqBawGhrCZIpbAb1P8/VEQfCfd2MJ8UtLOFy0laOq78k0LaQewpyR7gCYkWi1hY zwJkgAB5eHyZ/LfS7d087B+sIjMQBsM73TV0dLrdRz/5YovHFz8Z5ewxE55Kq5ZfU/2E B6LQ== X-Gm-Message-State: AOAM530FRJVH3m/q048Xbrl/1n61J1XJMVttved2zkCnW4+MqtP/B1Sn K28tezRSFVJJ+SClMBhah2wZUA== X-Google-Smtp-Source: ABdhPJxbgzHToqjWN4TNa/GSiCdj7cTiaJMnuNQbXIW1aBNAJSbiWKAUSNl+Hp+JOgMGviJ7E8DK3A== X-Received: by 2002:ac2:4111:0:b0:472:f24c:e759 with SMTP id b17-20020ac24111000000b00472f24ce759mr6998851lfi.612.1652537443420; Sat, 14 May 2022 07:10:43 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id x9-20020a05651c104900b0024f3d1daedasm845912ljm.98.2022.05.14.07.10.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 May 2022 07:10:42 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 01/12] arm64: dts: qcom: sdm630: disable dsi0/dsi0_phy by default Date: Sat, 14 May 2022 17:10:30 +0300 Message-Id: <20220514141041.3158521-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220514141041.3158521-1-dmitry.baryshkov@linaro.org> References: <20220514141041.3158521-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Follow the typical practice and keep DSI0/DSI0 PHY disabled by default. They should be enabled in the board DT files. No existing boards use them at this moment. Suggested-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 240293592ef9..8697d40e9b74 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1559,6 +1559,8 @@ dsi0: dsi@c994000 { phys = <&dsi0_phy>; phy-names = "dsi"; + status = "disabled"; + ports { #address-cells = <1>; #size-cells = <0>; @@ -1592,6 +1594,7 @@ dsi0_phy: dsi-phy@c994400 { clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; clock-names = "iface", "ref"; + status = "disabled"; }; }; From patchwork Sat May 14 14:10:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 572826 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37268C433F5 for ; Sat, 14 May 2022 14:10:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232943AbiENOKs (ORCPT ); Sat, 14 May 2022 10:10:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232920AbiENOKs (ORCPT ); Sat, 14 May 2022 10:10:48 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0441C14030 for ; Sat, 14 May 2022 07:10:46 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id u23so18949035lfc.1 for ; Sat, 14 May 2022 07:10:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ypxafSXytWa1pPBeHJ41K2y3Cfr7QvnghKr6SvtMtAA=; b=lwl1u/CLn67GrQl8k1xpyGiVF9l1USF+zHwYPOpibgw0rG86X3JASfLk2olkq1YeFO uf/aDxFJ50K8pI+AlksFUQTW2iPJSh/XCj13GjPkRsS9PQ0sMPoZesx+Ag9zhNbDZI68 7SgleCDJk8rP6FNTiXHfzj5NdujLnP9P+e4zHHgau4PgGHXUaYkjh8kjQ0lWSzqE1cEo OvQlsuMl88FicL6wwDiMZWWr2oV9BmrpbRxZeQHFQkgINc7GLsZy1Ffxuh0S2dSlhjOz R3e8EiQmAF8CazrQmDzC/d27ZlATUTS2Z/1Xn/wf/8z7umKEoyOm1yljteU2b4sq6kPr bHVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ypxafSXytWa1pPBeHJ41K2y3Cfr7QvnghKr6SvtMtAA=; b=GG69PGjt2J1+ucC9QIzKlOFeZIEXzy8Jps5E4tbT24M7wQZj4BXT/52E0+lKPT5Mz+ BrGec09g4blmHciMnjK1eY5wMXSQmd58/z548AA413OtnDTxrPKoPXq4cdVtQ2hcahnM HPGMsypkRnTOBb5gxcV3SGRmUJlA5LaR+U4o9czp0TEhWZit2hVlqd4NtSxMDvHjR5lA dEmuG63nAAFij5j0BjT27dfnunfIJ8GjhbFnb9X49YqdxQjpW7Bc8lqssTYPOjMZQgWr FcXiR/eV9WcJBEwckZQ27O72vIjRQ95HUxjseXOLV9BJND2jU38Smp708AmZr1mLZ761 A34Q== X-Gm-Message-State: AOAM531Y00Y2un/Y0VpcuHjPXGOMUpOLgPmisumt1Ww2M05hhljRPfiy mD+N2ghAf1Zyl/WT6LeGDhB5Qg== X-Google-Smtp-Source: ABdhPJwgG1GZ4Bypt8jajdAGNK3nhdf5rfnXcTDCYaTEtqDY/IQO4vcNj/stGmw35pT01mYQoyzjUQ== X-Received: by 2002:a05:6512:150a:b0:474:bb9:5174 with SMTP id bq10-20020a056512150a00b004740bb95174mr6455136lfb.207.1652537444376; Sat, 14 May 2022 07:10:44 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id x9-20020a05651c104900b0024f3d1daedasm845912ljm.98.2022.05.14.07.10.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 May 2022 07:10:43 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 02/12] arm64: dts: qcom: sdm660: disable dsi1/dsi1_phy by default Date: Sat, 14 May 2022 17:10:31 +0300 Message-Id: <20220514141041.3158521-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220514141041.3158521-1-dmitry.baryshkov@linaro.org> References: <20220514141041.3158521-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Follow the typical practice and keep DSI1/DSI1 PHY disabled by default. They should be enabled in the board DT files. No existing boards use them at this moment. Reviewed-by: Marijn Suijten Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm660.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi index eccf6fde16b4..023b0ac4118c 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -192,6 +192,8 @@ dsi1: dsi@c996000 { phys = <&dsi1_phy>; phy-names = "dsi"; + status = "disabled"; + ports { #address-cells = <1>; #size-cells = <0>; @@ -225,6 +227,7 @@ dsi1_phy: dsi-phy@c996400 { clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "ref"; + status = "disabled"; }; }; From patchwork Sat May 14 14:10:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 572566 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0729EC43219 for ; Sat, 14 May 2022 14:10:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232920AbiENOKt (ORCPT ); Sat, 14 May 2022 10:10:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232934AbiENOKs (ORCPT ); Sat, 14 May 2022 10:10:48 -0400 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BA680140EC for ; Sat, 14 May 2022 07:10:46 -0700 (PDT) Received: by mail-lj1-x22f.google.com with SMTP id l19so13313258ljb.7 for ; Sat, 14 May 2022 07:10:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Tuq5sCaVtmkjPi9RkbWXYl4iAUGc0Sy3jGc43YOB5ng=; b=lnRUNjD5lUvoOtp5wPhBZCOmV9eqAVPdpQ1P5QTMNXOxx5/27dToQK5gZYcsvsctfm Kcrf6lZiybF50ADpmhaAAAM2hWWs3sqN2XdWuVyylIKAvs4atpUYhUAMWm2ZSWHRowYT oacCXDQmxgqcEe5Gj/6D5UC78Ig0YzbfdlA4CYT/X5hdubSN4AouaW1JCwQLNPPoj8gl ZPMdw2/6pVTyYVOem32BPH/sfFtDxu8L+WhzE2TsNZFt/BmynzIZ3o/EaCgwXyydasma qO20keiFbw6HEW98pXMFwApj6UwSTI8+TGbQCCjROVREJZlCltCt5CuJovRyE3AT1GwL dnfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Tuq5sCaVtmkjPi9RkbWXYl4iAUGc0Sy3jGc43YOB5ng=; b=aOq3E1MwseQiz2hulRU3kek9wz9VP3gQ1+a4aEeZBSyuqVVdiaNfB1tRjSpUrXNgc7 wz8xXF0jRFCIDkmbT/7TFoTNZVIDo0yuCFVS35ijtdqhEVg0C92wNy9StUWVxYQ1swxo mtNw7RjDbt27k/7YDixMvVBOQ6TGLjBK99k2nav7CLmEVb2KisFMFsNOoCkful58bLX5 tqsTiHNfM2uyjg5uFFhKOd5G/cqmO+rNNKs6yVJTTEa6FJ2D1xaOGiREOc1RbS6b1NHP EyUZD8Cot7+TuR1nskQ31rTfHBrkapry59HBWin893PWTVIdui+kjN5vCEq0tTQQ12rI azDQ== X-Gm-Message-State: AOAM5335BzmMx+dsNd7TBh84BRBfooti5MchvBFjLfM61wbzextNvh9u La37L3KYMah1ofdABkfhqC9nSA== X-Google-Smtp-Source: ABdhPJwwTWgZshaJf/ToGct2p5ekmmYJA1mT9ow/zKUwY3qdnvEI6m18k3Ay1+9o6CsnWif5aArP5g== X-Received: by 2002:a2e:978c:0:b0:250:8db3:d1cc with SMTP id y12-20020a2e978c000000b002508db3d1ccmr6052669lji.370.1652537445073; Sat, 14 May 2022 07:10:45 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id x9-20020a05651c104900b0024f3d1daedasm845912ljm.98.2022.05.14.07.10.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 May 2022 07:10:44 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 03/12] arm64: dts: qcom: sdm630: disable GPU by default Date: Sat, 14 May 2022 17:10:32 +0300 Message-Id: <20220514141041.3158521-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220514141041.3158521-1-dmitry.baryshkov@linaro.org> References: <20220514141041.3158521-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The SoC's device tree file disables gpucc and adreno's SMMU by default. So let's disable the GPU too. Moreover it looks like SMMU might be not usable without additional patches (which means that GPU is unusable too). No board uses GPU at this moment. Fixes: 5cf69dcbec8b ("arm64: dts: qcom: sdm630: Add Adreno 508 GPU configuration") Reviewed-by: Konrad Dybcio Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 8697d40e9b74..e8bb170e8b2f 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1050,6 +1050,8 @@ adreno_gpu: gpu@5000000 { operating-points-v2 = <&gpu_sdm630_opp_table>; + status = "disabled"; + gpu_sdm630_opp_table: opp-table { compatible = "operating-points-v2"; opp-775000000 { From patchwork Sat May 14 14:10:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 572825 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEACBC4321E for ; Sat, 14 May 2022 14:10:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232940AbiENOKt (ORCPT ); Sat, 14 May 2022 10:10:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232938AbiENOKs (ORCPT ); Sat, 14 May 2022 10:10:48 -0400 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9421B140D5 for ; Sat, 14 May 2022 07:10:47 -0700 (PDT) Received: by mail-lf1-x12f.google.com with SMTP id bu29so19031221lfb.0 for ; Sat, 14 May 2022 07:10:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M0l8uf13lS8T2BMe8oGUirk3JiCk+Q/7ugdeXN9BOAM=; b=U8hSAUb8DK2WBaCc/mVtKuRoBrYqxsph2Kt1kxzCH08QEOaPvN1hbyyaqdSAv+dUsB k7WLZIWrXdKEtfGJRBF3Lnd25XzhdERyQ9h2wCpfHRfwaTg86kIbnXKbAjEZXKU9YVi3 pwJbDIzYVjTBGDUsBNZs+Qb6TqaWo5rFf1uEJ3fY+p4SOHP5GWaM4/pvrI1bD1Rq60cU 3K++xLMmYGJa5L+0ToqPvhXIPcStq7BfixJ5eg6h2qd9uTx2tl+VdnPLMSUswBN32j9M 80z/TZZl0XDLYtfLkIwof/w33itntUCW06aTaavWHJtLPcTdRoClamlPAkrw/P4sRmyT 6nxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M0l8uf13lS8T2BMe8oGUirk3JiCk+Q/7ugdeXN9BOAM=; b=MyQtAZGCTNPw0LDw4J3VfWAB4by5K/somEyNi9unxuwKC19o3VpGSmaB8Y+9BIz471 kP0cK9YQBxaxBEYQiVJK0nrmNSSxxqwlgIWH00GgR/iEk8hfQX83E+pbj0i9KLvY2EbF I3WyZUirN3+8ipmQtw8cKQmuMgGo0zHespGdbGaovv2kUO17LYPTY3BZ2YHSxtGC4Ho/ MRbiPcXGhIo6RJkTMzhi6sD4W3FHJO0b/k0Kf+vL7nrNKTnxQo8qJ3Qc3hhkQFm7cBFM WALH8VLFbe3cespIT+6miXMtK69Hp/njlRf1p5PT6h7GVfAkZOITEaLSxCitDdeeoPT8 866w== X-Gm-Message-State: AOAM533JKJ/sPHveq2ondh7weJdomH1ZgADbuqz1vEmHZqXgf8zS1fEt 2CBTssjQ7kfMah4V1kknbYIlPg== X-Google-Smtp-Source: ABdhPJxHtrOggywCH1D3tFl4UkhhWN6SbJ40OrZovjcJtDH7dPrYNKzffiIFlKGTNoG2ZHvnzwPJzA== X-Received: by 2002:a05:6512:3b28:b0:473:b9ec:187e with SMTP id f40-20020a0565123b2800b00473b9ec187emr6866220lfv.536.1652537445942; Sat, 14 May 2022 07:10:45 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id x9-20020a05651c104900b0024f3d1daedasm845912ljm.98.2022.05.14.07.10.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 May 2022 07:10:45 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 04/12] arm64: dts: qcom: sdm630: fix the qusb2phy ref clock Date: Sat, 14 May 2022 17:10:33 +0300 Message-Id: <20220514141041.3158521-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220514141041.3158521-1-dmitry.baryshkov@linaro.org> References: <20220514141041.3158521-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org According to the downstram DT file, the qusb2phy ref clock should be GCC_RX0_USB2_CLKREF_CLK, not GCC_RX1_USB2_CLKREF_CLK. Fixes: c65a4ed2ea8b ("arm64: dts: qcom: sdm630: Add USB configuration") Cc: Konrad Dybcio Reviewed-by: Konrad Dybcio Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index e8bb170e8b2f..5be0ec06ed86 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1262,7 +1262,7 @@ qusb2phy: phy@c012000 { #phy-cells = <0>; clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_RX1_USB2_CLKREF_CLK>; + <&gcc GCC_RX0_USB2_CLKREF_CLK>; clock-names = "cfg_ahb", "ref"; resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; From patchwork Sat May 14 14:10:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 572565 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8B05C4332F for ; Sat, 14 May 2022 14:11:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232942AbiENOKv (ORCPT ); Sat, 14 May 2022 10:10:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45750 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232956AbiENOKt (ORCPT ); Sat, 14 May 2022 10:10:49 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AB38140C1 for ; Sat, 14 May 2022 07:10:48 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id bu29so19031264lfb.0 for ; Sat, 14 May 2022 07:10:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GI298Kg9rc4h34nf3DAQdxeYL6loj33xP/T6q0BntqI=; b=liUhwWaOI+8GpSiMpcnF4elqYgD3fClPppVOUI0yqkJbxepo1vAKumyBmwi/rIF8+3 5wY+f/xXyovKOzst6Yk1keLP7CndK/v3xpIUUOXnDyRGxOQTn3NrJLp6oYcbO2jgOYsr 0SoI34hyyjnIInD9OWEhAlM/5IVLONRaDwZra4+xcb6l73kYKTwNHHnQGV3vWTJxjP1/ ybNU8KEevi+WC+fvffXwbYwi6q87KKs/371JygH+L4Ux7WYlcyZtbKmSx6gk5Wv9e9jC 4cNBuGvygwTmyv6xySi2J5q1uUDMj0/y+H1tNyYDqKxRcSnF2EVWEIMQzZ9hl4Vrq25h 2miA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GI298Kg9rc4h34nf3DAQdxeYL6loj33xP/T6q0BntqI=; b=rH0Roe4866Cy734nBNa5yPIkgBgE7/AB1dzzpUwdrkHAB112yiofYuEfGKgv4rBplZ aiMuJAb6016E30B33zzN8J2vMB/16ObgmVk7MiL24HIHnKwemhXQbEadIRFLbATVglWZ 0qZncqhLJG8EDvnTdNc5qhMaCyFP7cIeo/Jv8vwbD1vZPIMOmApPwwIyfAWdy+mZuq/H DW55gHqgThLc/HlCi3RBMV/yMP6znWvKEbpqTtokBpoz0iI2iiMHFuwYVE3bmQ4YIAOZ O5TdaOUFUevtNNVa80KUCsRvPRLqamGZBs6ry0DEIWDu/Hd5D6xPnHo5v0XGhAvjkUht 7HiA== X-Gm-Message-State: AOAM530382dfOadFKNU4rJwHdD/EWMeIIr4J1DgGtHmMrNrHJEC3Aj7R cjSI9EU6vSp37/x897bNEgYoag== X-Google-Smtp-Source: ABdhPJzsl1YH8jYVIh2DSLs9a1OJoWcrwsk3ak1Iqj7QIitfzp79NqHlkyy8PYIOVx0Q9cquYQ5A8w== X-Received: by 2002:a19:fc0e:0:b0:471:ff7d:ab35 with SMTP id a14-20020a19fc0e000000b00471ff7dab35mr6899089lfi.345.1652537446703; Sat, 14 May 2022 07:10:46 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id x9-20020a05651c104900b0024f3d1daedasm845912ljm.98.2022.05.14.07.10.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 May 2022 07:10:46 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 05/12] arm64: dts: qcom: sdm630: rename qusb2phy to qusb2phy0 Date: Sat, 14 May 2022 17:10:34 +0300 Message-Id: <20220514141041.3158521-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220514141041.3158521-1-dmitry.baryshkov@linaro.org> References: <20220514141041.3158521-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In preparation to adding second USB host/PHY pair, change first USB PHY's label to qusb2phy0. Suggested-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm630.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 42af1fade461..00baacf28c63 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -224,7 +224,7 @@ &pon_resin { linux,code = ; }; -&qusb2phy { +&qusb2phy0 { status = "okay"; vdd-supply = <&vreg_l1b_0p925>; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 5be0ec06ed86..eb8504e5735c 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1250,13 +1250,13 @@ usb3_dwc3: usb@a800000 { * haven't seen any devices making use of it. */ maximum-speed = "high-speed"; - phys = <&qusb2phy>; + phys = <&qusb2phy0>; phy-names = "usb2-phy"; snps,hird-threshold = /bits/ 8 <0>; }; }; - qusb2phy: phy@c012000 { + qusb2phy0: phy@c012000 { compatible = "qcom,sdm660-qusb2-phy"; reg = <0x0c012000 0x180>; #phy-cells = <0>; diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index dcbaacf18f66..9280c1f0c334 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -103,7 +103,7 @@ &pon_resin { linux,code = ; }; -&qusb2phy { +&qusb2phy0 { status = "okay"; vdd-supply = <&vreg_l1b_0p925>; From patchwork Sat May 14 14:10:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 572563 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A74A2C433FE for ; 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Sat, 14 May 2022 07:10:47 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 06/12] arm64: dts: qcom: sdm630: add second (HS) USB host support Date: Sat, 14 May 2022 17:10:35 +0300 Message-Id: <20220514141041.3158521-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220514141041.3158521-1-dmitry.baryshkov@linaro.org> References: <20220514141041.3158521-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add DT entries for the second DWC3 USB host, which is limited to the USB2.0 (HighSpeed), and the corresponding QUSB PHY. Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 55 ++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index eb8504e5735c..2b5dbc12bdf8 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1270,6 +1270,20 @@ qusb2phy0: phy@c012000 { status = "disabled"; }; + qusb2phy1: phy@c014000 { + compatible = "qcom,sdm660-qusb2-phy"; + reg = <0x0c014000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_RX1_USB2_CLKREF_CLK>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + nvmem-cells = <&qusb2_hstx_trim>; + status = "disabled"; + }; + sdhc_2: sdhci@c084000 { compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; reg = <0x0c084000 0x1000>; @@ -1375,6 +1389,47 @@ opp-384000000 { }; }; + usb2: usb@c2f8800 { + compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; + reg = <0x0c2f8800 0x400>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>; + clock-names = "cfg_noc", "core", + "mock_utmi", "sleep"; + + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>; + assigned-clock-rates = <19200000>, <60000000>; + + interrupts = ; + interrupt-names = "hs_phy_irq"; + + qcom,select-utmi-as-pipe-clk; + + resets = <&gcc GCC_USB_20_BCR>; + + usb2_dwc3: usb@c200000 { + compatible = "snps,dwc3"; + reg = <0x0c200000 0xc8d0>; + interrupts = ; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + /* This is the HS-only host */ + maximum-speed = "high-speed"; + phys = <&qusb2phy1>; + phy-names = "usb2-phy"; + snps,hird-threshold = /bits/ 8 <0>; + }; + }; + mmcc: clock-controller@c8c0000 { compatible = "qcom,mmcc-sdm630"; reg = <0x0c8c0000 0x40000>; From patchwork Sat May 14 14:10:36 2022 Content-Type: text/plain; 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According to the downstream GPU uses MASTER_OXILI here, <&bimc 1 ...>. Fixes: 5cf69dcbec8b ("arm64: dts: qcom: sdm630: Add Adreno 508 GPU configuration") Reported-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 2b5dbc12bdf8..6d0bc9e8fb5b 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1045,7 +1045,7 @@ adreno_gpu: gpu@5000000 { nvmem-cells = <&gpu_speed_bin>; nvmem-cell-names = "speed_bin"; - interconnects = <&gnoc 1 &bimc 5>; + interconnects = <&bimc 1 &bimc 5>; interconnect-names = "gfx-mem"; operating-points-v2 = <&gpu_sdm630_opp_table>; From patchwork Sat May 14 14:10:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 572823 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7BC1CC433EF for ; Sat, 14 May 2022 14:11:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232959AbiENOKw (ORCPT ); Sat, 14 May 2022 10:10:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232957AbiENOKu (ORCPT ); Sat, 14 May 2022 10:10:50 -0400 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F52A14D23 for ; Sat, 14 May 2022 07:10:49 -0700 (PDT) Received: by mail-lf1-x12f.google.com with SMTP id b18so18902326lfv.9 for ; Sat, 14 May 2022 07:10:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vAKzbIo4hRjweGPYwmYctILBgK8ro78wB6S5h8puzVU=; b=sOzCUR6V98rqT7GY+XYtG9PyE3u4k5Hqtjemu8W6GaDAS6jsLgerdUYvJy50sY4JHF aqdZbvLH9DjdHU9Hh6XrczSOz9YGNZ13XstZM8GTbjCNTJs2QlQyCJL95kYPZCOvrqi6 WERJ/1xs6wFz8UKX+CUbN/y63aREU6CoJbYKmR9s/h0oHuWT6bJTcl8Pt7MN6ohaEvjp +ZsprPfgZN6dPEEU9ZPceYEc+GMZ5SKx88iab2EIGiPW8ei+DXz5M7i0a6jdC1EoRLYX z0UqS2qQ6R3pgpk/YC/cAbETyoa/bpGhdkAsnf2tGZnxaSSMzS89PAYnCNn489jtHxs3 20EA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vAKzbIo4hRjweGPYwmYctILBgK8ro78wB6S5h8puzVU=; b=GiVF0Q+CD2SjDOANoBjBjrXxHVEgsmjw6pAjO8qAdJsEWjVUbANA2TqEQhPaEcUfik t0+XTyztGKpmW0ToQkKh8WVwoJcFDJdJc08bmBFydMeYnOy+v3Dqz8i37SfCgxmHopED VPNWHok2+Fy2Hid5NAB+S6pKB2HkO5TrQDtz7n+BHAvFvmXaOjWFZl458eM9PYMkX5A/ X8t8hmH6bsu2WaAYffI1x62I5CFnSTNIG+WiErUp7IG4bzrXXs6N6uly3fHeVKwNIQE1 yOcYyvEUZ9zKW2eGmqH6V14VbTHwv/Cqh1NnefU6bLrrBRGOsjmitUkDSkUtCDbmknUN aZnQ== X-Gm-Message-State: AOAM5335YocoquwDjRtBEOHLvcT1On23WzojuqsUhLDzyiGrZhkOHYVZ Qt4KvXF2W3Uw2zQOeDHT4vzFvA== X-Google-Smtp-Source: ABdhPJzYF4uRWhQ+XRmyrgNwFS5IbmNsiuCp414tMvuttj6/n7nvxSr+SMGtSvNpzelN14umWqxF5g== X-Received: by 2002:a05:6512:3b2b:b0:473:a42b:faa4 with SMTP id f43-20020a0565123b2b00b00473a42bfaa4mr6785574lfv.292.1652537449017; Sat, 14 May 2022 07:10:49 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id x9-20020a05651c104900b0024f3d1daedasm845912ljm.98.2022.05.14.07.10.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 May 2022 07:10:48 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 08/12] arm64: dts: qcom: sdm630: use defined symbols for interconnects Date: Sat, 14 May 2022 17:10:37 +0300 Message-Id: <20220514141041.3158521-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220514141041.3158521-1-dmitry.baryshkov@linaro.org> References: <20220514141041.3158521-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Replace numeric values with the symbolic names defined in the bindings header. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 6d0bc9e8fb5b..44f048934fc6 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -1045,7 +1046,7 @@ adreno_gpu: gpu@5000000 { nvmem-cells = <&gpu_speed_bin>; nvmem-cell-names = "speed_bin"; - interconnects = <&bimc 1 &bimc 5>; + interconnects = <&bimc MASTER_OXILI &bimc SLAVE_EBI>; interconnect-names = "gfx-mem"; operating-points-v2 = <&gpu_sdm630_opp_table>; @@ -1299,8 +1300,8 @@ sdhc_2: sdhci@c084000 { <&xo_board>; clock-names = "core", "iface", "xo"; - interconnects = <&a2noc 3 &a2noc 10>, - <&gnoc 0 &cnoc 28>; + interconnects = <&a2noc MASTER_SDCC_2 &a2noc SLAVE_A2NOC_SNOC>, + <&gnoc MASTER_APSS_PROC &cnoc SLAVE_SDCC_2>; operating-points-v2 = <&sdhc2_opp_table>; pinctrl-names = "default", "sleep"; @@ -1351,8 +1352,8 @@ sdhc_1: sdhci@c0c4000 { <&gcc GCC_SDCC1_ICE_CORE_CLK>; clock-names = "core", "iface", "xo", "ice"; - interconnects = <&a2noc 2 &a2noc 10>, - <&gnoc 0 &cnoc 27>; + interconnects = <&a2noc MASTER_SDCC_1 &a2noc SLAVE_A2NOC_SNOC>, + <&gnoc MASTER_APSS_PROC &cnoc SLAVE_SDCC_1>; interconnect-names = "sdhc1-ddr", "cpu-sdhc1"; operating-points-v2 = <&sdhc1_opp_table>; pinctrl-names = "default", "sleep"; @@ -1525,9 +1526,9 @@ mdp: mdp@c901000 { "core", "vsync"; - interconnects = <&mnoc 2 &bimc 5>, - <&mnoc 3 &bimc 5>, - <&gnoc 0 &mnoc 17>; + interconnects = <&mnoc MASTER_MDP_P0 &bimc SLAVE_EBI>, + <&mnoc MASTER_MDP_P1 &bimc SLAVE_EBI>, + <&gnoc MASTER_APSS_PROC &mnoc SLAVE_DISPLAY_CFG>; interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem"; @@ -2034,7 +2035,7 @@ camss: camss@ca00000 { "cphy_csid1", "cphy_csid2", "cphy_csid3"; - interconnects = <&mnoc 5 &bimc 5>; + interconnects = <&mnoc MASTER_VFE &bimc SLAVE_EBI>; interconnect-names = "vfe-mem"; iommus = <&mmss_smmu 0xc00>, <&mmss_smmu 0xc01>, @@ -2097,8 +2098,8 @@ venus: video-codec@cc00000 { <&mmcc VIDEO_AXI_CLK>, <&mmcc THROTTLE_VIDEO_AXI_CLK>; clock-names = "core", "iface", "bus", "bus_throttle"; - interconnects = <&gnoc 0 &mnoc 13>, - <&mnoc 4 &bimc 5>; + interconnects = <&gnoc MASTER_APSS_PROC &mnoc SLAVE_VENUS_CFG>, + <&mnoc MASTER_VENUS &bimc SLAVE_EBI>; interconnect-names = "cpu-cfg", "video-mem"; interrupts = ; iommus = <&mmss_smmu 0x400>, From patchwork Sat May 14 14:10:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 572821 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B147C433FE for ; Sat, 14 May 2022 14:11:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232970AbiENOLy (ORCPT ); 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Sat, 14 May 2022 07:10:49 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 09/12] arm64: dts: qcom: sdm636-sony-xperia-ganges-mermaid: correct sdc2 pinconf Date: Sat, 14 May 2022 17:10:38 +0300 Message-Id: <20220514141041.3158521-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220514141041.3158521-1-dmitry.baryshkov@linaro.org> References: <20220514141041.3158521-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Fix the device tree node in the &sdc2_state_on override. The sdm630 uses 'clk' rather than 'pinconf-clk'. Fixes: 4c1d849ec047 ("arm64: dts: qcom: sdm630-xperia: Retire sdm630-sony-xperia-ganges.dtsi") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts b/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts index b96da53f2f1e..58f687fc49e0 100644 --- a/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts +++ b/arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dts @@ -19,7 +19,7 @@ / { }; &sdc2_state_on { - pinconf-clk { + clk { drive-strength = <14>; }; }; From patchwork Sat May 14 14:10:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 572824 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C9CFC433EF for ; Sat, 14 May 2022 14:11:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230124AbiENOLW (ORCPT ); Sat, 14 May 2022 10:11:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46122 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232976AbiENOKw (ORCPT ); Sat, 14 May 2022 10:10:52 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09228140DD for ; Sat, 14 May 2022 07:10:50 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id u23so18948972lfc.1 for ; Sat, 14 May 2022 07:10:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PIPhrHSX0vDaE6umAr6Uz83mLWrCmZ9TxDaxz4FKhdY=; b=ljDlVvdD4mMOmXSlRL8FCA6+V2POm2uIk4NElroUmvzAVTsgq3Ndudktq0m2dUE2eD d4nA/ASkSyi0Ad3lFvICu924OEt1n/4X2XVyhDLtAmwpeS0lO7ReNaRo6qX6+gVWTH37 /KaZtjGMLGasRE6AcWD3wvMbRobxyYktW+z3SHftbRXeSAz3VXUsKYBxsAFH2nffpOhU 6cO6XlwQbtRuW0Owr/ard9X3W/5VCZkouOM1s4LKZu6xIU+A3b6OBsu+PrKszSvRoJdW t9/uPXqoiHqKVjvFENzumi33eBYsdqxWHfomKk57KRc5zTlxpp6e32hJgJmMhIibSC0Y zM9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PIPhrHSX0vDaE6umAr6Uz83mLWrCmZ9TxDaxz4FKhdY=; b=S1v3jYht7mbXwEsK4Yx9uqByGrZJc94rryLFCzm+U/pEjb68IjpYGAe26YFoTrB1El mHm9HkdQVR2FOpqEpyhZfd3+JQkvLQ8qdc4HnnSQ37XyQkOVA8hsjiruZ5LPu+oRbqW5 YmA+rBP6QHIimi7OhyKDQ8gY9UIWRANiBtlQhhsR5/adceM56iQCXf2cq76wt5BsycEo sA+YcVPCYYdpFyEe1+DEJajZcLs10w3Gpe+NiDRHROvfP0kq9NnUyEiqOrTmKj+fllPe qNgGqYAIylQk4W0iaAMfl/G+aZvjdK3qEylnbe6P7M0yghocgzGcufAXqYoBTOIjzoij dyFg== X-Gm-Message-State: AOAM5322qISXCuzk/WEpHD1rTP6NeB2PPmq89IMpz8WBiTNZo43X5ngW dU9TgC8H5tlUcRMAIOzYliYjhA== X-Google-Smtp-Source: ABdhPJyRGew1JK1nZsJhMCqES0pLUXwuFX5Usolj6U1v6Ye3QbczlArwNUmZj7OclsTRWV7drc8CCg== X-Received: by 2002:a05:6512:33c9:b0:473:a418:2da7 with SMTP id d9-20020a05651233c900b00473a4182da7mr6766972lfg.356.1652537450511; Sat, 14 May 2022 07:10:50 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id x9-20020a05651c104900b0024f3d1daedasm845912ljm.98.2022.05.14.07.10.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 May 2022 07:10:50 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 10/12] arm64: dts: qcom: sdm660: move SDHC2 card detect pinconf to board files Date: Sat, 14 May 2022 17:10:39 +0300 Message-Id: <20220514141041.3158521-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220514141041.3158521-1-dmitry.baryshkov@linaro.org> References: <20220514141041.3158521-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This results in dts duplication, but per mutual agreement card detect pin configuration belongs to the board files. Move it from the SoC dtsi to the board DT files. Suggested-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov --- .../boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/qcom/sdm630.dtsi | 12 ------------ .../boot/dts/qcom/sdm660-xiaomi-lavender.dts | 16 ++++++++++++++++ 3 files changed, 32 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 00baacf28c63..ccde9951e4fb 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -549,6 +549,22 @@ vreg_l19a_3p3: l19 { }; }; +&sdc2_state_on { + sd-cd { + pins = "gpio54"; + bias-pull-up; + drive-strength = <2>; + }; +}; + +&sdc2_state_off { + sd-cd { + pins = "gpio54"; + bias-disable; + drive-strength = <2>; + }; +}; + &sdhc_1 { status = "okay"; supports-cqe; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 44f048934fc6..e6f06a548011 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -983,12 +983,6 @@ data { bias-pull-up; drive-strength = <10>; }; - - sd-cd { - pins = "gpio54"; - bias-pull-up; - drive-strength = <2>; - }; }; sdc2_state_off: sdc2-off { @@ -1009,12 +1003,6 @@ data { bias-pull-up; drive-strength = <2>; }; - - sd-cd { - pins = "gpio54"; - bias-disable; - drive-strength = <2>; - }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 9280c1f0c334..2b1216502eb0 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -363,6 +363,22 @@ vreg_l19a_3p3: l19 { }; }; +&sdc2_state_on { + sd-cd { + pins = "gpio54"; + bias-pull-up; + drive-strength = <2>; + }; +}; + +&sdc2_state_off { + sd-cd { + pins = "gpio54"; + bias-disable; + drive-strength = <2>; + }; +}; + &sdhc_1 { status = "okay"; supports-cqe; From patchwork Sat May 14 14:10:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 572562 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E875DC4332F for ; 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Sat, 14 May 2022 07:10:50 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 11/12] arm64: dts: qcom: sdm660: Add initial Inforce IFC6560 board support Date: Sat, 14 May 2022 17:10:40 +0300 Message-Id: <20220514141041.3158521-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220514141041.3158521-1-dmitry.baryshkov@linaro.org> References: <20220514141041.3158521-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The IFC6560 is a board from Inforce Computing, built around the SDA660 SoC. This patch describes core clocks, some regulators from the two PMICs, debug uart, storage, bluetooth and audio DSP remoteproc. The regulator settings are inherited from prior work by Konrad Dybcio and AngeloGioacchino Del Regno. Co-developed-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sda660-inforce-ifc6560.dts | 471 ++++++++++++++++++ 2 files changed, 472 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f9e6343acd03..5f717fe0e8d0 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -88,6 +88,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd.dtb +dtb-$(CONFIG_ARCH_QCOM) += sda660-inforce-ifc6560.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts new file mode 100644 index 000000000000..d1923c1310f6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts @@ -0,0 +1,471 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Linaro Ltd. + * Copyright (c) 2020, Konrad Dybcio + * Copyright (c) 2020, AngeloGioacchino Del Regno + * + */ + +/dts-v1/; + +#include "sdm660.dtsi" +#include "pm660.dtsi" +#include "pm660l.dtsi" + +/ { + model = "Inforce 6560 Single Board Computer"; + compatible = "inforce,ifc6560", "qcom,sda660"; + chassis-type = "embedded"; /* SBC */ + + aliases { + serial0 = &blsp1_uart2; + serial1 = &blsp2_uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + volup { + label = "Volume Up"; + gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + }; + + /* + * Until we hook up type-c detection, we + * have to stick with this. But it works. + */ + extcon_usb: extcon-usb { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7533_out>; + }; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + + regulator-always-on; + regulator-boot-on; + }; + + v3p3_bck_bst: v3p3-bck-bst-regulator { + compatible = "regulator-fixed"; + regulator-name = "v3p3_bck_bst"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vph_pwr>; + }; + + v1p2_ldo: v1p2-ldo-regulator { + compatible = "regulator-fixed"; + regulator-name = "v1p2_ldo"; + + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + vin-supply = <&vph_pwr>; + }; + + v5p0_boost: v5p0-boost-regulator { + compatible = "regulator-fixed"; + regulator-name = "v5p0_boost"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + vin-supply = <&vph_pwr>; + }; +}; + +&adsp_pil { + firmware-name = "qcom/ifc6560/adsp.mbn"; +}; + +&blsp1_dma { + /* + * The board will lock up if we toggle the BLSP clock, unless the + * BAM DMA interconnects support is in place. + */ + /delete-property/ clocks; +}; + +&blsp_i2c6 { + status = "okay"; + + adv7533: hdmi@39 { + compatible = "adi,adv7535"; + reg = <0x39>, <0x66>; + reg-names = "main", "edid"; + + interrupt-parent = <&pm660l_gpios>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + + clocks = <&rpmcc RPM_SMD_BB_CLK2>; + clock-names = "cec"; + /* + * Limit to 3 lanes to prevent the bridge from changing amount + * of lanes in the fly. MSM DSI host doesn't like that. + */ + adi,dsi-lanes = <3>; + avdd-supply = <&vreg_l13a_1p8>; + dvdd-supply = <&vreg_l13a_1p8>; + pvdd-supply = <&vreg_l13a_1p8>; + a2vdd-supply = <&vreg_l13a_1p8>; + v3p3-supply = <&v3p3_bck_bst>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7533_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + adv7533_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&blsp2_dma { + /* + * The board will lock up if we toggle the BLSP clock, unless the + * BAM DMA interconnects support is in place. + */ + /delete-property/ clocks; +}; + +&blsp2_uart1 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_l13a_1p8>; + vddxo-supply = <&vreg_l9a_1p8>; + vddrf-supply = <&vreg_l6a_1p3>; + vddch0-supply = <&vreg_l19a_3p3>; + max-speed = <3200000>; + }; +}; + +&dsi0 { + status = "okay"; + vdda-supply = <&vreg_l1a_1p225>; +}; + +&dsi0_out { + remote-endpoint = <&adv7533_in>; + data-lanes = <0 1 2 3>; +}; + +&dsi0_phy { + status = "okay"; + vcca-supply = <&vreg_l1b_0p925>; +}; + +&mdp { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mmss_smmu { + status = "okay"; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + + linux,code = ; +}; + +&qusb2phy0 { + status = "okay"; + + vdd-supply = <&vreg_l1b_0p925>; + vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; +}; + +&qusb2phy1 { + status = "okay"; + + vdd-supply = <&vreg_l1b_0p925>; + vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; +}; + +&rpm_requests { + pm660-regulators { + compatible = "qcom,rpm-pm660-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l6_l7-supply = <&vreg_s5a_1p35>; + vdd_l2_l3-supply = <&vreg_s2b_1p05>; + vdd_l5-supply = <&vreg_s2b_1p05>; + vdd_l8_l9_l10_l11_l12_l13_l14-supply = <&vreg_s4a_2p04>; + vdd_l15_l16_l17_l18_l19-supply = <&vreg_bob>; + + vreg_s4a_2p04: s4 { + regulator-min-microvolt = <1805000>; + regulator-max-microvolt = <2040000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + vreg_s5a_1p35: s5 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1350000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + vreg_l1a_1p225: l1 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l6a_1p3: l6 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1368000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l8a_1p8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-system-load = <325000>; + regulator-allow-set-load; + }; + + vreg_l9a_1p8: l9 { + regulator-min-microvolt = <1804000>; + regulator-max-microvolt = <1896000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l13a_1p8: l13 { + /* This gives power to the LPDDR4: never turn it off! */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1944000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-always-on; + regulator-boot-on; + }; + + vreg_l19a_3p3: l19 { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + }; + + pm660l-regulators { + compatible = "qcom,rpm-pm660l-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l9_l10-supply = <&vreg_s2b_1p05>; + vdd_l2-supply = <&vreg_bob>; + vdd_l3_l5_l7_l8-supply = <&vreg_bob>; + vdd_l4_l6-supply = <&vreg_bob>; + vdd_bob-supply = <&vph_pwr>; + + vreg_s2b_1p05: s2 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + vreg_l1b_0p925: l1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <925000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l2b_2p95: l2 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l4b_2p95: l4 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <2952000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + + regulator-min-microamp = <200>; + regulator-max-microamp = <600000>; + regulator-system-load = <570000>; + regulator-allow-set-load; + }; + + /* + * Downstream specifies a range of 1721-3600mV, + * but the only assigned consumers are SDHCI2 VMMC + * and Coresight QPDI that both request pinned 2.95V. + * Tighten the range to 1.8-3.328 (closest to 3.3) to + * make the mmc driver happy. + */ + vreg_l5b_2p95: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3328000>; + regulator-enable-ramp-delay = <250>; + regulator-system-load = <800000>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l7b_3p125: l7 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3125000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l8b_3p3: l8 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3624000>; + regulator-enable-ramp-delay = <500>; + regulator-ramp-delay = <0>; + }; + }; +}; + +&sdc2_state_on { + sd-cd { + pins = "gpio54"; + bias-pull-up; + drive-strength = <2>; + }; +}; + +&sdc2_state_off { + sd-cd { + pins = "gpio54"; + bias-disable; + drive-strength = <2>; + }; +}; + +&sdhc_1 { + status = "okay"; + supports-cqe; + + vmmc-supply = <&vreg_l4b_2p95>; + vqmmc-supply = <&vreg_l8a_1p8>; + + mmc-ddr-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&vreg_l5b_2p95>; + vqmmc-supply = <&vreg_l2b_2p95>; + + cd-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>; + no-sdio; + no-emmc; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <8 4>; + + sdc2_card_det_n: sd-card-det-n { + pins = "gpio54"; + function = "gpio"; + bias-pull-up; + }; +}; + +&usb2 { + status = "okay"; +}; + +&usb2_dwc3 { + dr_mode = "host"; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; + extcon = <&extcon_usb>; +}; From patchwork Sat May 14 14:10:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 572822 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 964B5C43217 for ; Sat, 14 May 2022 14:11:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232957AbiENOLx (ORCPT ); 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Sat, 14 May 2022 07:10:51 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio , Marijn Suijten Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 12/12] dt-bindings: arm: qcom: document sda660 SoC and ifc6560 board Date: Sat, 14 May 2022 17:10:41 +0300 Message-Id: <20220514141041.3158521-13-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220514141041.3158521-1-dmitry.baryshkov@linaro.org> References: <20220514141041.3158521-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add binding documentation for the Inforce IFC6560 board which uses Snapdragon SDA660. Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 129cdd246223..ac4ee0f874ea 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -41,6 +41,7 @@ description: | sa8155p sc7180 sc7280 + sda660 sdm630 sdm632 sdm660 @@ -225,6 +226,11 @@ properties: - google,senor - const: qcom,sc7280 + - items: + - enum: + - inforce,ifc6560 + - const: qcom,sda660 + - items: - enum: - fairphone,fp3