From patchwork Fri May 13 23:45:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 572244 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A5EDC433F5 for ; Fri, 13 May 2022 23:55:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229484AbiEMXzZ (ORCPT ); Fri, 13 May 2022 19:55:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51400 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229441AbiEMXzY (ORCPT ); Fri, 13 May 2022 19:55:24 -0400 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF7033A8AF1 for ; Fri, 13 May 2022 16:45:39 -0700 (PDT) Received: by mail-lj1-x22c.google.com with SMTP id s27so11999667ljd.2 for ; Fri, 13 May 2022 16:45:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ypxafSXytWa1pPBeHJ41K2y3Cfr7QvnghKr6SvtMtAA=; b=KDfN369II16+5p2gc4GulHkeIqPe81bmC5OQuViwrZQXhW28iWwmNhjJ2aApZx23Wg ptYdBumtf1L/x6MxSBZ9zw8PWk2U+Qpnuk7WAYuZa4birs3qunMMdD8ui7gSuZzVul64 jx2qZ2PZ91+Z9BWtj+iBSMeut2szue6Ja9UsO5Te2XnwLkVOfqDzSQfrTuWzJxL3oRD6 DEjfXFCxcIpicZE9ihUMHEnzWW5AKpewz4ZJMKUbYxsz/p42n3x3Fh751Jc9rwVzp9Vm sejgaIlXjFAQRrQ3yFMfjstylW9IJBz5FVRLcuPN+K9SfD4MLk6vkRcvOThhT+m6WQ8X JhEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ypxafSXytWa1pPBeHJ41K2y3Cfr7QvnghKr6SvtMtAA=; b=JMYh5eqbWs9JVAWrmr5xT4vuZwIP9efKmKX/s5bqx3d4kqAc7bRBN2tHr0qB46M5Qj RPWCN9InX+I2zO4s48AaivlA+brZMUsjyrHw10u+zfTASqvRtoA4+piQWkJiEuhlBljd T5qN4+yo2LCAh8tBLlfOC8mAfZIe9c1qPd2W8mBr3ZD07z9vCKnc2L+Yirj/T2/YitU1 0x89CNc0SOR585q0NY/PSk1pZoTrH4BuGlxpOUbankQvoEKx7WTtlE78r+k0Ot6SCb/F H7RfPnJsn2V86lbHpGwlJQ1rgrBonL7DIMIzQ0Z5uAjg6N0oFALWxLnwZDjwx7/OZ9uN OR5A== X-Gm-Message-State: AOAM530ZESY4loV8A4Vv30MCaENYf332MyafN/9MR5I2D6yXfi2uviQi dQ0JjeNrEDIHOEyZO3pj9mAfCA== X-Google-Smtp-Source: ABdhPJxkC9UkmXQIquUS/nbTM5as+JgDGHLhvAoXwMioa7NQELEnTg6u2yL54nFsduJhWTQ7+oKXqQ== X-Received: by 2002:a05:651c:89:b0:250:87c9:d4e6 with SMTP id 9-20020a05651c008900b0025087c9d4e6mr4480668ljq.315.1652485520441; Fri, 13 May 2022 16:45:20 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id o8-20020a05651205c800b0047255d2118csm527342lfo.187.2022.05.13.16.45.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 May 2022 16:45:20 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Marijn Suijten Subject: [PATCH v3 1/8] arm64: dts: qcom: sdm660: disable dsi1/dsi1_phy by default Date: Sat, 14 May 2022 02:45:11 +0300 Message-Id: <20220513234518.3068480-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220513234518.3068480-1-dmitry.baryshkov@linaro.org> References: <20220513234518.3068480-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Follow the typical practice and keep DSI1/DSI1 PHY disabled by default. They should be enabled in the board DT files. No existing boards use them at this moment. Reviewed-by: Marijn Suijten Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm660.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi index eccf6fde16b4..023b0ac4118c 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -192,6 +192,8 @@ dsi1: dsi@c996000 { phys = <&dsi1_phy>; phy-names = "dsi"; + status = "disabled"; + ports { #address-cells = <1>; #size-cells = <0>; @@ -225,6 +227,7 @@ dsi1_phy: dsi-phy@c996400 { clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "ref"; + status = "disabled"; }; }; From patchwork Fri May 13 23:45:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 572883 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E037C433EF for ; Sat, 14 May 2022 01:41:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229616AbiENBlX (ORCPT ); Fri, 13 May 2022 21:41:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57570 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229702AbiENBlQ (ORCPT ); Fri, 13 May 2022 21:41:16 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7D6473A9CB6 for ; Fri, 13 May 2022 16:45:48 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id bu29so17058850lfb.0 for ; Fri, 13 May 2022 16:45:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=azPGR+vZJiRZ8wrc365ZR8Nim5+sjCT0QCeZdqg0Fso=; b=tLX7iIWQN0MaA9bCcqHBAJailxCpxzFiocc1kjv911EMS9wlACNcgn7mcOi9N7pP6y 3RgSJdKa1a+UNfTvso3bzum4wKkU7KKqWzigv3PETuL68i3jPb0jJA5Whtyt/vK/F3qY X0toXYeODLdUZ8PEQRO50Wr009pjokkOW9qpMrcyozqEAimLIgfuqF7jN4gpAmM0zEUW pMS2KdlnL72f2w3+lDPfJCQb1LKlUr/6XKfGFzyHK0xpez2RseaZQ70XB08riyQ2yrvB IbBeRiXsLGmNmTBe3mYX4xEsCwusYzsdFx2K2nheoS6TGoVK1l2+ymDjWPyQKa6EGygU AtTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=azPGR+vZJiRZ8wrc365ZR8Nim5+sjCT0QCeZdqg0Fso=; b=tqLqvU4u/Q0LeF+Nwu4tEC+849r6iT+JMvcwGs/vE8vcZWu3somw0VbzehSf7fBJut eCh5Q5CvbXfbisd+MvbuPBqa9LI5P9jYh8VK2PKrGuS8tqYcGvy0mNeZm6/u1MriCmbk h2/47WHVv0ZkdugECttz3ijhX/YcE37auqkQHvsqgShpiROhZ/O+VDSvm9A0V31iMqIH mVmAA8KOtu3Y6eSm+6/4TZGPnv0S61GwOVMxmaRBMiVJNbbkGyFEzq4CWNbRBwa+Q1Zw gP5WVP0mpyTvI8R22GyaghDnJPJh39vKTq59Cvd4kXBOkbo83idHDA15l6+P4Up/6Pas KJqQ== X-Gm-Message-State: AOAM531YRfvMs1xgbw+krIjWNR1HyE2mOnwQiIyKIvtxU/DsYArs9r4w vwd/1WMvuuD776CGyNfCcJeQjw== X-Google-Smtp-Source: ABdhPJwbf1YnNnKsUh7jswHCcTiVi6hxvSITTeIKu1qKT+R8IDeznnXIe3k4oWr7S149yb6OwIRgWg== X-Received: by 2002:a05:6512:401d:b0:473:c7e2:f3ca with SMTP id br29-20020a056512401d00b00473c7e2f3camr5212065lfb.153.1652485521236; Fri, 13 May 2022 16:45:21 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id o8-20020a05651205c800b0047255d2118csm527342lfo.187.2022.05.13.16.45.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 May 2022 16:45:20 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 2/8] arm64: dts: qcom: sdm630: disable dsi1/dsi1_phy by default Date: Sat, 14 May 2022 02:45:12 +0300 Message-Id: <20220513234518.3068480-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220513234518.3068480-1-dmitry.baryshkov@linaro.org> References: <20220513234518.3068480-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Follow the typical practice and keep DSI0/DSI0 PHY disabled by default. They should be enabled in the board DT files. No existing boards use them at this moment. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 240293592ef9..8697d40e9b74 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1559,6 +1559,8 @@ dsi0: dsi@c994000 { phys = <&dsi0_phy>; phy-names = "dsi"; + status = "disabled"; + ports { #address-cells = <1>; #size-cells = <0>; @@ -1592,6 +1594,7 @@ dsi0_phy: dsi-phy@c994400 { clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; clock-names = "iface", "ref"; + status = "disabled"; }; }; From patchwork Fri May 13 23:45:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 572882 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52678C433F5 for ; Sat, 14 May 2022 01:41:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229543AbiENBlb (ORCPT ); Fri, 13 May 2022 21:41:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229610AbiENBlb (ORCPT ); Fri, 13 May 2022 21:41:31 -0400 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 909B13AAB03 for ; Fri, 13 May 2022 16:45:55 -0700 (PDT) Received: by mail-lf1-x129.google.com with SMTP id bq30so16991851lfb.3 for ; Fri, 13 May 2022 16:45:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=i1goeg2wYzcHMfXO9CDFGJF9XLqANUBaSoksUz5XNRc=; b=DOh4ydj8Vt+P+KC3rNmfFvdd0RxSWIf5d7MsrKn4wDhhzx3X5T4v0Z5B+/KH6TQyOC bGYJ/c6Lqw9kO2xadkgrLqAkhe6CJ+68tMTQRRAIFiEWzrUuWlatl/Iw2NL0p5nDCQF+ /bqJrNpu4ZsNn1NtGnNo2osR7rrqQZZFEz29Odxr0g+uI1SxDqN/DoVvSkgHEIfvrT/i Jz3WxFaCB6VpSDlx1dvE0sc4j3yXm3XbFY5XUPcWEkO2XVgTJgjNCNaejgD5ztMbIYVn 21ejXb74zhGuJ+0JTGTo/nxdKWC3aMrHXAdTj95+aOuGrAcLEepLD7zoAXBLJYqtBex7 caJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=i1goeg2wYzcHMfXO9CDFGJF9XLqANUBaSoksUz5XNRc=; b=QCv90DEttBPcx7wrFyR7TMP9Kxf4qGB+oSiRCBfVPaIKPdjyZ06ikHBNb0zFrBy8ea jKBFyu8BKBOXAPS53wQgKM68vs0hdCFLGHK+zzOGvvEd3BWoMP7D/n/q7JKWehL3EnHu 31RCF5XVhgSzl5lNNhQDzxSyTdYUWogf3QAgXplloLadS26jlJ9jRzYbSSivkWpotBhK vf0xnc+u8MPghK+QtA1NhBlDXa3Z8qiXZQrl6K0YTQtudD1779mbByD6BqEiAOat86R/ rDWGUjkG51xtDUW6rYaleA32C/eeN23rCj3ftnwaSvvwKMwv0ylZfCRZrNnJS2MOjTxg t85Q== X-Gm-Message-State: AOAM533njaVbU6ECGTyvaDvwYo5pa8Wtg1J69v/ng+nWrL1nyGLTPeWS 0Z57afRhpaHTWBrAFbcl+oqjaQ== X-Google-Smtp-Source: ABdhPJzuGCarikvO5ii1GxPSc5tz+D29jM0wDdsYs0FLCL+VY4bt1vgxhr6toc81lM9HG2h9qHZVDQ== X-Received: by 2002:a05:6512:33c5:b0:473:d0c5:dd03 with SMTP id d5-20020a05651233c500b00473d0c5dd03mr5014216lfg.605.1652485522004; Fri, 13 May 2022 16:45:22 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id o8-20020a05651205c800b0047255d2118csm527342lfo.187.2022.05.13.16.45.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 May 2022 16:45:21 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 3/8] arm64: dts: qcom: sdm630: disable GPU by default Date: Sat, 14 May 2022 02:45:13 +0300 Message-Id: <20220513234518.3068480-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220513234518.3068480-1-dmitry.baryshkov@linaro.org> References: <20220513234518.3068480-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SoC's device tree file disables gpucc and adreno's SMMU by default. So let's disable the GPU too. Moreover it looks like SMMU might be not usable without additional patches (which means that GPU is unusable too). No board uses GPU at this moment. Fixes: 5cf69dcbec8b ("arm64: dts: qcom: sdm630: Add Adreno 508 GPU configuration") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 8697d40e9b74..e8bb170e8b2f 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1050,6 +1050,8 @@ adreno_gpu: gpu@5000000 { operating-points-v2 = <&gpu_sdm630_opp_table>; + status = "disabled"; + gpu_sdm630_opp_table: opp-table { compatible = "operating-points-v2"; opp-775000000 { From patchwork Fri May 13 23:45:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 572639 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DD1EC43217 for ; Sat, 14 May 2022 01:41:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229604AbiENBlY (ORCPT ); Fri, 13 May 2022 21:41:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229707AbiENBlR (ORCPT ); Fri, 13 May 2022 21:41:17 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2BAE53AAB27 for ; Fri, 13 May 2022 16:45:59 -0700 (PDT) Received: by mail-lj1-x233.google.com with SMTP id y19so11977922ljd.4 for ; Fri, 13 May 2022 16:45:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=x2qQH918JYdrczWJIIm8XRXT3abBOAyM4GeAzsiuGrc=; b=SeoS+Ay7JrwJplYt71eGo1y7KdWEdpebHQHUFH7uc44/Oiokf9Xuhq5HUcR0IlcZQB 5nSeDFF8qJmowEkvBKERSetRLJp5V21ZNpTUzooXmuCVqrM3DOTUL8FpzV94OLKU0ZK+ ngeqho+zdHKi7nMqCcM2zSe5j9eL0SWtpsUzjP84bLAxdPilwcVvPfBUg0kc8wlfJymz g7RPXVhTwmTeMterfjNpJpLqf7Ab/HOGHRXJnbW8sHyZqlcmR74Rdb1Mtcnq8akIK88f s6wshgspnpJodCwqLEhdIuo9M5z/hT4hRtJArcVcU3d+h9tQgCek9HWnu65t6yJ+ejdP DsVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=x2qQH918JYdrczWJIIm8XRXT3abBOAyM4GeAzsiuGrc=; b=etffDFJ9wfxiNhTSNpzvQlP7JDSz1tBbvF6jW8y1IAZuDg3extVu+WMq4eTOCnzxL1 e6Hy7ZNx/2nKuAj4ft6DGTZpO3RCaq9SIqlbev1J5Bz3IJDGia8OF1l+SorPdJYwMHin HoHNFCbr0o68+NIp376XEg2luTIUWwODTiVBtSysfTttpxAlnUofxg5QZTIJ0WQSIA7e BRO3RVaLWLfGRgp4AxvR3a7xUuVOUnVosRdEOgF3yx408Sya058i7uJvykk8u30G9aWU Yap0mtgDfO5tQUnvKh+00cU+iItpb5yRSTWz400V1h1WSchC2QeECx4YvdiPWY/UHjHl Tstw== X-Gm-Message-State: AOAM531sKe5yxxmuJRtfK/F5ecj5BqF/xE0KrSYddiBFVMS5Og6yAx3p 7gUfzCbXs6CwBigmwdQgCOHoVQ== X-Google-Smtp-Source: ABdhPJxXCLHqAqEgg5HzVVhdNjvALIvlwrJyELVKyeOj4unPswlBVhSCXGXRpYs8nUuM3N/R2b3udA== X-Received: by 2002:a2e:a552:0:b0:250:6297:8109 with SMTP id e18-20020a2ea552000000b0025062978109mr4420350ljn.504.1652485522710; Fri, 13 May 2022 16:45:22 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id o8-20020a05651205c800b0047255d2118csm527342lfo.187.2022.05.13.16.45.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 May 2022 16:45:22 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 4/8] arm64: dts: qcom: sdm630: fix the qusb2phy ref clock Date: Sat, 14 May 2022 02:45:14 +0300 Message-Id: <20220513234518.3068480-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220513234518.3068480-1-dmitry.baryshkov@linaro.org> References: <20220513234518.3068480-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org According to the downstram DT file, the qusb2phy ref clock should be GCC_RX0_USB2_CLKREF_CLK, not GCC_RX1_USB2_CLKREF_CLK. Fixes: c65a4ed2ea8b ("arm64: dts: qcom: sdm630: Add USB configuration") Cc: Konrad Dybcio Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index e8bb170e8b2f..cca56f2fad96 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1262,7 +1262,7 @@ qusb2phy: phy@c012000 { #phy-cells = <0>; clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, - <&gcc GCC_RX1_USB2_CLKREF_CLK>; + <&gcc GCC_RX0_USB2_CLKREF_CLK>; clock-names = "cfg_ahb", "ref"; resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; From patchwork Fri May 13 23:45:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 572644 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03C58C433F5 for ; Fri, 13 May 2022 23:56:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230108AbiEMX4Q (ORCPT ); Fri, 13 May 2022 19:56:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229534AbiEMXzx (ORCPT ); Fri, 13 May 2022 19:55:53 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D098D3AB9AC for ; Fri, 13 May 2022 16:46:05 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id b18so16937713lfv.9 for ; Fri, 13 May 2022 16:46:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=u1F2z8vf2EByZAfH4u3WGQEipah84mZvdDX5pars+Lg=; b=JFwzclKOM1V3qtLae9wxI2GoDoyADdTNMhn7fkIPqqcvFLJWhPXd8v0Qz1kG8cuP5r nyDh+Org9X6jMa/FM+odgGTVcq2t8p2Nv44KkXAIreNjlHH9gzLov8iIXjKRKepPp2dr 8f9E5OiIuMjtOh9nRdyqhVAEfCIi0FTZVpvmySFd9q0gohwSnZY7TfNqMtVUt2gFnhT+ jlQ1s1XKEXiZGRjyZmS7QTAK7dYU4TSTbmi41wa0AQkWdm8Aral3Ijqa/ekWv7wPcoJH RQr/6ubahaBICkmucQK2YU4xsBx0Sj7v6KgkCnWU8NjIgBx0rB8GGcrM160I6C2FIwD/ 0eIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u1F2z8vf2EByZAfH4u3WGQEipah84mZvdDX5pars+Lg=; b=w+N6OfO+ZJtemXRtcNdS8UWStHCtVMF+Qpg2i3wURr6flAKAGNnSkz09DnmnuCRlUb 0NeQi+TzkBi/udHKYVncG4OsoberRyD4glaKncuS/Znjmtwc06JMNE3Ph1P2KdcO1Ym8 ezENHeBRPUJrUhUg90pN8sN5d76wvsDyn6c0BY0+YArvbM/T+RpD/PyYXW95diVKmHto xnzgCIZ2bfLFJwA7bhw9OhhadnHpl7RP3Lra+8OquTpep02Ja9pfLNHYTOpj36yz2AUB RHZeCEShPcW3U8FwVZAPuPjgcap5V5eYmoTrBTVYIC0V9nukLcAl86/lwFrDleopnsUi IsLA== X-Gm-Message-State: AOAM533AaLxuufq9vR4UAObB0SSogbB406RpTp3SCIu1JksaqwIgbcTf o8gGE/My9nQw91E8H538BHijrw== X-Google-Smtp-Source: ABdhPJzub7V1/LiwJ38+Za7EX4T2nNS1CQ1XsrjiZdVIRQXPObo17tKPB0Dact7BLCGaBSNZUvjQTw== X-Received: by 2002:a05:6512:2311:b0:473:a659:878b with SMTP id o17-20020a056512231100b00473a659878bmr5123218lfu.352.1652485523426; Fri, 13 May 2022 16:45:23 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id o8-20020a05651205c800b0047255d2118csm527342lfo.187.2022.05.13.16.45.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 May 2022 16:45:23 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 5/8] arm64: dts: qcom: sdm630: add second (HS) USB host support Date: Sat, 14 May 2022 02:45:15 +0300 Message-Id: <20220513234518.3068480-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220513234518.3068480-1-dmitry.baryshkov@linaro.org> References: <20220513234518.3068480-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT entries for the second DWC3 USB host, which is limited to the USB2.0 (HighSpeed), and the corresponding QUSB PHY. Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 55 ++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index cca56f2fad96..17a1877587cf 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1270,6 +1270,20 @@ qusb2phy: phy@c012000 { status = "disabled"; }; + qusb2phy1: phy@c014000 { + compatible = "qcom,sdm660-qusb2-phy"; + reg = <0x0c014000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_RX1_USB2_CLKREF_CLK>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + nvmem-cells = <&qusb2_hstx_trim>; + status = "disabled"; + }; + sdhc_2: sdhci@c084000 { compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; reg = <0x0c084000 0x1000>; @@ -1375,6 +1389,47 @@ opp-384000000 { }; }; + usb2: usb@c2f8800 { + compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; + reg = <0x0c2f8800 0x400>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>; + clock-names = "cfg_noc", "core", + "mock_utmi", "sleep"; + + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>; + assigned-clock-rates = <19200000>, <60000000>; + + interrupts = ; + interrupt-names = "hs_phy_irq"; + + qcom,select-utmi-as-pipe-clk; + + resets = <&gcc GCC_USB_20_BCR>; + + usb2_dwc3: usb@c200000 { + compatible = "snps,dwc3"; + reg = <0x0c200000 0xc8d0>; + interrupts = ; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + /* This is the HS-only host */ + maximum-speed = "high-speed"; + phys = <&qusb2phy1>; + phy-names = "usb2-phy"; + snps,hird-threshold = /bits/ 8 <0>; + }; + }; + mmcc: clock-controller@c8c0000 { compatible = "qcom,mmcc-sdm630"; reg = <0x0c8c0000 0x40000>; From patchwork Fri May 13 23:45:16 2022 Content-Type: text/plain; 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Fri, 13 May 2022 16:45:27 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id o8-20020a05651205c800b0047255d2118csm527342lfo.187.2022.05.13.16.45.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 May 2022 16:45:27 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 6/8] arm64: dts: qcom: sdm630: use defined symbols for interconnects Date: Sat, 14 May 2022 02:45:16 +0300 Message-Id: <20220513234518.3068480-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220513234518.3068480-1-dmitry.baryshkov@linaro.org> References: <20220513234518.3068480-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Replace numeric values with the symbolic names defined in the bindings header. Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 17a1877587cf..01a1a1703568 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -1045,7 +1046,7 @@ adreno_gpu: gpu@5000000 { nvmem-cells = <&gpu_speed_bin>; nvmem-cell-names = "speed_bin"; - interconnects = <&gnoc 1 &bimc 5>; + interconnects = <&gnoc MASTER_APSS_PROC &bimc SLAVE_EBI>; interconnect-names = "gfx-mem"; operating-points-v2 = <&gpu_sdm630_opp_table>; @@ -1299,8 +1300,8 @@ sdhc_2: sdhci@c084000 { <&xo_board>; clock-names = "core", "iface", "xo"; - interconnects = <&a2noc 3 &a2noc 10>, - <&gnoc 0 &cnoc 28>; + interconnects = <&a2noc MASTER_SDCC_2 &a2noc SLAVE_A2NOC_SNOC>, + <&gnoc MASTER_APSS_PROC &cnoc SLAVE_SDCC_2>; operating-points-v2 = <&sdhc2_opp_table>; pinctrl-names = "default", "sleep"; @@ -1351,8 +1352,8 @@ sdhc_1: sdhci@c0c4000 { <&gcc GCC_SDCC1_ICE_CORE_CLK>; clock-names = "core", "iface", "xo", "ice"; - interconnects = <&a2noc 2 &a2noc 10>, - <&gnoc 0 &cnoc 27>; + interconnects = <&a2noc MASTER_SDCC_1 &a2noc SLAVE_A2NOC_SNOC>, + <&gnoc MASTER_APSS_PROC &cnoc SLAVE_SDCC_1>; interconnect-names = "sdhc1-ddr", "cpu-sdhc1"; operating-points-v2 = <&sdhc1_opp_table>; pinctrl-names = "default", "sleep"; @@ -1525,9 +1526,9 @@ mdp: mdp@c901000 { "core", "vsync"; - interconnects = <&mnoc 2 &bimc 5>, - <&mnoc 3 &bimc 5>, - <&gnoc 0 &mnoc 17>; + interconnects = <&mnoc MASTER_MDP_P0 &bimc SLAVE_EBI>, + <&mnoc MASTER_MDP_P1 &bimc SLAVE_EBI>, + <&gnoc MASTER_APSS_PROC &mnoc SLAVE_DISPLAY_CFG>; interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem"; @@ -2034,7 +2035,7 @@ camss: camss@ca00000 { "cphy_csid1", "cphy_csid2", "cphy_csid3"; - interconnects = <&mnoc 5 &bimc 5>; + interconnects = <&mnoc MASTER_VFE &bimc SLAVE_EBI>; interconnect-names = "vfe-mem"; iommus = <&mmss_smmu 0xc00>, <&mmss_smmu 0xc01>, @@ -2097,8 +2098,8 @@ venus: video-codec@cc00000 { <&mmcc VIDEO_AXI_CLK>, <&mmcc THROTTLE_VIDEO_AXI_CLK>; clock-names = "core", "iface", "bus", "bus_throttle"; - interconnects = <&gnoc 0 &mnoc 13>, - <&mnoc 4 &bimc 5>; + interconnects = <&gnoc MASTER_APSS_PROC &mnoc SLAVE_VENUS_CFG>, + <&mnoc MASTER_VENUS &bimc SLAVE_EBI>; interconnect-names = "cpu-cfg", "video-mem"; interrupts = ; iommus = <&mmss_smmu 0x400>, From patchwork Fri May 13 23:45:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 572242 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D08CC433EF for ; Fri, 13 May 2022 23:56:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229608AbiEMX4R (ORCPT ); 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Fri, 13 May 2022 16:45:28 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 7/8] arm64: dts: qcom: sdm660: Add initial Inforce IFC6560 board support Date: Sat, 14 May 2022 02:45:17 +0300 Message-Id: <20220513234518.3068480-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220513234518.3068480-1-dmitry.baryshkov@linaro.org> References: <20220513234518.3068480-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The IFC6560 is a board from Inforce Computing, built around the SDA660 SoC. This patch describes core clocks, some regulators from the two PMICs, debug uart, storage, bluetooth and audio DSP remoteproc. The regulator settings are inherited from prior work by Konrad Dybcio and AngeloGioacchino Del Regno. Co-developed-by: Bjorn Andersson Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sda660-inforce-ifc6560.dts | 455 ++++++++++++++++++ 2 files changed, 456 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f9e6343acd03..5f717fe0e8d0 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -88,6 +88,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd.dtb +dtb-$(CONFIG_ARCH_QCOM) += sda660-inforce-ifc6560.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts new file mode 100644 index 000000000000..ade5c27dafcf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts @@ -0,0 +1,455 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Linaro Ltd. + * Copyright (c) 2020, Konrad Dybcio + * Copyright (c) 2020, AngeloGioacchino Del Regno + * + */ + +/dts-v1/; + +#include "sdm660.dtsi" +#include "pm660.dtsi" +#include "pm660l.dtsi" + +/ { + model = "Inforce 6560 Single Board Computer"; + compatible = "inforce,ifc6560", "qcom,sda660"; + chassis-type = "embedded"; /* SBC */ + + aliases { + serial0 = &blsp1_uart2; + serial1 = &blsp2_uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + volup { + label = "Volume Up"; + gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + }; + }; + + /* + * Until we hook up type-c detection, we + * have to stick with this. But it works. + */ + extcon_usb: extcon-usb { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7533_out>; + }; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + + regulator-always-on; + regulator-boot-on; + }; + + v3p3_bck_bst: v3p3-bck-bst-regulator { + compatible = "regulator-fixed"; + regulator-name = "v3p3_bck_bst"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vph_pwr>; + }; + + v1p2_ldo: v1p2-ldo-regulator { + compatible = "regulator-fixed"; + regulator-name = "v1p2_ldo"; + + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + vin-supply = <&vph_pwr>; + }; + + v5p0_boost: v5p0-boost-regulator { + compatible = "regulator-fixed"; + regulator-name = "v5p0_boost"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + vin-supply = <&vph_pwr>; + }; +}; + +&adsp_pil { + firmware-name = "qcom/ifc6560/adsp.mbn"; +}; + +&blsp1_dma { + /* + * The board will lock up if we toggle the BLSP clock, unless the + * BAM DMA interconnects support is in place. + */ + /delete-property/ clocks; +}; + +&blsp_i2c6 { + status = "okay"; + + adv7533: hdmi@39 { + compatible = "adi,adv7535"; + reg = <0x39>, <0x66>; + reg-names = "main", "edid"; + + interrupt-parent = <&pm660l_gpios>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + + clocks = <&rpmcc RPM_SMD_BB_CLK2>; + clock-names = "cec"; + /* + * Limit to 3 lanes to prevent the bridge from changing amount + * of lanes in the fly. MSM DSI host doesn't like that. + */ + adi,dsi-lanes = <3>; + avdd-supply = <&vreg_l13a_1p8>; + dvdd-supply = <&vreg_l13a_1p8>; + pvdd-supply = <&vreg_l13a_1p8>; + a2vdd-supply = <&vreg_l13a_1p8>; + v3p3-supply = <&v3p3_bck_bst>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7533_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + adv7533_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&blsp2_dma { + /* + * The board will lock up if we toggle the BLSP clock, unless the + * BAM DMA interconnects support is in place. + */ + /delete-property/ clocks; +}; + +&blsp2_uart1 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_l13a_1p8>; + vddxo-supply = <&vreg_l9a_1p8>; + vddrf-supply = <&vreg_l6a_1p3>; + vddch0-supply = <&vreg_l19a_3p3>; + max-speed = <3200000>; + }; +}; + +&dsi0 { + status = "okay"; + vdda-supply = <&vreg_l1a_1p225>; +}; + +&dsi0_out { + remote-endpoint = <&adv7533_in>; + data-lanes = <0 1 2 3>; +}; + +&dsi0_phy { + status = "okay"; + vcca-supply = <&vreg_l1b_0p925>; +}; + +&mdss { + status = "okay"; +}; + +&mmss_smmu { + status = "okay"; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + + linux,code = ; +}; + +&qusb2phy { + status = "okay"; + + vdd-supply = <&vreg_l1b_0p925>; + vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; +}; + +&qusb2phy1 { + status = "okay"; + + vdd-supply = <&vreg_l1b_0p925>; + vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; +}; + +&rpm_requests { + pm660-regulators { + compatible = "qcom,rpm-pm660-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l6_l7-supply = <&vreg_s5a_1p35>; + vdd_l2_l3-supply = <&vreg_s2b_1p05>; + vdd_l5-supply = <&vreg_s2b_1p05>; + vdd_l8_l9_l10_l11_l12_l13_l14-supply = <&vreg_s4a_2p04>; + vdd_l15_l16_l17_l18_l19-supply = <&vreg_bob>; + + vreg_s4a_2p04: s4 { + regulator-min-microvolt = <1805000>; + regulator-max-microvolt = <2040000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + vreg_s5a_1p35: s5 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1350000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + vreg_l1a_1p225: l1 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l6a_1p3: l6 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1368000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l8a_1p8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-system-load = <325000>; + regulator-allow-set-load; + }; + + vreg_l9a_1p8: l9 { + regulator-min-microvolt = <1804000>; + regulator-max-microvolt = <1896000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l13a_1p8: l13 { + /* This gives power to the LPDDR4: never turn it off! */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1944000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-always-on; + regulator-boot-on; + }; + + vreg_l19a_3p3: l19 { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + }; + + pm660l-regulators { + compatible = "qcom,rpm-pm660l-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l9_l10-supply = <&vreg_s2b_1p05>; + vdd_l2-supply = <&vreg_bob>; + vdd_l3_l5_l7_l8-supply = <&vreg_bob>; + vdd_l4_l6-supply = <&vreg_bob>; + vdd_bob-supply = <&vph_pwr>; + + vreg_s2b_1p05: s2 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + vreg_l1b_0p925: l1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <925000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l2b_2p95: l2 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l4b_2p95: l4 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <2952000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + + regulator-min-microamp = <200>; + regulator-max-microamp = <600000>; + regulator-system-load = <570000>; + regulator-allow-set-load; + }; + + /* + * Downstream specifies a range of 1721-3600mV, + * but the only assigned consumers are SDHCI2 VMMC + * and Coresight QPDI that both request pinned 2.95V. + * Tighten the range to 1.8-3.328 (closest to 3.3) to + * make the mmc driver happy. + */ + vreg_l5b_2p95: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3328000>; + regulator-enable-ramp-delay = <250>; + regulator-system-load = <800000>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l7b_3p125: l7 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3125000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l8b_3p3: l8 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3624000>; + regulator-enable-ramp-delay = <500>; + regulator-ramp-delay = <0>; + }; + }; +}; + +&sdhc_1 { + status = "okay"; + supports-cqe; + + vmmc-supply = <&vreg_l4b_2p95>; + vqmmc-supply = <&vreg_l8a_1p8>; + + mmc-ddr-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&sdhc_2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&sdc2_state_on &sdc2_card_det_n>; + pinctrl1 = <&sdc2_state_off &sdc2_card_det_n>; + + vmmc-supply = <&vreg_l5b_2p95>; + vqmmc-supply = <&vreg_l2b_2p95>; + + cd-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>; + no-sdio; + no-emmc; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <8 4>; + + sdc2_card_det_n: sd-card-det-n { + pins = "gpio54"; + function = "gpio"; + bias-pull-up; + }; +}; + +&usb2 { + status = "okay"; +}; + +&usb2_dwc3 { + dr_mode = "host"; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; + extcon = <&extcon_usb>; +}; From patchwork Fri May 13 23:45:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 572638 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBC6DC433EF for ; Sat, 14 May 2022 01:41:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229613AbiENBlm (ORCPT ); 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Fri, 13 May 2022 16:45:28 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 8/8] dt-bindings: arm: qcom: document sda660 SoC and ifc6560 board Date: Sat, 14 May 2022 02:45:18 +0300 Message-Id: <20220513234518.3068480-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220513234518.3068480-1-dmitry.baryshkov@linaro.org> References: <20220513234518.3068480-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add binding documentation for the Inforce IFC6560 board which uses Snapdragon SDA660. Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 129cdd246223..ac4ee0f874ea 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -41,6 +41,7 @@ description: | sa8155p sc7180 sc7280 + sda660 sdm630 sdm632 sdm660 @@ -225,6 +226,11 @@ properties: - google,senor - const: qcom,sc7280 + - items: + - enum: + - inforce,ifc6560 + - const: qcom,sda660 + - items: - enum: - fairphone,fp3