From patchwork Thu May 12 23:43:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 571900 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A70DC4167E for ; Thu, 12 May 2022 23:44:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359595AbiELXoB (ORCPT ); Thu, 12 May 2022 19:44:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359601AbiELXny (ORCPT ); Thu, 12 May 2022 19:43:54 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FE1F289BE4 for ; Thu, 12 May 2022 16:43:52 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id y32so11723942lfa.6 for ; Thu, 12 May 2022 16:43:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ypxafSXytWa1pPBeHJ41K2y3Cfr7QvnghKr6SvtMtAA=; b=HYYWbtOp+pyhDnTUwDvvkj8h1srbhPIfBQrtpDMd0/p71LPYf9kNeLldexP27+/IlA DKmuRETGMWTAzbrZXw7ckynx1W+70H39NaJvvf3MT69Hn5G51O66aJSgEGvPOCwCo8qF Di3kWKlEj/8J0u5nO6JkSomyt10yZY/QZ1ppBaBSlz6AGsaIV1xb6B1LEokUNgBZHD7J wX/bTUVuObqRSVHL8bZ/bI4jPbPt7yFJCf6WFHsZhrEx58he4AP6Dsi7KIQlhVzZ30sz CTfKOXYgA6Bs0sxGhywL77zjYp20skxWDiwfxpjBEZ1DD6SP2lOz9w9T39W7h6lFlF55 POJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ypxafSXytWa1pPBeHJ41K2y3Cfr7QvnghKr6SvtMtAA=; b=DXqIC9fBrz+6fmlkxJt4s1W9zD4Mu/2FkBKhQ9ZLUZ9huEQ7M7BgvLatAbAbjX/lqS As7alt1vgUWvl87l1CPKJ3w4Nl/T8lBOsSs/800u3yOfEFyTfNbDljDNuqnqiNZV3u6z OJqZWiWKc6EK82+cIbFupWosnkFJ2CbJvcSgd40QrssXy3LFEtdlxJS9rmPSptBpnlv3 Bu1UTTA3/uR++MLbFk+EzL6jWwusOk8k0bTna2NnwE+NRptc0bqrPNhLIKeCZRHTbcpb fcMzOqmGmf2PVz8ztVjocPfL9tzUafKLH3eR30z6P+OC6b/xWSBDR53myBiRR1W2HJ2l g7ZQ== X-Gm-Message-State: AOAM53063aIbbI/orzmXGt7dbSze80hUAEg7dAblDUncbR2esBCXi8PH MdMIKVHafbriW52+0u/laT3I1w== X-Google-Smtp-Source: ABdhPJzwJLrVsnKk3326SVHGPojUnjR52rHNQWh4Cw/dHGdl35TF1oIKYJTfyCkzUa59MR836Hx4hw== X-Received: by 2002:a05:6512:22c1:b0:46b:a2b7:2edd with SMTP id g1-20020a05651222c100b0046ba2b72eddmr1501962lfu.133.1652399030979; Thu, 12 May 2022 16:43:50 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id u10-20020ac248aa000000b0047255d211b8sm129976lfg.231.2022.05.12.16.43.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 May 2022 16:43:50 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Marijn Suijten Subject: [RESEND v2 1/8] arm64: dts: qcom: sdm660: disable dsi1/dsi1_phy by default Date: Fri, 13 May 2022 02:43:42 +0300 Message-Id: <20220512234349.2673724-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220512234349.2673724-1-dmitry.baryshkov@linaro.org> References: <20220512234349.2673724-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Follow the typical practice and keep DSI1/DSI1 PHY disabled by default. They should be enabled in the board DT files. No existing boards use them at this moment. Reviewed-by: Marijn Suijten Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm660.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi index eccf6fde16b4..023b0ac4118c 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -192,6 +192,8 @@ dsi1: dsi@c996000 { phys = <&dsi1_phy>; phy-names = "dsi"; + status = "disabled"; + ports { #address-cells = <1>; #size-cells = <0>; @@ -225,6 +227,7 @@ dsi1_phy: dsi-phy@c996400 { clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "iface", "ref"; + status = "disabled"; }; }; From patchwork Thu May 12 23:43:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 571901 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E873CC4321E for ; Thu, 12 May 2022 23:44:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359620AbiELXn7 (ORCPT ); Thu, 12 May 2022 19:43:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359610AbiELXn4 (ORCPT ); Thu, 12 May 2022 19:43:56 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DAE1D289BF5 for ; Thu, 12 May 2022 16:43:53 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id d19so11733400lfj.4 for ; Thu, 12 May 2022 16:43:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=i1goeg2wYzcHMfXO9CDFGJF9XLqANUBaSoksUz5XNRc=; b=AUSOaxGf4QvWFnxYykvOb6GQPte8Hm2nflFvbpNrV7v5k+oCT2+2v0h539XWv0UgtQ wx4FStpqIoFYYAI3xlJ3VNqXC0Kr5d8aoL/OTRci37kJXNq7/UuPS/Jm+AhmDOJgdi6u NHLll7b1x481IvBqecZqPHxTbN8WtovaBjjFq7gC2fomdbHV5ulL+zC2qYf5W22bsoqm KaFYaqy/2u042xxOWrIs4Chu5N/aoFso9QcgwHgb0wNOYc9GYAAIiwyunJrjSGnOTqhw tEJ01OB9H2SKIkS7NOXnqDBuH8spDSThVkMlB2q9mHqsLbyan+UTq4r0Glir36QAxrCM 6zwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=i1goeg2wYzcHMfXO9CDFGJF9XLqANUBaSoksUz5XNRc=; b=W3WCh02meW/vgOZwLlwgHNvuNTtFH4binqjEfV/HINVBfFhP9/pxMIy5/ly6bsnb9F SSSrOW9SBc60sYRORHwvJuE0SslDHNAhXKNTMzqKGJ6toWtoJVJY2dxcEa88kBgqp0kB 4jJ9YhNPCJefp8LsgQhzpfU+7lecmSMnDvVtZNlVYOrfPkGhA2Qjl3nNXYMEHERTHUBX UCKqC2z9jPjfdDJu2R33Kz9TPckjRpESl8xid6vB3uOqwAmpHYnRerCWT4LhlHe/aQhZ zgyBNI2rYMlFcKBVFgKaeAhfV501awX6Qctj9Le9ZP0wxuox8wdf0k1xOJxN23qnJxaq LxuA== X-Gm-Message-State: AOAM531ywX1fR3fZjmJQcmLsCJ5mq5AzMM3JrAzd7m56ud+56ol3rNSX bhLJ9jdlBCj6FKRcguYWS5rHTLe7tBm5LQ== X-Google-Smtp-Source: ABdhPJyZ4/wxLf8HN+jjarLtkCBweIJPNbWeRtrKWtIvGUJkDeQ6jmIG4vH6gc+Bz8rcNEESwYWV0g== X-Received: by 2002:a19:4315:0:b0:474:1ca5:c8e2 with SMTP id q21-20020a194315000000b004741ca5c8e2mr1503314lfa.4.1652399032285; Thu, 12 May 2022 16:43:52 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id u10-20020ac248aa000000b0047255d211b8sm129976lfg.231.2022.05.12.16.43.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 May 2022 16:43:51 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [RESEND v2 3/8] arm64: dts: qcom: sdm630: disable GPU by default Date: Fri, 13 May 2022 02:43:44 +0300 Message-Id: <20220512234349.2673724-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220512234349.2673724-1-dmitry.baryshkov@linaro.org> References: <20220512234349.2673724-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The SoC's device tree file disables gpucc and adreno's SMMU by default. So let's disable the GPU too. Moreover it looks like SMMU might be not usable without additional patches (which means that GPU is unusable too). No board uses GPU at this moment. Fixes: 5cf69dcbec8b ("arm64: dts: qcom: sdm630: Add Adreno 508 GPU configuration") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 8697d40e9b74..e8bb170e8b2f 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1050,6 +1050,8 @@ adreno_gpu: gpu@5000000 { operating-points-v2 = <&gpu_sdm630_opp_table>; + status = "disabled"; + gpu_sdm630_opp_table: opp-table { compatible = "operating-points-v2"; opp-775000000 { From patchwork Thu May 12 23:43:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 571898 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6078C433EF for ; Thu, 12 May 2022 23:44:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359643AbiELXoM (ORCPT ); Thu, 12 May 2022 19:44:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45414 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359611AbiELXoL (ORCPT ); Thu, 12 May 2022 19:44:11 -0400 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 85BC1289BF0 for ; Thu, 12 May 2022 16:43:55 -0700 (PDT) Received: by mail-lj1-x22f.google.com with SMTP id q130so8369563ljb.5 for ; Thu, 12 May 2022 16:43:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=u1F2z8vf2EByZAfH4u3WGQEipah84mZvdDX5pars+Lg=; b=YwUDsZZ/i1N7G2rbHoq/n8N9W9vEPgup0kjquj3LKMzsJH5QtDUmFd722aXOrADiFB Bfn00gA9IuzNeu8zSEBrLZOoFhDdXZIdqGO6L/zhoyTQb/rGUTqaatK8L8U3/g0OF7ue 7JB5S1/e6M5sw/6HC0fHADv/DtkgokWvTAnFYwP4cnWROBw5/klw11h33Bnrzl6bDDRh X+o2dJo1F2x4V5+bjn0fNNUSmUkZuxWL2Fe2xhmFDWVLhMZ72GspSo1UW4ejUCxorCiq 2aUvbTIFmnbzogzzRVTk2HG4NRap67JstbX82PksLVmTWW6C8+I88wPPE7YN2tdXyFo3 dY5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=u1F2z8vf2EByZAfH4u3WGQEipah84mZvdDX5pars+Lg=; b=g7mcH4uZiVXPsBct8wvYI+1k4qtGeDZFmdwatKfXNgPQ0Fh4yEusatdUO/rTNZ72r7 GAZsghEFxK0ENN3MuSE1bwmurxSYnncYge5BuXSys30bxL2on/vHQf5gvsH8S2E42UGH IA9EQ55Vh/A6JehzTEOLaQbRfUBp0RK365DTXdxNOuuEfl0rLEuGlyH/+hFLE9Hb+yjs tnB/QLWsMiEova/eCcpiDtLPVOiVgUZNYslMPs4aiLtMmHIXbjKCWJL1LxPajDxdg8fU vYYvZ5fp+DWKODvDqxAohjIU3BaSErWiTzyBkP/LnBCRJSwmnzdDTgqCBz9aSI5XepYg wGcw== X-Gm-Message-State: AOAM532Iswki2OT2MyK3rkiCrxrSkLNHivum7HDD5q9uR4mtn86g6abx LcWgmWBgpaKxf3VI/WET2HEM2g== X-Google-Smtp-Source: ABdhPJxxHZpHg/uxbWs7yQJNsGhxlkAS7AqvErxFJAbC1dYUvTgcx3h02IhwCKj7kbuCN2hAHz/TAA== X-Received: by 2002:a05:651c:1035:b0:250:ecad:d79 with SMTP id w21-20020a05651c103500b00250ecad0d79mr1453324ljm.397.1652399033796; Thu, 12 May 2022 16:43:53 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id u10-20020ac248aa000000b0047255d211b8sm129976lfg.231.2022.05.12.16.43.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 May 2022 16:43:53 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [RESEND v2 5/8] arm64: dts: qcom: sdm630: add second (HS) USB host support Date: Fri, 13 May 2022 02:43:46 +0300 Message-Id: <20220512234349.2673724-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220512234349.2673724-1-dmitry.baryshkov@linaro.org> References: <20220512234349.2673724-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT entries for the second DWC3 USB host, which is limited to the USB2.0 (HighSpeed), and the corresponding QUSB PHY. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 55 ++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index cca56f2fad96..17a1877587cf 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1270,6 +1270,20 @@ qusb2phy: phy@c012000 { status = "disabled"; }; + qusb2phy1: phy@c014000 { + compatible = "qcom,sdm660-qusb2-phy"; + reg = <0x0c014000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_RX1_USB2_CLKREF_CLK>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + nvmem-cells = <&qusb2_hstx_trim>; + status = "disabled"; + }; + sdhc_2: sdhci@c084000 { compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; reg = <0x0c084000 0x1000>; @@ -1375,6 +1389,47 @@ opp-384000000 { }; }; + usb2: usb@c2f8800 { + compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; + reg = <0x0c2f8800 0x400>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>, + <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_SLEEP_CLK>; + clock-names = "cfg_noc", "core", + "mock_utmi", "sleep"; + + assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, + <&gcc GCC_USB20_MASTER_CLK>; + assigned-clock-rates = <19200000>, <60000000>; + + interrupts = ; + interrupt-names = "hs_phy_irq"; + + qcom,select-utmi-as-pipe-clk; + + resets = <&gcc GCC_USB_20_BCR>; + + usb2_dwc3: usb@c200000 { + compatible = "snps,dwc3"; + reg = <0x0c200000 0xc8d0>; + interrupts = ; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + + /* This is the HS-only host */ + maximum-speed = "high-speed"; + phys = <&qusb2phy1>; + phy-names = "usb2-phy"; + snps,hird-threshold = /bits/ 8 <0>; + }; + }; + mmcc: clock-controller@c8c0000 { compatible = "qcom,mmcc-sdm630"; reg = <0x0c8c0000 0x40000>; From patchwork Thu May 12 23:43:47 2022 Content-Type: text/plain; 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Thu, 12 May 2022 16:43:54 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id u10-20020ac248aa000000b0047255d211b8sm129976lfg.231.2022.05.12.16.43.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 May 2022 16:43:54 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [RESEND v2 6/8] arm64: dts: qcom: sdm630: use defined symbols for interconnects Date: Fri, 13 May 2022 02:43:47 +0300 Message-Id: <20220512234349.2673724-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220512234349.2673724-1-dmitry.baryshkov@linaro.org> References: <20220512234349.2673724-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Replace numeric values with the symbolic names defined in the bindings header. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 17a1877587cf..01a1a1703568 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -1045,7 +1046,7 @@ adreno_gpu: gpu@5000000 { nvmem-cells = <&gpu_speed_bin>; nvmem-cell-names = "speed_bin"; - interconnects = <&gnoc 1 &bimc 5>; + interconnects = <&gnoc MASTER_APSS_PROC &bimc SLAVE_EBI>; interconnect-names = "gfx-mem"; operating-points-v2 = <&gpu_sdm630_opp_table>; @@ -1299,8 +1300,8 @@ sdhc_2: sdhci@c084000 { <&xo_board>; clock-names = "core", "iface", "xo"; - interconnects = <&a2noc 3 &a2noc 10>, - <&gnoc 0 &cnoc 28>; + interconnects = <&a2noc MASTER_SDCC_2 &a2noc SLAVE_A2NOC_SNOC>, + <&gnoc MASTER_APSS_PROC &cnoc SLAVE_SDCC_2>; operating-points-v2 = <&sdhc2_opp_table>; pinctrl-names = "default", "sleep"; @@ -1351,8 +1352,8 @@ sdhc_1: sdhci@c0c4000 { <&gcc GCC_SDCC1_ICE_CORE_CLK>; clock-names = "core", "iface", "xo", "ice"; - interconnects = <&a2noc 2 &a2noc 10>, - <&gnoc 0 &cnoc 27>; + interconnects = <&a2noc MASTER_SDCC_1 &a2noc SLAVE_A2NOC_SNOC>, + <&gnoc MASTER_APSS_PROC &cnoc SLAVE_SDCC_1>; interconnect-names = "sdhc1-ddr", "cpu-sdhc1"; operating-points-v2 = <&sdhc1_opp_table>; pinctrl-names = "default", "sleep"; @@ -1525,9 +1526,9 @@ mdp: mdp@c901000 { "core", "vsync"; - interconnects = <&mnoc 2 &bimc 5>, - <&mnoc 3 &bimc 5>, - <&gnoc 0 &mnoc 17>; + interconnects = <&mnoc MASTER_MDP_P0 &bimc SLAVE_EBI>, + <&mnoc MASTER_MDP_P1 &bimc SLAVE_EBI>, + <&gnoc MASTER_APSS_PROC &mnoc SLAVE_DISPLAY_CFG>; interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem"; @@ -2034,7 +2035,7 @@ camss: camss@ca00000 { "cphy_csid1", "cphy_csid2", "cphy_csid3"; - interconnects = <&mnoc 5 &bimc 5>; + interconnects = <&mnoc MASTER_VFE &bimc SLAVE_EBI>; interconnect-names = "vfe-mem"; iommus = <&mmss_smmu 0xc00>, <&mmss_smmu 0xc01>, @@ -2097,8 +2098,8 @@ venus: video-codec@cc00000 { <&mmcc VIDEO_AXI_CLK>, <&mmcc THROTTLE_VIDEO_AXI_CLK>; clock-names = "core", "iface", "bus", "bus_throttle"; - interconnects = <&gnoc 0 &mnoc 13>, - <&mnoc 4 &bimc 5>; + interconnects = <&gnoc MASTER_APSS_PROC &mnoc SLAVE_VENUS_CFG>, + <&mnoc MASTER_VENUS &bimc SLAVE_EBI>; interconnect-names = "cpu-cfg", "video-mem"; interrupts = ; iommus = <&mmss_smmu 0x400>,