From patchwork Sat May 7 20:36:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 570747 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8C44C433EF for ; Sat, 7 May 2022 20:36:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235554AbiEGUkN (ORCPT ); Sat, 7 May 2022 16:40:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233873AbiEGUkM (ORCPT ); Sat, 7 May 2022 16:40:12 -0400 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 119EB1401C; Sat, 7 May 2022 13:36:25 -0700 (PDT) Received: by mail-ed1-x536.google.com with SMTP id d6so12151402ede.8; Sat, 07 May 2022 13:36:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=noiLEGjS69TNqfsR+PPtmcT72BXbzXlEteGUOjRdti4=; b=BbA6bRIpdAWpIV9pvdRT9NeS4/gk+YGmY08PtHTCbxrs+qXW6etY3ymmfXnazN3urS 7IGH2l1Mjy/4xZBCzzsxtakmF6IuP8rIWpTNwhsGaiM/NAWfQA8ocCwU3Rl/q6xXQp5F 318mY0SRMIcKA5uVV6ffp/wA1IYqwhZ0nW9RLZ1eE/7JJRbhS611lp2qmAr5htzK+vkM k2MrrZGKepeqdwyTTyYk4AXm8AW6daF+ksb3D/4GVO8E8V0aswRNg8FIQAqDwAxx+5wR K69uS2wNfMhsrxNy8L6aImVDTCyjoAYhhehkJHZef2wtWyweTdFoyn+U3phI4hge2JvO ZBow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=noiLEGjS69TNqfsR+PPtmcT72BXbzXlEteGUOjRdti4=; b=CR5XB2CjLeJ+7uVsfvY2D6YTh++y1B9xdW9Ef0Mced3yu5I4pNBZkfd/s5QS/J60VX 93i8s7X7018g1UyRu8TzcionSxNpOmR2xBY//WfZZSAWrTYPtsleJNjKqleeKvrW9qoE Jx2eCk8wKXr8IDRhJgAmUrwxYYJEN4RwZFmbPhGgIJjwTOnHgOVYpmlN7prOvxk6yGzO q2lOC0fSvbI54gDS7gMmLhSzZvFPztd0J6Y587YfyZJslXPmyc9dPws/AD7GrY6kXhlg IbnRxi1++4JEgpzOdg6ItQZE5h/ien08G+O0qMMJaoRswJO2AjGmUs6I/c4Y6fV83B2x eBcA== X-Gm-Message-State: AOAM532slQb3HDdPjZvO8nXdxm+novSWcJ17lAjNRfkW343QjFM8P/Jz Qzl/E2HO//WSWj1sJoHMEkQ= X-Google-Smtp-Source: ABdhPJxFYtQqx07mssLwTTmx7D8Hn0EBF7PbzlW992Y0hSoBrZ3bUfAwQiFX/5Kffi1SkxyloczqBw== X-Received: by 2002:a05:6402:2318:b0:425:dd87:b4cd with SMTP id l24-20020a056402231800b00425dd87b4cdmr10111077eda.316.1651955783612; Sat, 07 May 2022 13:36:23 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-244-cbl.xnet.hr. [94.253.144.244]) by smtp.googlemail.com with ESMTPSA id eb20-20020a170907281400b006f4c557b7d2sm3283456ejc.203.2022.05.07.13.36.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 13:36:23 -0700 (PDT) From: Robert Marko To: agross@kernel.org, jassisinghbrar@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Cc: Robert Marko Subject: [PATCH v3 1/6] clk: qcom: clk-alpha-pll: add support for APSS PLL Date: Sat, 7 May 2022 22:36:15 +0200 Message-Id: <20220507203620.399028-1-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org APSS PLL type will be used by the IPQ8074 APSS driver for providing the CPU core clocks and enabling CPU Frequency scaling. This is ported from the downstream 5.4 kernel. Signed-off-by: Robert Marko --- drivers/clk/qcom/clk-alpha-pll.c | 12 ++++++++++++ drivers/clk/qcom/clk-alpha-pll.h | 1 + 2 files changed, 13 insertions(+) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 4406cf609aae..8270363ff98e 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -154,6 +154,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { [PLL_OFF_TEST_CTL_U] = 0x30, [PLL_OFF_TEST_CTL_U1] = 0x34, }, + [CLK_ALPHA_PLL_TYPE_APSS] = { + [PLL_OFF_L_VAL] = 0x08, + [PLL_OFF_ALPHA_VAL] = 0x10, + [PLL_OFF_ALPHA_VAL_U] = 0xff, + [PLL_OFF_USER_CTL] = 0x18, + [PLL_OFF_USER_CTL_U] = 0xff, + [PLL_OFF_CONFIG_CTL] = 0x20, + [PLL_OFF_CONFIG_CTL_U] = 0x24, + [PLL_OFF_TEST_CTL] = 0x30, + [PLL_OFF_TEST_CTL_U] = 0x34, + [PLL_OFF_STATUS] = 0x28, + }, }; EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 6e9907deaf30..626fdf80336d 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -18,6 +18,7 @@ enum { CLK_ALPHA_PLL_TYPE_AGERA, CLK_ALPHA_PLL_TYPE_ZONDA, CLK_ALPHA_PLL_TYPE_LUCID_EVO, + CLK_ALPHA_PLL_TYPE_APSS, CLK_ALPHA_PLL_TYPE_MAX, }; From patchwork Sat May 7 20:36:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 570488 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E34BC433F5 for ; Sat, 7 May 2022 20:36:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1384083AbiEGUkP (ORCPT ); Sat, 7 May 2022 16:40:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345154AbiEGUkO (ORCPT ); Sat, 7 May 2022 16:40:14 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A756D1401C; Sat, 7 May 2022 13:36:26 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id y3so20088413ejo.12; Sat, 07 May 2022 13:36:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WTfXR0xPMf1GwhzCgPtnYbCFhGYrMS55yt3GLmdVE6Y=; b=nE3hyDr/dmSO1jLuH3Q7369AG/hxuQ98kISyIjkiAxQ0GNB2/2rVyXOtT3WUnbNsWE sC2eSiVuVFBcb+rPuNwzBCBQRG8MEHi2vLOQIaPrhHnmmoUPD8ScJJq4Kdv1vpP9fZF7 cw+GCxumvdNLSsqpCFLk2htR1YSd6TdQvTOC5x//X9pE7GzvzYiytFLh6orwZ1nskEG+ 6qLh/r/aDCShoOzTjhNi7aeZgIi8v/5cWqvFW6xme+Wxf7oVeh5SIUC9Cf70fp/02ZbM 6rmVBuSJVy7X5U9xaduWfIgAR6EpJlur6F3Jjghh7XGOfAnuuTWZupP2/95TGFPjVBb4 hpRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WTfXR0xPMf1GwhzCgPtnYbCFhGYrMS55yt3GLmdVE6Y=; b=qTYbswABQTzdI6+b6JdXCYn9fs9xhr/zuvqnMf+4yovcNgQeLfKnJIOv0rLvHsSIca 5WNUHr/B80fjfyKdIDbBU/fy2i+SWJ+kU2TGx6g71v+Ugy8zIcPoqeuRHJx0iUXJ0MIZ 13ghzul0Mh6Wr6xpBaRJ3r5H18bANoU6o9NT+dTU3DETqi+h/sTOMGJGCEPmmmUqAnFA mj43rEJdcAnFWOxdatmkxupsT7Um0Z+aLLGX/hnxKpzu9wpypEBvBrQ82Ennia9B+oAH /MCJfiqzJsd9S+XdXhKpNIZ3TuRCh9cpNMgPuuRviSUCysg1pP7w+lfEF5dxq6Ln4nz8 gkwA== X-Gm-Message-State: AOAM533HWagqPmHrKxdKzmkZiMeIFtClAPdrj8GqAYAvDdnK7l+DWtm6 FLgijuOEwcQlpxJXkQAOLbgCCo2d14lYgg== X-Google-Smtp-Source: ABdhPJxuG/q5Bd5k9ModQiEN1ygyUaknJ4C5akMeIlhG1GxwD8sVb/K2s1MUaPA9XeWhQRDxoHwQfQ== X-Received: by 2002:a17:907:3f26:b0:6f4:dc59:3cfe with SMTP id hq38-20020a1709073f2600b006f4dc593cfemr8602191ejc.528.1651955785253; Sat, 07 May 2022 13:36:25 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-244-cbl.xnet.hr. [94.253.144.244]) by smtp.googlemail.com with ESMTPSA id eb20-20020a170907281400b006f4c557b7d2sm3283456ejc.203.2022.05.07.13.36.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 13:36:24 -0700 (PDT) From: Robert Marko To: agross@kernel.org, jassisinghbrar@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Cc: Robert Marko Subject: [PATCH v3 2/6] dt-bindings: clock: Add support for IPQ8074 APSS clock controller Date: Sat, 7 May 2022 22:36:16 +0200 Message-Id: <20220507203620.399028-2-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220507203620.399028-1-robimarko@gmail.com> References: <20220507203620.399028-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add dt-binding for the IPQ8074 APSS clock controller which provides clocks to the CPU cores. Signed-off-by: Robert Marko Acked-by: Krzysztof Kozlowski --- Changes in v2: * Correct subject --- include/dt-bindings/clock/qcom,apss-ipq8074.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,apss-ipq8074.h diff --git a/include/dt-bindings/clock/qcom,apss-ipq8074.h b/include/dt-bindings/clock/qcom,apss-ipq8074.h new file mode 100644 index 000000000000..df07766b0146 --- /dev/null +++ b/include/dt-bindings/clock/qcom,apss-ipq8074.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLOCK_QCA_APSS_IPQ8074_H +#define _DT_BINDINGS_CLOCK_QCA_APSS_IPQ8074_H + +#define APSS_PLL_EARLY 0 +#define APSS_PLL 1 +#define APCS_ALIAS0_CLK_SRC 2 +#define APCS_ALIAS0_CORE_CLK 3 + +#endif From patchwork Sat May 7 20:36:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 570746 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49E46C433FE for ; Sat, 7 May 2022 20:36:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1387390AbiEGUkS (ORCPT ); Sat, 7 May 2022 16:40:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1386612AbiEGUkQ (ORCPT ); Sat, 7 May 2022 16:40:16 -0400 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5604D1401C; Sat, 7 May 2022 13:36:28 -0700 (PDT) Received: by mail-ej1-x62c.google.com with SMTP id dk23so20146747ejb.8; Sat, 07 May 2022 13:36:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dGJC+Bs+gJ1awQTG1Kw29NfK1ye6F6x7CH4HnoOeRyo=; b=flHfAiE30/Hb40tkBXXoAM5C+a6d/l1KvyOO3mN8S/w4tR+hXKvqtZisa3kEEio3Jk U5dDGL9qyxS5V2hAbdKkfORSgAP4e6zXZQ1p0CK8y8+ThW6VX6Lx7V6Pn2h/OTRDgxa0 gdGaXeMmLGT+lWEVRMB7sh9hNL57xgLIlzqXWzoiyp4hUXJcMGjN+Yq/9aFNnoMBz81w AyBsLCXc2LsX+yADSasqYFhe+VRCbbIaONvXeB1xU2WubpwD2QncnoMAkp9j9fHGduef RJC4ccXhYg5pyNXh/2ywFgw2zSLgd/owWfe/i9VogxnEh1hZWZ7aRs4TFCJWQ6/6xAIm R2vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dGJC+Bs+gJ1awQTG1Kw29NfK1ye6F6x7CH4HnoOeRyo=; b=cgmEaHVZmIxnJ8D8oQ4V4Hm6r/WgIRmmwR7tRNVhvaoHMBjmyMSvfCibWUJDe+Jlf9 zVvNoGRXMpPY0RlWJapO05aE0DkEla8WJ/T6WnIofqgp5oPVj2/v+tnJqtmACkIU9UXP 01lqvH/Cb0skjtMZ4jjLfJ7D6QHf+bkX6XKuCpBqjs98JqsaPXpyHlB1/YArHhBT1XC5 Sc33wEaAC0Zp175ZsY5oOuqOl/01I7Pa+KwFK1x1bK4AaK5A2oIUmAT0KBWS/si8QD7e 6/8kORdEQqMjGBv2/uuUCZe2Nzdk4iCjXuJ5qZmZwwdaYyX72p4T42CL6gb4walRWqS3 LyTw== X-Gm-Message-State: AOAM531PEBJ6b1Ddg5l2jmC1wOT37teNNA6HO2NCnnHR8alPomCgyQTk 18rNyCTQodrrnGAcZciYyTE= X-Google-Smtp-Source: ABdhPJxMDTVQIWK2z2p/nOL15ScK/6xRLlF8wyhdKMIS59iMNoev6QTvFUuyKAJxJYAXlxnFkMt0qA== X-Received: by 2002:a17:907:d29:b0:6f4:87d4:ecad with SMTP id gn41-20020a1709070d2900b006f487d4ecadmr8218690ejc.166.1651955786873; Sat, 07 May 2022 13:36:26 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-244-cbl.xnet.hr. [94.253.144.244]) by smtp.googlemail.com with ESMTPSA id eb20-20020a170907281400b006f4c557b7d2sm3283456ejc.203.2022.05.07.13.36.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 13:36:26 -0700 (PDT) From: Robert Marko To: agross@kernel.org, jassisinghbrar@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Cc: Robert Marko , Ansuel Smith Subject: [PATCH v3 3/6] clk: qcom: Add IPQ8074 APSS clock controller Date: Sat, 7 May 2022 22:36:17 +0200 Message-Id: <20220507203620.399028-3-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220507203620.399028-1-robimarko@gmail.com> References: <20220507203620.399028-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org IPQ8074 APSS clock controller provides the clock for the IPQ8074 CPU cores, thus also providing support for CPU frequency scaling. It looks like they are clocked by the XO and a custom APSS type PLL. Co-developed-by: Ansuel Smith Signed-off-by: Ansuel Smith Signed-off-by: Robert Marko --- Changes in v2: * Convert to using parent-data instead of parent-names --- drivers/clk/qcom/Kconfig | 11 +++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/apss-ipq8074.c | 170 ++++++++++++++++++++++++++++++++ 3 files changed, 182 insertions(+) create mode 100644 drivers/clk/qcom/apss-ipq8074.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 00fe5f066de5..9494eb74374a 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -134,6 +134,17 @@ config IPQ_APSS_6018 Say Y if you want to support CPU frequency scaling on ipq based devices. +config IPQ_APSS_8074 + tristate "IPQ8074 APSS Clock Controller" + select IPQ_GCC_8074 + depends on QCOM_APCS_IPC || COMPILE_TEST + help + Support for APSS clock controller on IPQ8074 platforms. The + APSS clock controller manages the Mux and enable block that feeds the + CPUs. + Say Y if you want to support CPU frequency scaling on + IPQ8074 based devices. + config IPQ_GCC_4019 tristate "IPQ4019 Global Clock Controller" help diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 671cf5821af1..7b2da6dd570c 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o +obj-$(CONFIG_IPQ_APSS_8074) += apss-ipq8074.o obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o diff --git a/drivers/clk/qcom/apss-ipq8074.c b/drivers/clk/qcom/apss-ipq8074.c new file mode 100644 index 000000000000..38d03cd0ff76 --- /dev/null +++ b/drivers/clk/qcom/apss-ipq8074.c @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2022, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include + +#include "common.h" +#include "clk-regmap.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-branch.h" +#include "clk-alpha-pll.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" + +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } + +enum { + P_XO, + P_GPLL0, + P_GPLL2, + P_GPLL4, + P_APSS_PLL_EARLY, + P_APSS_PLL +}; + +static struct clk_alpha_pll apss_pll_early = { + .offset = 0x5000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_APSS], + .clkr = { + .enable_reg = 0x5000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "apss_pll_early", + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xo", .name = "xo" + }, + .num_parents = 1, + .ops = &clk_alpha_pll_huayra_ops, + }, + }, +}; + +static struct clk_alpha_pll_postdiv apss_pll = { + .offset = 0x5000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_APSS], + .width = 2, + .clkr.hw.init = &(struct clk_init_data){ + .name = "apss_pll", + .parent_hws = (const struct clk_hw *[]){ + &apss_pll_early.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + }, +}; + +static const struct clk_parent_data parents_apcs_alias0_clk_src[] = { + { .fw_name = "xo", .name = "xo" }, + { .fw_name = "gpll0", .name = "gpll0" }, + { .fw_name = "gpll2", .name = "gpll2" }, + { .fw_name = "gpll4", .name = "gpll4" }, + { .hw = &apss_pll.clkr.hw }, + { .hw = &apss_pll_early.clkr.hw }, +}; + +static const struct parent_map parents_apcs_alias0_clk_src_map[] = { + { P_XO, 0 }, + { P_GPLL0, 4 }, + { P_GPLL2, 2 }, + { P_GPLL4, 1 }, + { P_APSS_PLL, 3 }, + { P_APSS_PLL_EARLY, 5 }, +}; + +struct freq_tbl ftbl_apcs_alias0_clk_src[] = { + F(19200000, P_XO, 1, 0, 0), + F(403200000, P_APSS_PLL_EARLY, 1, 0, 0), + F(806400000, P_APSS_PLL_EARLY, 1, 0, 0), + F(1017600000, P_APSS_PLL_EARLY, 1, 0, 0), + F(1382400000, P_APSS_PLL_EARLY, 1, 0, 0), + F(1651200000, P_APSS_PLL_EARLY, 1, 0, 0), + F(1843200000, P_APSS_PLL_EARLY, 1, 0, 0), + F(1920000000, P_APSS_PLL_EARLY, 1, 0, 0), + F(2208000000UL, P_APSS_PLL_EARLY, 1, 0, 0), + { } +}; + +struct clk_rcg2 apcs_alias0_clk_src = { + .cmd_rcgr = 0x0050, + .freq_tbl = ftbl_apcs_alias0_clk_src, + .hid_width = 5, + .parent_map = parents_apcs_alias0_clk_src_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "apcs_alias0_clk_src", + .parent_data = parents_apcs_alias0_clk_src, + .num_parents = ARRAY_SIZE(parents_apcs_alias0_clk_src), + .ops = &clk_rcg2_ops, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_branch apcs_alias0_core_clk = { + .halt_reg = 0x0058, + .halt_bit = 31, + .clkr = { + .enable_reg = 0x0058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "apcs_alias0_core_clk", + .parent_hws = (const struct clk_hw *[]){ + &apcs_alias0_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT | + CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *apss_ipq8074_clks[] = { + [APSS_PLL_EARLY] = &apss_pll_early.clkr, + [APSS_PLL] = &apss_pll.clkr, + [APCS_ALIAS0_CLK_SRC] = &apcs_alias0_clk_src.clkr, + [APCS_ALIAS0_CORE_CLK] = &apcs_alias0_core_clk.clkr, +}; + +static const struct regmap_config apss_ipq8074_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x5ffc, + .fast_io = true, +}; + +static const struct qcom_cc_desc apss_ipq8074_desc = { + .config = &apss_ipq8074_regmap_config, + .clks = apss_ipq8074_clks, + .num_clks = ARRAY_SIZE(apss_ipq8074_clks), +}; + +static int apss_ipq8074_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = dev_get_regmap(pdev->dev.parent, NULL); + if (!regmap) + return -ENODEV; + + return qcom_cc_really_probe(pdev, &apss_ipq8074_desc, regmap); +} + +static struct platform_driver apss_ipq8074_driver = { + .probe = apss_ipq8074_probe, + .driver = { + .name = "qcom,apss-ipq8074-clk", + }, +}; + +module_platform_driver(apss_ipq8074_driver); + +MODULE_DESCRIPTION("Qualcomm IPQ8074 APSS clock driver"); +MODULE_LICENSE("GPL"); From patchwork Sat May 7 20:36:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 570487 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58F3DC433F5 for ; Sat, 7 May 2022 20:36:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1447045AbiEGUkX (ORCPT ); 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[94.253.144.244]) by smtp.googlemail.com with ESMTPSA id eb20-20020a170907281400b006f4c557b7d2sm3283456ejc.203.2022.05.07.13.36.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 13:36:27 -0700 (PDT) From: Robert Marko To: agross@kernel.org, jassisinghbrar@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Cc: Robert Marko Subject: [PATCH v3 4/6] mailbox: qcom-apcs-ipc: add IPQ8074 APSS clock controller support Date: Sat, 7 May 2022 22:36:18 +0200 Message-Id: <20220507203620.399028-4-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220507203620.399028-1-robimarko@gmail.com> References: <20220507203620.399028-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org IPQ8074 has the APSS clock controller utilizing the same register space as the APCS, so provide access to the APSS utilizing a child device like IPQ6018 does as well, but just by utilizing the IPQ8074 specific APSS clock driver. Also, APCS register space in IPQ8074 is 0x6000 so max_register needs to be updated to 0x5FFC. Signed-off-by: Robert Marko --- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c index 80a54d81412e..b3b9debf5673 100644 --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c @@ -33,6 +33,10 @@ static const struct qcom_apcs_ipc_data ipq6018_apcs_data = { .offset = 8, .clk_name = "qcom,apss-ipq6018-clk" }; +static const struct qcom_apcs_ipc_data ipq8074_apcs_data = { + .offset = 8, .clk_name = "qcom,apss-ipq8074-clk" +}; + static const struct qcom_apcs_ipc_data msm8916_apcs_data = { .offset = 8, .clk_name = "qcom-apcs-msm8916-clk" }; @@ -57,7 +61,7 @@ static const struct regmap_config apcs_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, - .max_register = 0x1008, + .max_register = 0x5FFC, .fast_io = true, }; @@ -142,7 +146,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev) /* .data is the offset of the ipc register within the global block */ static const struct of_device_id qcom_apcs_ipc_of_match[] = { { .compatible = "qcom,ipq6018-apcs-apps-global", .data = &ipq6018_apcs_data }, - { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &msm8994_apcs_data }, + { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq8074_apcs_data }, { .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data }, { .compatible = "qcom,msm8939-apcs-kpss-global", .data = &msm8916_apcs_data }, { .compatible = "qcom,msm8953-apcs-kpss-global", .data = &msm8994_apcs_data }, From patchwork Sat May 7 20:36:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 570745 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 253A5C4332F for ; Sat, 7 May 2022 20:36:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1447012AbiEGUk0 (ORCPT ); Sat, 7 May 2022 16:40:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36756 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1446964AbiEGUkX (ORCPT ); Sat, 7 May 2022 16:40:23 -0400 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7094A1A050; Sat, 7 May 2022 13:36:31 -0700 (PDT) Received: by mail-ej1-x633.google.com with SMTP id i19so20127463eja.11; Sat, 07 May 2022 13:36:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ViM0XELfh6s+qiFABkqI+WbFDa/9aqIqNljn2rQxT14=; b=IdCY/VJLdYjQVcGYDHv7DvvY5cu2OiukGHDORUQZ+u6vsNKSWmPHlksbbSOE1fmAq0 qF/8m3aGhlnJnfqd0Zdnjpm7Rh80sBGF7jXmOxUD7DFGVJnLni6N19127kChoGrN9GgZ MwnJlM816XDaj7LgmyLsdp8uEYYks0D3uJEK2ZeQWS1nihti6p7wmpVnhonlNVt0lr4o m6Osoixe4QQo9/0YetCP1zchceZS0UTd3DaaGkp4CYDbvLyuGqKiNI+k77Gf40cRju/l v+o9qYFX4oq6KSquBirv+4oMZ05tKzpEqBw+y0y6xHD8hfX/qbgu+pKet7uhFN9qEd9s 9DmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ViM0XELfh6s+qiFABkqI+WbFDa/9aqIqNljn2rQxT14=; b=wi/8cs+vFIXyFQjyC9A+mcWyIDZpxbO7+eKCtnyJPzKnyuOeYdY0xZX/j55GH4rdja bXRpX1Ri6qGSaTRqHFdAALpXCIvofYGmkiFWvHaCPBo+bSjQvxHGfkECbvgBVj+6JRqc u4G3AIhf5f4KN0GCT4U5V1S/akyPJAwXPjE3FQ9clGX2s+TSGuGXaeBvKGR+WCu7/r+j iGF6D+poVqt5edwcHd9y758ES4M9lHiXWrEBS7jcteW0XIqSfkyzUL4uFRwHrTmcLkJK zJIbv9fowILPQs6Rt8T1Nb3tWazgUtXye6U9ztuTUS/X4aCi6y4sxY+JtYy8aFlyxf4F ns+g== X-Gm-Message-State: AOAM532OX6INfVqjH+htDeLw6IjVClVsxlwqCT9x62bwbWIDFiBLHxW+ VXG3S09VSKhjVA2kX79np0w= X-Google-Smtp-Source: ABdhPJyAWz0k/PgBD35GMC/k388JZ3mysq4UwEtLRYReoczgLVdPeqYR4xcR6RyBXqlMaq6MUAaMOw== X-Received: by 2002:a17:906:d552:b0:6f8:6136:d0a0 with SMTP id cr18-20020a170906d55200b006f86136d0a0mr2926688ejc.366.1651955789840; Sat, 07 May 2022 13:36:29 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-244-cbl.xnet.hr. [94.253.144.244]) by smtp.googlemail.com with ESMTPSA id eb20-20020a170907281400b006f4c557b7d2sm3283456ejc.203.2022.05.07.13.36.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 13:36:29 -0700 (PDT) From: Robert Marko To: agross@kernel.org, jassisinghbrar@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Cc: Robert Marko , Krzysztof Kozlowski Subject: [PATCH v3 5/6] dt-bindings: mailbox: qcom: set correct #clock-cells Date: Sat, 7 May 2022 22:36:19 +0200 Message-Id: <20220507203620.399028-5-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220507203620.399028-1-robimarko@gmail.com> References: <20220507203620.399028-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org IPQ6018 and IPQ8074 require #clock-cells to be set to 1 as their APSS clock driver provides multiple clock outputs. So allow setting 1 as #clock-cells and check that its set to 1 for IPQ6018 and IPQ8074, check others for 0 as its currently. Signed-off-by: Robert Marko Reviewed-by: Krzysztof Kozlowski --- Changes in v3: * Drop not needed blank line Changes in v2: * Correct subject name --- .../bindings/mailbox/qcom,apcs-kpss-global.yaml | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index 3b5ba7ecc19d..95ecb84e3278 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -50,7 +50,7 @@ properties: const: 1 '#clock-cells': - const: 0 + enum: [0, 1] clock-names: minItems: 2 @@ -96,6 +96,21 @@ allOf: properties: clocks: maxItems: 3 + - if: + properties: + compatible: + enum: + - qcom,ipq6018-apcs-apps-global + - qcom,ipq8074-apcs-apps-global + then: + properties: + '#clock-cells': + const: 1 + else: + properties: + '#clock-cells': + const: 0 + examples: # Example apcs with msm8996 From patchwork Sat May 7 20:36:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 570486 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 937AEC433FE for ; Sat, 7 May 2022 20:36:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1387365AbiEGUkb (ORCPT ); Sat, 7 May 2022 16:40:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36792 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1447023AbiEGUkX (ORCPT ); Sat, 7 May 2022 16:40:23 -0400 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 18DA61A83A; Sat, 7 May 2022 13:36:33 -0700 (PDT) Received: by mail-ej1-x62a.google.com with SMTP id i19so20127514eja.11; Sat, 07 May 2022 13:36:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7DWoX9+H0DxYYZrmDNlSMsfSAn3l95094c1JRWnLT7M=; b=AenD+lrs+dbZfipB99nC/SkuwXSY9y7aLz1aNvVX3KuhfTydePoQhobTR1YZmakS9J fpUAKi8zgzpbhvXz89r7lEPz6/rHq6UK1bImTesNXqo0kGD52tC5u0aMhanaHeOZjtPo ijVhcRHHIgAU96ruRwJn+XS5dhgcMAIFatvWUB1hTLmZXHOFu7jkjaESle7EposTvUxJ +7uVJ4qyomMXuO4/BxHcxEaoOPhVJHbRzp+feYUcO7MwHGa0TXg18zygbRKcf+ulIYl7 0eQrr+h0TOSPL1j/YBnJK+E6wC23rCE7nas72qRFsGiFHb47gqZZh2ovHYlt0LW5b3Uv Ah1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7DWoX9+H0DxYYZrmDNlSMsfSAn3l95094c1JRWnLT7M=; b=0bv20Wbvs3tnB85qpfSM1IRyr1zaf1U4F9Zl0YVrawVn3DussRjm3Et4R+LilaJF1z cDBn9ddLSMbIj751HS047mZA7lY4sHj6qzK1Gu7x/mveLRvN2nC8xVC7A3B3oPY/CnyJ Y3M+CbWANK4JDTxbeQzdv2XonefZjDz4nSRCzUoYMxMfV94IuD01SXkve2eLigQqlrKs kILtudQwK3HRSLu2MOvT42zpXUrNa9MVHBJM79nxqNrMxw3hzcrIov8ATOOhofDlqrW4 8qzj5v/UjesX88WTvVCPdU/4h/be4Bgput3oWPDuoqyFMR/2yCefnjhtEfLXa7Tx0Bvs PXLg== X-Gm-Message-State: AOAM530cF1BrxczeX4RsTS/QkKeAmGmBT6S/lK5arLd8IQYLDjrl523/ RA18pHgqMU0ZTLNi+gu6BO+nJGxx2Rltgw== X-Google-Smtp-Source: ABdhPJxuH5K94XMR19pYP05cjMRB9Q7KjTAQoTwIfGqgCVeDwE3dKA6WgFxqpBNYl2rqszK0RxqJ3w== X-Received: by 2002:a17:907:9806:b0:6f5:f45:8736 with SMTP id ji6-20020a170907980600b006f50f458736mr8528972ejc.731.1651955791345; Sat, 07 May 2022 13:36:31 -0700 (PDT) Received: from fedora.robimarko.hr (cpezg-94-253-144-244-cbl.xnet.hr. [94.253.144.244]) by smtp.googlemail.com with ESMTPSA id eb20-20020a170907281400b006f4c557b7d2sm3283456ejc.203.2022.05.07.13.36.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 May 2022 13:36:31 -0700 (PDT) From: Robert Marko To: agross@kernel.org, jassisinghbrar@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org Cc: Robert Marko Subject: [PATCH v3 6/6] arm64: dts: ipq8074: add APCS node Date: Sat, 7 May 2022 22:36:20 +0200 Message-Id: <20220507203620.399028-6-robimarko@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220507203620.399028-1-robimarko@gmail.com> References: <20220507203620.399028-1-robimarko@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org APCS now has support for providing the APSS clocks as the child device for IPQ8074. So, add the required DT node for it as it will later be used as the CPU clocksource. Signed-off-by: Robert Marko --- Changes in v3: * Node does not currently exist in the upstream kernel, so add it instead of modifying. --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 0bc21b0c177f..271eb733f2c8 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -886,5 +886,13 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */ "axi_m_sticky"; status = "disabled"; }; + + apcs_glb: mailbox@b111000 { + compatible = "qcom,ipq8074-apcs-apps-global"; + reg = <0x0b111000 0x6000>; + + #clock-cells = <1>; + #mbox-cells = <1>; + }; }; };