From patchwork Thu May 5 19:45:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 570044 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFBA6C433F5 for ; Thu, 5 May 2022 19:46:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1385290AbiEETtx (ORCPT ); Thu, 5 May 2022 15:49:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1385294AbiEETtv (ORCPT ); Thu, 5 May 2022 15:49:51 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4821D5D651; Thu, 5 May 2022 12:46:11 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id 9FA281F45CC6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1651779970; bh=5Kcbcqr9OhmHIuCYNXcg4C+KzQ6qGeSuadFLlrIJIpI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ea29dOxZVnZfxMa8lHkkVZVcdYNA/IJW9A/OO8DPYVdpBx9E2IEP7OKdsAekp9IlG /NOoFuzjIX/C73+/b/njYYfStfREJ6dg+jd5C2ViKlHimpXa1rCxbDs//sGEr18atH sU7wovYGUidGjGXEwLvbl/jWKXKUSbEvsvJbrkjyVDNVMKnz5FV14FIVrBgvbVQZ9m j6ShUa/7LqVG86/oJRLW3Wqx78A1fQmsQVaELZdkMVXDGJnamVjHXZ4gV8IUa6HdDq 3pvQqX7hrCYkZWb+aWVEGIX0brnH+szPZBmV2Bz+/oYo70AzptrMw4Atvb4l27drJ8 cmxgDAcyMnAdw== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Chen-Yu Tsai , =?utf-8?b?TsOtY29s?= =?utf-8?b?YXMgRi4gUi4gQS4gUHJhZG8=?= , Allen-KH Cheng , Hsin-Yi Wang , Krzysztof Kozlowski , Maxim Kutnij , Rob Herring , Sam Shih , Sean Wang , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 02/16] dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-hayato Date: Thu, 5 May 2022 15:45:36 -0400 Message-Id: <20220505194550.3094656-3-nfraprado@collabora.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220505194550.3094656-1-nfraprado@collabora.com> References: <20220505194550.3094656-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add binding for the Google Hayato board. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- Changes in v2: - Added this patch Documentation/devicetree/bindings/arm/mediatek.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 43fc3417e786..bbe475788479 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -131,6 +131,11 @@ properties: - enum: - mediatek,mt8183-evb - const: mediatek,mt8183 + - description: Google Hayato + items: + - const: google,hayato-rev1 + - const: google,hayato + - const: mediatek,mt8192 - description: Google Spherion (Acer Chromebook 514) items: - const: google,spherion-rev3 From patchwork Thu May 5 19:45:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 570043 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CABC4C433EF for ; Thu, 5 May 2022 19:46:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1383031AbiEETuE (ORCPT ); Thu, 5 May 2022 15:50:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1385302AbiEETt5 (ORCPT ); Thu, 5 May 2022 15:49:57 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6413E5D645; Thu, 5 May 2022 12:46:17 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id B7ACC1F45CC6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1651779976; bh=9KGAf5hdHZB127eIs5P8+2H2JU2EwWKMyqvvcsvsETU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=n4+o6THEhmHSSB+EDl0I0M4qWz60BWuae9YbFhwP67bfCw5MqFHtqxmwkNF8QFcNM fUVY3Zw+BPkaDUXIGD+YxwYxYfhyi72I6iKnKYXZr+gaM+ItAd3L621DfdUO41GywB /e0RiEJLKg7tios7IvWPXk3FuUC/Y3/VWPayv7j8KPIeSc1OMWz1/xfRzAiua8Xncf 08qhlPFXm0LvobytR1xlvR4M087Z4fC5Rpo6ULqko2THnyBTvWW/gCUbp9zZrS1zz+ tIQIN3WZLBeJdxrGa6ybixd4afbfWe4dbVGmVS32VuKuKX81el5CQGTtNz7/QNw3Qo Fe4M7zECjSkhQ== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Chen-Yu Tsai , =?utf-8?b?TsOtY29s?= =?utf-8?b?YXMgRi4gUi4gQS4gUHJhZG8=?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 04/16] arm64: dts: mediatek: asurada: Document GPIO names Date: Thu, 5 May 2022 15:45:38 -0400 Message-Id: <20220505194550.3094656-5-nfraprado@collabora.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220505194550.3094656-1-nfraprado@collabora.com> References: <20220505194550.3094656-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the gpio-line-names property to gpio-controller in order to document the usage of GPIOs on the Asurada platform. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- (no changes since v1) .../boot/dts/mediatek/mt8192-asurada.dtsi | 228 ++++++++++++++++++ 1 file changed, 228 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 277bd38943fe..e10636298639 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -21,6 +21,234 @@ memory@40000000 { }; }; +&pio { + /* 220 lines */ + gpio-line-names = "I2S_DP_LRCK", + "IS_DP_BCLK", + "I2S_DP_MCLK", + "I2S_DP_DATAOUT", + "SAR0_INT_ODL", + "EC_AP_INT_ODL", + "EDPBRDG_INT_ODL", + "DPBRDG_INT_ODL", + "DPBRDG_PWREN", + "DPBRDG_RST_ODL", + "I2S_HP_MCLK", + "I2S_HP_BCK", + "I2S_HP_LRCK", + "I2S_HP_DATAIN", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it AP_FLASH_WP_ODL. + */ + "AP_FLASH_WP_L", + "TRACKPAD_INT_ODL", + "EC_AP_HPD_OD", + "SD_CD_ODL", + "HP_INT_ODL_ALC", + "EN_PP1000_DPBRDG", + "AP_GPIO20", + "TOUCH_INT_L_1V8", + "UART_BT_WAKE_ODL", + "AP_GPIO23", + "AP_SPI_FLASH_CS_L", + "AP_SPI_FLASH_CLK", + "EN_PP3300_DPBRDG_DX", + "AP_SPI_FLASH_MOSI", + "AP_SPI_FLASH_MISO", + "I2S_HP_DATAOUT", + "AP_GPIO30", + "I2S_SPKR_MCLK", + "I2S_SPKR_BCLK", + "I2S_SPKR_LRCK", + "I2S_SPKR_DATAIN", + "I2S_SPKR_DATAOUT", + "AP_SPI_H1_TPM_CLK", + "AP_SPI_H1_TPM_CS_L", + "AP_SPI_H1_TPM_MISO", + "AP_SPI_H1_TPM_MOSI", + "BL_PWM", + "EDPBRDG_PWREN", + "EDPBRDG_RST_ODL", + "EN_PP3300_HUB", + "HUB_RST_L", + "", + "", + "", + "", + "", + "", + "SD_CLK", + "SD_CMD", + "SD_DATA3", + "SD_DATA0", + "SD_DATA2", + "SD_DATA1", + "", + "", + "", + "", + "", + "", + "PCIE_WAKE_ODL", + "PCIE_RST_L", + "PCIE_CLKREQ_ODL", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SPMI_SCL", + "SPMI_SDA", + "AP_GOOD", + "UART_DBG_TX_AP_RX", + "UART_AP_TX_DBG_RX", + "UART_AP_TX_BT_RX", + "UART_BT_TX_AP_RX", + "MIPI_DPI_D0_R", + "MIPI_DPI_D1_R", + "MIPI_DPI_D2_R", + "MIPI_DPI_D3_R", + "MIPI_DPI_D4_R", + "MIPI_DPI_D5_R", + "MIPI_DPI_D6_R", + "MIPI_DPI_D7_R", + "MIPI_DPI_D8_R", + "MIPI_DPI_D9_R", + "MIPI_DPI_D10_R", + "", + "", + "MIPI_DPI_DE_R", + "MIPI_DPI_D11_R", + "MIPI_DPI_VSYNC_R", + "MIPI_DPI_CLK_R", + "MIPI_DPI_HSYNC_R", + "PCM_BT_DATAIN", + "PCM_BT_SYNC", + "PCM_BT_DATAOUT", + "PCM_BT_CLK", + "AP_I2C_AUDIO_SCL", + "AP_I2C_AUDIO_SDA", + "SCP_I2C_SCL", + "SCP_I2C_SDA", + "AP_I2C_WLAN_SCL", + "AP_I2C_WLAN_SDA", + "AP_I2C_DPBRDG_SCL", + "AP_I2C_DPBRDG_SDA", + "EN_PP1800_DPBRDG_DX", + "EN_PP3300_EDP_DX", + "EN_PP1800_EDPBRDG_DX", + "EN_PP1000_EDPBRDG", + "SCP_JTAG0_TDO", + "SCP_JTAG0_TDI", + "SCP_JTAG0_TMS", + "SCP_JTAG0_TCK", + "SCP_JTAG0_TRSTN", + "EN_PP3000_VMC_PMU", + "EN_PP3300_DISPLAY_DX", + "TOUCH_RST_L_1V8", + "TOUCH_REPORT_DISABLE", + "", + "", + "AP_I2C_TRACKPAD_SCL_1V8", + "AP_I2C_TRACKPAD_SDA_1V8", + "EN_PP3300_WLAN", + "BT_KILL_L", + "WIFI_KILL_L", + "SET_VMC_VOLT_AT_1V8", + "EN_SPK", + "AP_WARM_RST_REQ", + "", + "", + "EN_PP3000_SD_S3", + "AP_EDP_BKLTEN", + "", + "", + "", + "AP_SPI_EC_CLK", + "AP_SPI_EC_CS_L", + "AP_SPI_EC_MISO", + "AP_SPI_EC_MOSI", + "AP_I2C_EDPBRDG_SCL", + "AP_I2C_EDPBRDG_SDA", + "MT6315_PROC_INT", + "MT6315_GPU_INT", + "UART_SERVO_TX_SCP_RX", + "UART_SCP_TX_SERVO_RX", + "BT_RTS_AP_CTS", + "AP_RTS_BT_CTS", + "UART_AP_WAKE_BT_ODL", + "WLAN_ALERT_ODL", + "EC_IN_RW_ODL", + "H1_AP_INT_ODL", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "MSDC0_CMD", + "MSDC0_DAT0", + "MSDC0_DAT2", + "MSDC0_DAT4", + "MSDC0_DAT6", + "MSDC0_DAT1", + "MSDC0_DAT5", + "MSDC0_DAT7", + "MSDC0_DSL", + "MSDC0_CLK", + "MSDC0_DAT3", + "MSDC0_RST_L", + "SCP_VREQ_VAO", + "AUD_DAT_MOSI2", + "AUD_NLE_MOSI1", + "AUD_NLE_MOSI0", + "AUD_DAT_MISO2", + "AP_I2C_SAR_SDA", + "AP_I2C_SAR_SCL", + "AP_I2C_PWR_SCL", + "AP_I2C_PWR_SDA", + "AP_I2C_TS_SCL_1V8", + "AP_I2C_TS_SDA_1V8", + "SRCLKENA0", + "SRCLKENA1", + "AP_EC_WATCHDOG_L", + "PWRAP_SPI0_MI", + "PWRAP_SPI0_CSN", + "PWRAP_SPI0_MO", + "PWRAP_SPI0_CK", + "AP_RTC_CLK32K", + "AUD_CLK_MOSI", + "AUD_SYNC_MOSI", + "AUD_DAT_MOSI0", + "AUD_DAT_MOSI1", + "AUD_DAT_MISO0", + "AUD_DAT_MISO1"; +}; + &uart0 { status = "okay"; }; From patchwork Thu May 5 19:45:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 570042 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E68EC433FE for ; Thu, 5 May 2022 19:46:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1385302AbiEETuM (ORCPT ); Thu, 5 May 2022 15:50:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34850 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1385303AbiEETuL (ORCPT ); Thu, 5 May 2022 15:50:11 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A46B85D651; Thu, 5 May 2022 12:46:31 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id 8D1111F45CCB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1651779990; bh=I6V1qhlJl3e4i+gbr+q91PTZx0jogs0Jp+BzGxZx2KE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TW06FaAmI0ySY7OshRtxKpiWkT8By/BDpG0/bMqo7BdF1ZvxjVqFAOC5wrNrVHtUR WJAkewcDestegsNrKlFxerdHr6Pl2+/5VHqy/oK0yu/aay2lc5zmHI6LalzT/spr1y 89GihkT0L92RSIxX18NuevodbMabh6sZ+pbUyng3PIT16k8j5oioirdNbux/OmAghp iAVFdGyCWfy6tEkOxcIjwNrATs32aPF5eABgkKJJIo32jsiogZnwqCJ3lxMnAdemvb RqJDse0mK7FFnDO5WUTxS90w1F86oD1pFuM0EkMZMX9W6G6mP8rznAMg5ckXCycYYT /r4izLAdEGq+w== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Chen-Yu Tsai , =?utf-8?b?TsOtY29s?= =?utf-8?b?YXMgRi4gUi4gQS4gUHJhZG8=?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 06/16] arm64: dts: mediatek: asurada: Enable and configure I2C and SPI busses Date: Thu, 5 May 2022 15:45:40 -0400 Message-Id: <20220505194550.3094656-7-nfraprado@collabora.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220505194550.3094656-1-nfraprado@collabora.com> References: <20220505194550.3094656-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Asurada platform has five I2C controllers and two SPI controllers that are used. In preparation for enabling the devices connected to these controllers, enable and configure their busses. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- (no changes since v1) .../boot/dts/mediatek/mt8192-asurada.dtsi | 130 ++++++++++++++++++ 1 file changed, 130 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 5cb7580a13cf..3c5b1e475cf6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -85,6 +85,47 @@ ppvar_sys: ppvar-sys { }; }; +&i2c0 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; +}; + +&i2c1 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +}; + +&i2c2 { + status = "okay"; + + clock-frequency = <400000>; + clock-stretch-ns = <12600>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; +}; + +&i2c3 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; + +&i2c7 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_pins>; +}; + &pio { /* 220 lines */ gpio-line-names = "I2S_DP_LRCK", @@ -311,6 +352,95 @@ &pio { "AUD_DAT_MOSI1", "AUD_DAT_MISO0", "AUD_DAT_MISO1"; + + i2c0_pins: i2c0-default-pins { + pins-bus { + pinmux = , + ; + bias-pull-up; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <7>; + }; + }; + + i2c1_pins: i2c1-default-pins { + pins-bus { + pinmux = , + ; + bias-pull-up; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <7>; + }; + }; + + i2c2_pins: i2c2-default-pins { + pins-bus { + pinmux = , + ; + bias-pull-up; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <0>; + }; + }; + + i2c3_pins: i2c3-default-pins { + pins-bus { + pinmux = , + ; + bias-disable; + mediatek,drive-strength-adv = <7>; + }; + }; + + i2c7_pins: i2c7-default-pins { + pins-bus { + pinmux = , + ; + bias-disable; + mediatek,drive-strength-adv = <7>; + }; + }; + + spi1_pins: spi1-default-pins { + pins-cs-mosi-clk { + pinmux = , + , + ; + bias-disable; + }; + + pins-miso { + pinmux = ; + bias-pull-down; + }; + }; + + spi5_pins: spi5-default-pins { + pins-bus { + pinmux = , + , + , + ; + bias-disable; + }; + }; +}; + +&spi1 { + status = "okay"; + + mediatek,pad-select = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; +}; + +&spi5 { + status = "okay"; + + cs-gpios = <&pio 37 GPIO_ACTIVE_LOW>; + mediatek,pad-select = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi5_pins>; }; &uart0 { From patchwork Thu May 5 19:45:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 570041 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F02EDC433F5 for ; Thu, 5 May 2022 19:46:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354742AbiEETu2 (ORCPT ); Thu, 5 May 2022 15:50:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35054 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1385343AbiEETuT (ORCPT ); Thu, 5 May 2022 15:50:19 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D5245D651; Thu, 5 May 2022 12:46:38 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id 1B9571F45CCD DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1651779997; bh=T51OK/vVhW36JlunHPrBRDVW5Rm5AifIL1V8W6fBY8E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FsRnU6UG3UgTCz1SocvQc9D26+Rih/z1frhQXpJMHYd3Jr6cX/jBWl8/5/3EsATUI rx9M01vWO6o7C6w3BIU4sFNFND3/66m3LmoPMFMzJ8I68t0YwEQnYlnlUVO9EwM4va lpR8Qopc5wGhBIWVVxH2JFNIbxbJaHSCCcCVcu7ngtznSl87qThvwgrHHJjc74KNJT z4CSPH+pH6nuxckVLbSr2e5kTfRNbBulrzQDGerPmxHIfhhJKUgXqdUzKNM6gaTFbA je2Le7PNhrO21y/z/GNYT1ZxhBoG7Kv+r15OeOPxYbyMN5UvQ1BCuo+DZ4ri/V07Kf SbJhrPNPAcLtA== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Chen-Yu Tsai , =?utf-8?b?TsOtY29s?= =?utf-8?b?YXMgRi4gUi4gQS4gUHJhZG8=?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 08/16] arm64: dts: mediatek: asurada: Add keyboard mapping for the top row Date: Thu, 5 May 2022 15:45:42 -0400 Message-Id: <20220505194550.3094656-9-nfraprado@collabora.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220505194550.3094656-1-nfraprado@collabora.com> References: <20220505194550.3094656-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Chromebooks' embedded keyboards differ from standard layouts for the top row in that they have shortcuts in place of the standard function keys. Map these keys to achieve the functionality that is pictured on the printouts. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- (no changes since v1) .../boot/dts/mediatek/mt8192-asurada.dtsi | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 662207d0eb75..a1cbf7a375b6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -525,3 +525,32 @@ &uart0 { #include #include + +&keyboard_controller { + function-row-physmap = < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + + CROS_STD_MAIN_KEYMAP + >; +}; From patchwork Thu May 5 19:45:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 570040 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0FA1C433EF for ; Thu, 5 May 2022 19:46:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1385364AbiEETud (ORCPT ); Thu, 5 May 2022 15:50:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35462 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1385374AbiEETub (ORCPT ); Thu, 5 May 2022 15:50:31 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 942565E74E; Thu, 5 May 2022 12:46:44 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id D308A1F45CD0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1651780003; bh=Dj7vGkYC2BwaxdlFtxv9aMWMtotDYi0t1OanA82gQVk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ob34YrajdxH8LFFr/Uzcr6LQXBusD66HfS6+XCkQgwF+9I7/dqzTSip4UumJ4ElDm 4gctg/6716y5yLvdh//RAFfzEe8J6t0Ncmt/4HFojagHFvLoK04+slvMT7QaTb2lKE qGQcN6oGcWHVmnXfQLuKrvPsz3uE/IUGlkqv4X1JErzfPjIv0qPZka/2oz0Myn9dlb M4QnLgRAtia18gCJqu6J3PJ5UTWtGu96zvoHzyKo0/Ac5R1zUEUOTC5LGC4yin5Q+c 3gij+MxiX93X0p3kLNn+a8K63GVV75bhsOXAPlctkv1Vx8K01hRGrRMeoPUA1SxjYx 8HbVB94qzSN7w== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Chen-Yu Tsai , =?utf-8?b?TsOtY29s?= =?utf-8?b?YXMgRi4gUi4gQS4gUHJhZG8=?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 10/16] arm64: dts: mediatek: asurada: Add Elan eKTH3000 I2C trackpad Date: Thu, 5 May 2022 15:45:44 -0400 Message-Id: <20220505194550.3094656-11-nfraprado@collabora.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220505194550.3094656-1-nfraprado@collabora.com> References: <20220505194550.3094656-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for the Elan eKTH3000 i2c trackpad present on Asurada. It is connected to the I2C2 bus and has address 0x15. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- (no changes since v1) .../boot/dts/mediatek/mt8192-asurada.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 5221f1d1b7dc..a15e84d86449 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -109,6 +109,16 @@ &i2c2 { clock-stretch-ns = <12600>; pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins>; + + trackpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + interrupts-extended = <&pio 15 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_pins>; + vcc-supply = <&pp3300_u>; + wakeup-source; + }; }; &i2c3 { @@ -440,6 +450,14 @@ pins-bus { bias-disable; }; }; + + trackpad_pins: trackpad-default-pins { + pins-int-n { + pinmux = ; + input-enable; + mediatek,pull-up-adv = <3>; + }; + }; }; &spi1 { From patchwork Thu May 5 19:45:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 570039 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52226C433FE for ; Thu, 5 May 2022 19:47:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1385490AbiEETut (ORCPT ); Thu, 5 May 2022 15:50:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35646 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1385416AbiEETuf (ORCPT ); Thu, 5 May 2022 15:50:35 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9DF545EBD1; Thu, 5 May 2022 12:46:50 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id AC83F1F45CD2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1651780009; bh=8TvoEhGQU6t2qg9uM8iphoK/DuIcgX6ObTBGTPSxnTk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XSsfXvMh/3UvAYBBO5gWbz63asC1SxSMIAZvqX3j4MDRYYwGfClwFV3ak8VXdWV18 bqv0Bh+GBInZgOfD2LHapuhjie9qOp1OdtpVe4r5OREjgzG7zvI1lK4ulqRe2u9/Oi BGB/xUNuCMopwMrJnmU27zEjybmvzVd0qfrgolUngTt7beTEIafEG19kQzBpz/Wym+ eBGunoEKPuB4GDZfZEdeI7Gpaa+dPb3d8J4WgKx4zEvvUrvNPfepXdEoaVvolV/bAt pk4eKgKw+iuLd2pDB9EOAIWEwz09nXqgR2icBMdLX3MoaH6MHYFwYK+OT93OnNZn03 kg6aDjWuS0D1Q== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Chen-Yu Tsai , =?utf-8?b?TsOtY29s?= =?utf-8?b?YXMgRi4gUi4gQS4gUHJhZG8=?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 12/16] arm64: dts: mediatek: spherion: Add keyboard backlight Date: Thu, 5 May 2022 15:45:46 -0400 Message-Id: <20220505194550.3094656-13-nfraprado@collabora.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220505194550.3094656-1-nfraprado@collabora.com> References: <20220505194550.3094656-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Spherion board has keyboard backlight controlled by the PWM signal generated by the ChromeOS EC. Enable PWM output for ChromeOS EC and add a PWM controlled LED node for the keyboard backlight. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- (no changes since v1) .../dts/mediatek/mt8192-asurada-spherion-r0.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts index 35d9c5294fe0..7f9cf7ee1437 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts @@ -4,12 +4,28 @@ */ /dts-v1/; #include "mt8192-asurada.dtsi" +#include / { model = "Google Spherion (rev0 - 3)"; compatible = "google,spherion-rev3", "google,spherion-rev2", "google,spherion-rev1", "google,spherion-rev0", "google,spherion", "mediatek,mt8192"; + + pwmleds { + compatible = "pwm-leds"; + + led { + function = LED_FUNCTION_KBD_BACKLIGHT; + color = ; + pwms = <&cros_ec_pwm 0>; + max-brightness = <1023>; + }; + }; +}; + +&cros_ec_pwm { + status = "okay"; }; &touchscreen { From patchwork Thu May 5 19:45:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 570038 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9739C4332F for ; Thu, 5 May 2022 19:47:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1385363AbiEETu5 (ORCPT ); Thu, 5 May 2022 15:50:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35522 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238792AbiEETuk (ORCPT ); Thu, 5 May 2022 15:50:40 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B6D15E75B; Thu, 5 May 2022 12:46:56 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id 51B7B1F45CD4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1651780014; bh=xzUy2wIyZXyHws5Sfef8bUOIhBVmWMeAQk76VcEPaRI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eOVPVi70rUmGojFG3yEu34VRcLCOrYmReCGhcDWvQJ2s4HSOPhs4Gj+1janAdE+w+ UyXPLWUsJhooEqMvJ1dzcg2vuUnJeIvGe5zXkG8yxz3Gi7jS6Waa7FWzlkVZpF3BPd 8SJ12uM12ezZyu7YLHdTKy7QPFNBl/stxL34IXZiJG6CNpcvugBCGEFShYe0iCCK0W AMISaWJ0IBoxLmhmE7mZtHtgVBUlB2aysdQXLpi7sHmiw6oFXet2pJr2SmPML89+8O +6DOPUKVQY/dO2aCqIug8a5AGYxnq44atGQlD8CCO/2voZJXbfUuqXbi/o2Gfoz64C 6xeQciBOFYGFw== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Chen-Yu Tsai , =?utf-8?b?TsOtY29s?= =?utf-8?b?YXMgRi4gUi4gQS4gUHJhZG8=?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 14/16] arm64: dts: mediatek: asurada: Enable PCIe and add WiFi Date: Thu, 5 May 2022 15:45:48 -0400 Message-Id: <20220505194550.3094656-15-nfraprado@collabora.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220505194550.3094656-1-nfraprado@collabora.com> References: <20220505194550.3094656-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable MT8192's PCIe controller and add support for the MT7921e WiFi card that is present on that bus for the Asurada platform. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- Changes in v2: - Added this patch .../boot/dts/mediatek/mt8192-asurada.dtsi | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 4f9a9ec046b0..87a9a6b1eabc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -66,6 +66,19 @@ pp3300_u: pp3300-u { vin-supply = <&pp3300_g>; }; + pp3300_wlan: pp3300-wlan { + compatible = "regulator-fixed"; + regulator-name = "pp3300_wlan"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pp3300_wlan_pins>; + enable-active-high; + gpio = <&pio 143 GPIO_ACTIVE_HIGH>; + }; + /* system wide switching 5.0V power rail */ pp5000_a: pp5000-a { compatible = "regulator-fixed"; @@ -84,6 +97,17 @@ ppvar_sys: ppvar-sys { regulator-always-on; regulator-boot-on; }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + wifi_restricted_dma_region: wifi@c0000000 { + compatible = "restricted-dma-pool"; + reg = <0 0xc0000000 0 0x4000000>; + }; + }; }; &i2c0 { @@ -144,6 +168,28 @@ &i2c7 { pinctrl-0 = <&i2c7_pins>; }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + + pcie0: pcie@0,0 { + device_type = "pci"; + reg = <0x0000 0 0 0 0>; + num-lanes = <1>; + bus-range = <0x1 0x1>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + wifi: wifi@0,0 { + reg = <0x10000 0 0 0 0x100000>, + <0x10000 0 0x100000 0 0x100000>; + memory-region = <&wifi_restricted_dma_region>; + }; + }; +}; + &pio { /* 220 lines */ gpio-line-names = "I2S_DP_LRCK", @@ -434,6 +480,34 @@ pins-bus { }; }; + pcie_pins: pcie-default-pins { + pins-pcie-wake { + pinmux = ; + bias-pull-up; + }; + + pins-pcie-pereset { + pinmux = ; + }; + + pins-pcie-clkreq { + pinmux = ; + bias-pull-up; + }; + + pins-wifi-kill { + pinmux = ; /* WIFI_KILL_L */ + output-high; + }; + }; + + pp3300_wlan_pins: pp3300-wlan-pins { + pins-pcie-en-pp3300-wlan { + pinmux = ; + output-high; + }; + }; + spi1_pins: spi1-default-pins { pins-cs-mosi-clk { pinmux = , From patchwork Thu May 5 19:45:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 570037 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CEFCFC433EF for ; Thu, 5 May 2022 19:47:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1385400AbiEETvQ (ORCPT ); Thu, 5 May 2022 15:51:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35468 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1385368AbiEETun (ORCPT ); Thu, 5 May 2022 15:50:43 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A26D5DA7D; Thu, 5 May 2022 12:47:02 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: nfraprado) with ESMTPSA id A6FE71F45CD3 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1651780021; bh=riKUyF3QA26FPC6IN4C9exUYKfoEiGvXUwpYMcRDj7M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IEVITc3sCSDV2yoTf1mQwuHfgdj8nF+d/X2n/ZXKi5YwM4pS/WjEOl1DDvuWwo0cX HRjoOZee/WLN0iYDbwq3L9ydeRrTcCQoKLpcx3sD6uXW+L9di4gL1P7yjES8JrRTZW /PIYVbLAV0WClG+LBhsMYiLY/8LzDaRruJ/whCVuUVJngCTA1WixTyslwdSff4daGY S1mjJ6Uv2yolUv3Wcyb5cKE92j4ate6tCwKPdN+rxgyrb2k6tY1s/Lt5JHd2DrTKJ1 F4I3r5vPy3rqobPCxOvXQ9V6zXFeE1WG9wn3UTDOOPczbAqri0k0AX1IX5CBw5MNrz 5qD5Q98uEZ7nQ== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Chen-Yu Tsai , =?utf-8?b?TsOtY29s?= =?utf-8?b?YXMgRi4gUi4gQS4gUHJhZG8=?= , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 16/16] arm64: dts: mediatek: asurada: Add SPMI regulators Date: Thu, 5 May 2022 15:45:50 -0400 Message-Id: <20220505194550.3094656-17-nfraprado@collabora.com> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220505194550.3094656-1-nfraprado@collabora.com> References: <20220505194550.3094656-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Asurada platform uses regulators from MT6315 PMICs acessible through SPMI. Add support for them. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- Changes in v2: - Added this patch .../boot/dts/mediatek/mt8192-asurada.dtsi | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index a9ffa74b2764..7f4cee928f71 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -7,6 +7,7 @@ #include "mt8192.dtsi" #include "mt6359.dtsi" #include +#include / { aliases { @@ -683,6 +684,54 @@ cr50@0 { }; }; +&spmi { + #address-cells = <2>; + #size-cells = <0>; + + mt6315_6: pmic@6 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x6 SPMI_USID>; + + regulators { + mt6315_6_vbuck1: vbuck1 { + regulator-compatible = "vbuck1"; + regulator-name = "Vbcpu"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + + mt6315_6_vbuck3: vbuck3 { + regulator-compatible = "vbuck3"; + regulator-name = "Vlcpu"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + }; + }; + + mt6315_7: pmic@7 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x7 SPMI_USID>; + + regulators { + mt6315_7_vbuck1: vbuck1 { + regulator-compatible = "vbuck1"; + regulator-name = "Vgpu"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + }; + }; + }; +}; + &uart0 { status = "okay"; };