From patchwork Tue May 3 13:04:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 569079 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3168FC433F5 for ; Tue, 3 May 2022 13:05:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235811AbiECNIa (ORCPT ); Tue, 3 May 2022 09:08:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49044 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235795AbiECNI3 (ORCPT ); Tue, 3 May 2022 09:08:29 -0400 Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3AA9E387B7 for ; Tue, 3 May 2022 06:04:55 -0700 (PDT) Received: by mail-ej1-x62e.google.com with SMTP id dk23so33315811ejb.8 for ; Tue, 03 May 2022 06:04:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=vKhh0bhyLCkC5pTKYAdfR5BRKIIHfoHsreEDjsLLID4=; b=xXxe3Eycu6qRIC04JO+pavYVa/wqvhMc9smGHFZUbdmj6IOKVTiGR1DqFOoEpp4z4S LBrMFhmGqXKl1s5C60mxTirJ0AZSnDpF4eQGyY4bP768m/HKVxCFAvDZB9uEtfVKagR1 B3IFlu3hsQjZiinbEPXBAqidHewJKMpClSKwGYeDOpF9sjrd3Ve5CsxNeqybKcMBXHql 9g/cEJ+6RQsp3Tp35XB2DkvanqzRPKVYFtM+ztfdPzD3QyQyrgpxX1egAJLqV25wLsUW 1efvPBp3WXf54Vz18a91XbQu/92bVFgqkglbV5xmiFPkx0w+bSWHpmWCTqzkjY5qdtYP N28w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=vKhh0bhyLCkC5pTKYAdfR5BRKIIHfoHsreEDjsLLID4=; b=jfiHmKTYnBFgHS2m8vBZgiV9lQuU9Hf02bmZ2MItluN4w76IF5viCxEhjr+ELzSBjA iCUBaN9eAxsxnTn2hDWHqfVTjnlI1fWK21NmZWeeKdEzkFy+/PwokpoSeqvrUAKHyd+A kzZbm0WXS6kVbSFj2SoDX7B7idn4flPiEEgI8BZIk/9hm/b15mjdJI8yH1u3BoxXEnRf huJ7SZq8WgfeVzTKYnE7WRrNZfkJFTyaCzzFlj06vZdqpWKMRdBoZNwGuqTRHljH1GQB /pTJ2znY07SAHthPeOhRTCD3yMznn61aY1dkI6MqnCIyXr2qttiT7Own1cFmLaZ57YWQ CsJQ== X-Gm-Message-State: AOAM533b6Mlp2/zJBkXNveG7ZKFTWnWIHr5HVRBiUmluVs3R+Yh4Donw 4EibP3BKHxQ7sQ8tRUr2XxQvsw== X-Google-Smtp-Source: ABdhPJz+JcV4GpubVALOLerlASp0y4mGfBQsNh/CLjEdwGKiG4hGRMUXYaVdasEm22CLn5LbqcEyog== X-Received: by 2002:a17:907:3e8c:b0:6f4:4fdb:6f24 with SMTP id hs12-20020a1709073e8c00b006f44fdb6f24mr8997901ejc.44.1651583093752; Tue, 03 May 2022 06:04:53 -0700 (PDT) Received: from prec5560.. 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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id y13-20020aa7cccd000000b0042617ba639asm7868782edt.36.2022.05.03.06.04.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 May 2022 06:04:53 -0700 (PDT) From: Robert Foss To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, jonathan@marek.ca, tdas@codeaurora.org, anischal@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov Cc: Vinod Koul , Steev Klimaszewski Subject: [PATCH v2 1/8] clk: qcom: rcg2: Cache rate changes for parked RCGs Date: Tue, 3 May 2022 15:04:41 +0200 Message-Id: <20220503130448.520470-1-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Bjorn Andersson As GDSCs are turned on and off some associated clocks are momentarily enabled for house keeping purposes. Failure to enable these clocks seems to have been silently ignored in the past, but starting in SM8350 this failure will prevent the GDSC to turn on. At least on SM8350 this operation will enable the RCG per the configuration in CFG_REG. This means that the current model where the current configuration is written back to CF_REG immediately after parking the RCG doesn't work. Instead, keep track of the currently requested rate of the clock and upon enabling the clock reapply the configuration per the saved rate. Fixes: 7ef6f11887bd ("clk: qcom: Configure the RCGs to a safe source as needed") Signed-off-by: Bjorn Andersson Reviewed-by: Vinod Koul Tested-by: Steev Klimaszewski --- drivers/clk/qcom/clk-rcg.h | 2 ++ drivers/clk/qcom/clk-rcg2.c | 32 +++++++++++++++++--------------- 2 files changed, 19 insertions(+), 15 deletions(-) diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index 00cea508d49e..8b41244b8dbf 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -140,6 +140,7 @@ extern const struct clk_ops clk_dyn_rcg_ops; * @freq_tbl: frequency table * @clkr: regmap clock handle * @cfg_off: defines the cfg register offset from the CMD_RCGR + CFG_REG + * @current_rate: cached rate for parked RCGs */ struct clk_rcg2 { u32 cmd_rcgr; @@ -150,6 +151,7 @@ struct clk_rcg2 { const struct freq_tbl *freq_tbl; struct clk_regmap clkr; u8 cfg_off; + unsigned long current_rate; }; #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index f675fd969c4d..81fd3a2db709 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -167,6 +167,7 @@ clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask; + unsigned long rate; regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); @@ -186,7 +187,11 @@ clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) hid_div = cfg >> CFG_SRC_DIV_SHIFT; hid_div &= mask; - return calc_rate(parent_rate, m, n, mode, hid_div); + rate = calc_rate(parent_rate, m, n, mode, hid_div); + if (!rcg->current_rate) + rcg->current_rate = rate; + + return rate; } static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f, @@ -978,12 +983,14 @@ static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate, if (!f) return -EINVAL; + rcg->current_rate = rate; + /* - * In case clock is disabled, update the CFG, M, N and D registers - * and don't hit the update bit of CMD register. + * In the case that the shared RCG is parked, current_rate will be + * applied as the clock is unparked again, so just return here. */ if (!__clk_is_enabled(hw->clk)) - return __clk_rcg2_configure(rcg, f); + return 0; return clk_rcg2_shared_force_enable_clear(hw, f); } @@ -997,8 +1004,13 @@ static int clk_rcg2_shared_set_rate_and_parent(struct clk_hw *hw, static int clk_rcg2_shared_enable(struct clk_hw *hw) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); + const struct freq_tbl *f = NULL; int ret; + f = qcom_find_freq(rcg->freq_tbl, rcg->current_rate); + if (!f) + return -EINVAL; + /* * Set the update bit because required configuration has already * been written in clk_rcg2_shared_set_rate() @@ -1007,7 +1019,7 @@ static int clk_rcg2_shared_enable(struct clk_hw *hw) if (ret) return ret; - ret = update_config(rcg); + ret = clk_rcg2_configure(rcg, f); if (ret) return ret; @@ -1017,13 +1029,6 @@ static int clk_rcg2_shared_enable(struct clk_hw *hw) static void clk_rcg2_shared_disable(struct clk_hw *hw) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); - u32 cfg; - - /* - * Store current configuration as switching to safe source would clear - * the SRC and DIV of CFG register - */ - regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); /* * Park the RCG at a safe configuration - sourced off of safe source. @@ -1041,9 +1046,6 @@ static void clk_rcg2_shared_disable(struct clk_hw *hw) update_config(rcg); clk_rcg2_clear_force_enable(hw); - - /* Write back the stored configuration corresponding to current rate */ - regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg); } const struct clk_ops clk_rcg2_shared_ops = { From patchwork Tue May 3 13:04:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 569078 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93A39C4167D for ; Tue, 3 May 2022 13:05:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235785AbiECNIc (ORCPT ); Tue, 3 May 2022 09:08:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235798AbiECNIa (ORCPT ); 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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id y13-20020aa7cccd000000b0042617ba639asm7868782edt.36.2022.05.03.06.04.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 May 2022 06:04:55 -0700 (PDT) From: Robert Foss To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, jonathan@marek.ca, tdas@codeaurora.org, anischal@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov Cc: Vinod Koul Subject: [PATCH v2 3/8] clk: qcom: sm8250-dispcc: Flag shared RCGs as assumed enable Date: Tue, 3 May 2022 15:04:43 +0200 Message-Id: <20220503130448.520470-3-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220503130448.520470-1-robert.foss@linaro.org> References: <20220503130448.520470-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Bjorn Andersson The state of the shared RCGs found in the SM8250 dispcc can't reliably be queried and hence doesn't implement the is_enabled() callback. Mark the shared RCGs as CLK_ASSUME_ENABLED_WHEN_UNUSED, to ensure that clk_disable_unused() will issue a disable and park the RCGs before it turns off the parent PLLs - which will lock up these RCGs in any system with continuous splash enabled. Signed-off-by: Bjorn Andersson Reviewed-by: Vinod Koul --- drivers/clk/qcom/dispcc-sm8250.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index db9379634fb2..22d9cbabecab 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -214,7 +214,7 @@ static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { .name = "disp_cc_mdss_ahb_clk_src", .parent_data = disp_cc_parent_data_3, .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_ASSUME_ENABLED_WHEN_UNUSED, .ops = &clk_rcg2_shared_ops, }, }; @@ -546,7 +546,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { .name = "disp_cc_mdss_mdp_clk_src", .parent_data = disp_cc_parent_data_5, .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_ASSUME_ENABLED_WHEN_UNUSED, .ops = &clk_rcg2_shared_ops, }, }; @@ -598,7 +598,7 @@ static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { .name = "disp_cc_mdss_rot_clk_src", .parent_data = disp_cc_parent_data_5, .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_ASSUME_ENABLED_WHEN_UNUSED, .ops = &clk_rcg2_shared_ops, }, }; From patchwork Tue May 3 13:04:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 569077 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FB12C4332F for ; Tue, 3 May 2022 13:05:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235843AbiECNIf (ORCPT ); Tue, 3 May 2022 09:08:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49212 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235820AbiECNId (ORCPT ); Tue, 3 May 2022 09:08:33 -0400 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8D89245AD for ; Tue, 3 May 2022 06:05:00 -0700 (PDT) Received: by mail-ej1-x62c.google.com with SMTP id kq17so33323653ejb.4 for ; Tue, 03 May 2022 06:05:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rOsJ9Zrz7rA4F/2ineOAizsi6mknMU/UXeuWBA/JKfA=; b=U6leyOc4PR5xVs7AFN2B+5EUZ25Eq16L2YBKHN1RSYWmLmTsJLKoJWrDJCQFhEmka9 jLs92EDKpNXIuq2kblx6rXcc36SbyY3cfl3KpnjZc3W3Mmr7SL9eRP715QZsYFE+8IYQ dBZzTG8ZFAWpTHLa9TdG2/lO15NDdpTNmhBiNZ2h2NZ2p4Dp6tnBZoqXGNEC8PhCixx7 8Z7cZEXHL3wo992HOSFiHuuSKaFh/NtSVYWCRIhAPmaVvZ/yY323adDL1SOGZLQyAVT9 EoJWe82PCeUlyY0Uf6r016cV7WOhjTb7sovR1HFec/nvpXBED17x6XX0wTx0LBeDsqJm W8dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rOsJ9Zrz7rA4F/2ineOAizsi6mknMU/UXeuWBA/JKfA=; b=CeHJL9vTXsXXV1QhjP70qgioeUtVhAY1nYsQhtS1kEzXc0olLN5QZ0eAvobTB/mBV6 Nqyq08BkpwShTdG44CbZ5hW1TIgtN30JTeY/J79ksaRNMRinfXeo4NOikGeZtfFJcC4u w61g0b40xb2pqk381gJFbpNxJLY5tQ/FvvKxL4mdjCedoMr0iMtBTGJb65uEl/yxGXJ3 OLHNU7RxgSk02Cx1HhvQHtJab6+LMU4AlI10km25M/eAq/7vfn7n0B7JnMq3SGtXmaiI dtoe2fyL8WQMarj1RfiKqEt4liKLIBxIObHLS8VwhcE0X2PDeMcWqiRcPYrBhkaqJ/zL H5ZQ== X-Gm-Message-State: AOAM532/sChByqQxkojYM3B+MTHLua6uJZHafDoNyJrpl5rX/ngJaTin CsQxT4+Rgk4HSOVwnO+6tT3T7w== X-Google-Smtp-Source: ABdhPJy2J8mmkdiJxvqH8dGikN58L5gi+Ssd9S6yZ79H1xJDZryQTFJORRerTTeD7nXWU6jstgzEkQ== X-Received: by 2002:a17:907:6da5:b0:6f3:c4b1:378b with SMTP id sb37-20020a1709076da500b006f3c4b1378bmr15574510ejc.307.1651583099425; Tue, 03 May 2022 06:04:59 -0700 (PDT) Received: from prec5560.. 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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id y13-20020aa7cccd000000b0042617ba639asm7868782edt.36.2022.05.03.06.04.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 May 2022 06:04:58 -0700 (PDT) From: Robert Foss To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, jonathan@marek.ca, tdas@codeaurora.org, anischal@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov Cc: Robert Foss , Dmitry Baryshkov Subject: [PATCH v2 5/8] dt-bindings: clock: Add Qcom SM8350 GPUCC bindings Date: Tue, 3 May 2022 15:04:45 +0200 Message-Id: <20220503130448.520470-5-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220503130448.520470-1-robert.foss@linaro.org> References: <20220503130448.520470-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM8350 SoCs. Signed-off-by: Robert Foss Reviewed-by: Dmitry Baryshkov --- .../devicetree/bindings/clock/qcom,gpucc.yaml | 2 + include/dt-bindings/clock/qcom,gpucc-sm8350.h | 52 +++++++++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8350.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml index 9ebcb1943b0a..4090cc7ea2ae 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -20,6 +20,7 @@ description: | dt-bindings/clock/qcom,gpucc-sm6350.h dt-bindings/clock/qcom,gpucc-sm8150.h dt-bindings/clock/qcom,gpucc-sm8250.h + dt-bindings/clock/qcom,gpucc-sm8350.h properties: compatible: @@ -31,6 +32,7 @@ properties: - qcom,sm6350-gpucc - qcom,sm8150-gpucc - qcom,sm8250-gpucc + - qcom,sm8350-gpucc clocks: items: diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8350.h b/include/dt-bindings/clock/qcom,gpucc-sm8350.h new file mode 100644 index 000000000000..d2294e0d527e --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-sm8350.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_APB_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CX_QDSS_AT_CLK 5 +#define GPU_CC_CX_QDSS_TRIG_CLK 6 +#define GPU_CC_CX_QDSS_TSCTR_CLK 7 +#define GPU_CC_CX_SNOC_DVM_CLK 8 +#define GPU_CC_CXO_AON_CLK 9 +#define GPU_CC_CXO_CLK 10 +#define GPU_CC_FREQ_MEASURE_CLK 11 +#define GPU_CC_GMU_CLK_SRC 12 +#define GPU_CC_GX_GMU_CLK 13 +#define GPU_CC_GX_QDSS_TSCTR_CLK 14 +#define GPU_CC_GX_VSENSE_CLK 15 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 17 +#define GPU_CC_HUB_AON_CLK 18 +#define GPU_CC_HUB_CLK_SRC 19 +#define GPU_CC_HUB_CX_INT_CLK 20 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 21 +#define GPU_CC_MND1X_0_GFX3D_CLK 22 +#define GPU_CC_MND1X_1_GFX3D_CLK 23 +#define GPU_CC_PLL0 24 +#define GPU_CC_PLL1 25 +#define GPU_CC_SLEEP_CLK 26 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CB_BCR 1 +#define GPUCC_GPU_CC_CX_BCR 2 +#define GPUCC_GPU_CC_FAST_HUB_BCR 3 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 +#define GPUCC_GPU_CC_GMU_BCR 5 +#define GPUCC_GPU_CC_GX_BCR 6 +#define GPUCC_GPU_CC_XO_BCR 7 + +/* GPU_CC GDSCRs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif From patchwork Tue May 3 13:04:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 569076 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18FABC4332F for ; Tue, 3 May 2022 13:05:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235271AbiECNJJ (ORCPT ); Tue, 3 May 2022 09:09:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49328 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235871AbiECNIm (ORCPT ); Tue, 3 May 2022 09:08:42 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 28E9138DBF for ; Tue, 3 May 2022 06:05:05 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id y21so19794432edo.2 for ; Tue, 03 May 2022 06:05:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=K0SBCr7UtqnGTe/v3toP46qKZcKN+CT+jT8gh91QnOI=; b=FpFzDemp5JAOfv7feq0gNrbwAphBwtF86TL1CKRNuwxEeRgcVfl/mFHV2no7999C4e aZWaXxGCYMbf7yRcOt/v+EhsQz93NVJWmaSykBFpZYTC9xwKmQhuKY/xyuTF1yV8l+dq EsoU6dx8qc6MJZKHi/Jxc8SUT8v3S5Ot3QUwfYoqHzr8Vcu3E8DjCIM2IWrTsep+VHRn F1uU1Y7/7iDM4Twmh4xraXgEpz0QdSbEsj7MBHFcCEOR9qZSGs+zu8svkopyH/y/s5IE 8c8AXCpn3Uowesjm8Nfn18S6SX2yG9KYWiBsXfyHyI6JRPQparEvbl0VtwJpokWHsSii 4HKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=K0SBCr7UtqnGTe/v3toP46qKZcKN+CT+jT8gh91QnOI=; b=ALbx72VFt94A4WbpXRIA7wy2i8uNsMMqX8VgF8SphJni6p9N+/b5ZeQbF0ntQLIay5 ypPgFsHtYK67UPVA9HZTSDuqtm5lZzuvygSxHFIiHK9E4DjAsUBQMh84xjHHgc6Pc1Y8 bvquhGo3j7PwzEYZJnY/sda+O93Amj9N7i3647zb0MadcDx6TI4v17OFA6RYgvkpBCwx 3Mby4/+JzvVz3IE7Tul1P8WbZIaJ1jo9/QonRtx7ThY3EeNbFEHyQFIKm8fzCVRN7xZ5 3/hf902lxSUiZTfEwga50uRqVh7199cjkTKxFuEZP73hk2mtKgehmtnvG2OmdmloswBT DbLQ== X-Gm-Message-State: AOAM530biPmUT+y8WRHozZgJcadXMCZL9RXmse4Lo8JLl0bvDvKkPae8 KHSRihjRChiLUOQWQB6uQ6Munw== X-Google-Smtp-Source: ABdhPJx0ChXIobPkGkhWdTTODEQzyFRu77Glvj8BqeOTzzb17aBc4FJAO3qzbzS6sVFzqDCv9ox9fQ== X-Received: by 2002:a05:6402:4251:b0:427:bbac:e1ee with SMTP id g17-20020a056402425100b00427bbace1eemr11658858edb.374.1651583103417; Tue, 03 May 2022 06:05:03 -0700 (PDT) Received: from prec5560.. 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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id y13-20020aa7cccd000000b0042617ba639asm7868782edt.36.2022.05.03.06.05.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 May 2022 06:05:02 -0700 (PDT) From: Robert Foss To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, jonathan@marek.ca, tdas@codeaurora.org, anischal@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov Cc: Rob Herring Subject: [PATCH v2 7/8] dt-bindings: clock: Add Qcom SM8350 DISPCC bindings Date: Tue, 3 May 2022 15:04:47 +0200 Message-Id: <20220503130448.520470-7-robert.foss@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220503130448.520470-1-robert.foss@linaro.org> References: <20220503130448.520470-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Jonathan Marek Add sm8350 DISPCC bindings, which are simply a symlink to the sm8250 bindings. Update the documentation with the new compatible. Signed-off-by: Jonathan Marek Reviewed-by: Rob Herring Reviewed-by: Dmitry Baryshkov --- .../devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml | 6 ++++-- include/dt-bindings/clock/qcom,dispcc-sm8350.h | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) create mode 120000 include/dt-bindings/clock/qcom,dispcc-sm8350.h diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index 31497677e8de..7a8d375e055e 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -4,18 +4,19 @@ $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250 +title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350 maintainers: - Jonathan Marek description: | Qualcomm display clock control module which supports the clocks, resets and - power domains on SM8150 and SM8250. + power domains on SM8150/SM8250/SM8350. See also: dt-bindings/clock/qcom,dispcc-sm8150.h dt-bindings/clock/qcom,dispcc-sm8250.h + dt-bindings/clock/qcom,dispcc-sm8350.h properties: compatible: @@ -23,6 +24,7 @@ properties: - qcom,sc8180x-dispcc - qcom,sm8150-dispcc - qcom,sm8250-dispcc + - qcom,sm8350-dispcc clocks: items: diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8350.h b/include/dt-bindings/clock/qcom,dispcc-sm8350.h new file mode 120000 index 000000000000..0312b4544acb --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sm8350.h @@ -0,0 +1 @@ +qcom,dispcc-sm8250.h \ No newline at end of file