From patchwork Fri Apr 29 10:40:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 568411 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D501C433F5 for ; Fri, 29 Apr 2022 10:41:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357549AbiD2Kou (ORCPT ); Fri, 29 Apr 2022 06:44:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241432AbiD2Kot (ORCPT ); Fri, 29 Apr 2022 06:44:49 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 819DE6F9EA; Fri, 29 Apr 2022 03:41:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1651228890; x=1682764890; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZuFa87SywQwTRkYIIlhDNx8UApQkwnBlhQXVx2P4TEQ=; b=2lbNFDe+jO7z4dYLKk6hKGGWCoyngf54AMZcpZNS28zS3vrxlZW4XMfm v9OIquAjEIBegMC4+wzu2sLIvo77+xhtszfw9aXtoJiqAXSaE4nA/cmkX qAiKWvxS6El3dhR4EWFh+9PQzvmqa79vq0YE01oqnZ55WAAfIB5xusjyK W9quRN+4knhj9KgcMXi42Gl1JFdzSTk1w/eso2rkoOUOOWWhKN5T3Eu1C HLyp0JGnXQZk/7NSvtZAbFtj7hBJY+f7RXDEiZ9yOK/09FqjucDtZpvWn deHJONe//5o2ILdkZDsOIxAIrCdDU/9LrLi3X/P9dMeZJ01+bEM1Y43FF g==; X-IronPort-AV: E=Sophos;i="5.91,298,1647327600"; d="scan'208";a="94031887" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Apr 2022 03:41:29 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 29 Apr 2022 03:41:29 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 29 Apr 2022 03:41:26 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Daire McNamara , Cyril Jean , , , , "Arnd Bergmann" Subject: [PATCH v1 1/8] riscv: dts: microchip: remove icicle memory clocks Date: Fri, 29 Apr 2022 11:40:34 +0100 Message-ID: <20220429104040.197161-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.2 In-Reply-To: <20220429104040.197161-1-conor.dooley@microchip.com> References: <20220429104040.197161-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The clock properties in the icicle kit's memory entries cause dtbs_check errors: arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dtb: /: memory@80000000: 'clocks' does not match any of the regexes: 'pinctrl-[0-9]+' Get rid of the clocks to avoid the errors. Reported-by: Palmer Dabbelt Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board") Fixes: 5b28df37d311 ("riscv: dts: microchip: update peripherals in icicle kit device tree") Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts index 3392153dd0f1..c71d6aa6137a 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -32,14 +32,12 @@ cpus { ddrc_cache_lo: memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x2e000000>; - clocks = <&clkcfg CLK_DDRC>; status = "okay"; }; ddrc_cache_hi: memory@1000000000 { device_type = "memory"; reg = <0x10 0x0 0x0 0x40000000>; - clocks = <&clkcfg CLK_DDRC>; status = "okay"; }; }; From patchwork Fri Apr 29 10:40:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 568410 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82500C4332F for ; Fri, 29 Apr 2022 10:41:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241432AbiD2Koz (ORCPT ); Fri, 29 Apr 2022 06:44:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56198 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357559AbiD2Koy (ORCPT ); Fri, 29 Apr 2022 06:44:54 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 264876F9EA; Fri, 29 Apr 2022 03:41:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1651228896; x=1682764896; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aKR3tJNHcnSUKAVT7Q3BQcuQSowY0bVH8z3w3WzyYKU=; b=EAc05mOEb+F8GbKP9HAdheio/KqOSyhvps97bz3UVvDcEyOKzpp5WVJL PmBc18E5AJSGa+KP/JczxHLR9IoOAP6gSTn7KR6mvrdIrifwKg7R3Uk/2 ze1JgoIwl2fHnUHFRgOFwA3HbwBkzKB39PpxrXjphARUyyIJCsu3nycpF XL2Ga6uNCkGOzzSmmSA7mXtxbKxedhbNuefmUGTYit4YXNqm3hqXQ9QDW xo65Yxxcz/2Ol0ALcigdbUhaMMT4YqzzCBvvjDh6gr7+B4TYT0iDeAykx 0AK0+u1XNXcj6KXwBysm4ByqknDIKsRPXIxPiGXa8VQ1WvweCPldQp7w2 g==; X-IronPort-AV: E=Sophos;i="5.91,298,1647327600"; d="scan'208";a="154297285" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Apr 2022 03:41:35 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 29 Apr 2022 03:41:35 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 29 Apr 2022 03:41:32 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Daire McNamara , Cyril Jean , , , , "Arnd Bergmann" Subject: [PATCH v1 3/8] riscv: dts: microchip: remove soc vendor from filenames Date: Fri, 29 Apr 2022 11:40:36 +0100 Message-ID: <20220429104040.197161-4-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.2 In-Reply-To: <20220429104040.197161-1-conor.dooley@microchip.com> References: <20220429104040.197161-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Having the SoC vendor both as the directory and in the filename adds little. Remove microchip from the filenames so that the files will resemble the other directories in riscv (and arm64). The new names follow a soc-board.dts & soc{,-fabric}.dtsi pattern. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/Makefile | 2 +- .../microchip/{microchip-mpfs-fabric.dtsi => mpfs-fabric.dtsi} | 0 .../{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} | 2 +- .../riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} | 2 +- 4 files changed, 3 insertions(+), 3 deletions(-) rename arch/riscv/boot/dts/microchip/{microchip-mpfs-fabric.dtsi => mpfs-fabric.dtsi} (100%) rename arch/riscv/boot/dts/microchip/{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} (98%) rename arch/riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} (99%) diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile index 855c1502d912..af3a5059b350 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi similarity index 100% rename from arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi rename to arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts similarity index 98% rename from arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts rename to arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts index c71d6aa6137a..84b0015dfd47 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -3,7 +3,7 @@ /dts-v1/; -#include "microchip-mpfs.dtsi" +#include "mpfs.dtsi" /* Clock frequency (in Hz) of the rtcclk */ #define RTCCLK_FREQ 1000000 diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi similarity index 99% rename from arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi rename to arch/riscv/boot/dts/microchip/mpfs.dtsi index bf21a2edd180..cc3386068c2d 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -3,7 +3,7 @@ /dts-v1/; #include "dt-bindings/clock/microchip,mpfs-clock.h" -#include "microchip-mpfs-fabric.dtsi" +#include "mpfs-fabric.dtsi" / { #address-cells = <2>; From patchwork Fri Apr 29 10:40:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 568409 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D174C433F5 for ; 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X-IronPort-AV: E=Sophos;i="5.91,298,1647327600"; d="scan'208";a="171406907" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Apr 2022 03:41:43 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 29 Apr 2022 03:41:43 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 29 Apr 2022 03:41:41 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Daire McNamara , Cyril Jean , , , , "Arnd Bergmann" Subject: [PATCH v1 6/8] dt-bindings: vendor-prefixes: add Sundance DSP Date: Fri, 29 Apr 2022 11:40:39 +0100 Message-ID: <20220429104040.197161-7-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.2 In-Reply-To: <20220429104040.197161-1-conor.dooley@microchip.com> References: <20220429104040.197161-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Sundance DSP Inc. (https://www.sundancedsp.com/) is a supplier of high-performance DSP and FPGA processor boards and I/O modules. Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 01430973ecec..1d47a38c2a2e 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1197,6 +1197,8 @@ patternProperties: description: Summit microelectronics "^sunchip,.*": description: Shenzhen Sunchip Technology Co., Ltd + "^sundance,.*": + description: Sundance DSP Inc. "^sunplus,.*": description: Sunplus Technology Co., Ltd. "^SUNW,.*": From patchwork Fri Apr 29 10:40:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 568408 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF515C433EF for ; Fri, 29 Apr 2022 10:41:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1357667AbiD2KpL (ORCPT ); Fri, 29 Apr 2022 06:45:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1357675AbiD2KpK (ORCPT ); Fri, 29 Apr 2022 06:45:10 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 985FE6F9EA; Fri, 29 Apr 2022 03:41:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1651228912; x=1682764912; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Cv32FDml94cqqpdihITDsM5k1vOOBbEYHDCibMtfobU=; b=DiuQ5Wdf9Lq950ZuRRwkWzrIJ85i44hr4mkMJCgiijTWan7Gm1tXr77E d+GI55I0+z/n0gpvUb3/b0Lk8OMLVTL1Zu5LvpLI9X8wCj5NciIIttT7A jSLS2wxo/X8FmW6q1OKEHYKV4Q32lCoP/ZyvhZtYPdarLMWyjztrLJWxk LMF21tEq8M6HHM+FVb0dUt1Qc+a4M+ZHZR7PO7A+a8RQwlrSjRwsWu6xH aNsR8N0Xlrt8raUI5ZAhRbMzZ+rnLH42f59pl8upJ2i4EmzWI7YwPO9Co Mvr3mH/fV0I0R5SvpZbzg2T6Jk+nhf/D2A//YDMGzE7PTYIrS2/2iZg9G Q==; X-IronPort-AV: E=Sophos;i="5.91,298,1647327600"; d="scan'208";a="154297321" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Apr 2022 03:41:50 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 29 Apr 2022 03:41:49 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 29 Apr 2022 03:41:47 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Palmer Dabbelt CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Daire McNamara , Cyril Jean , , , , "Arnd Bergmann" Subject: [PATCH v1 8/8] riscv: dts: microchip: add the sundance polarberry Date: Fri, 29 Apr 2022 11:40:41 +0100 Message-ID: <20220429104040.197161-9-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.2 In-Reply-To: <20220429104040.197161-1-conor.dooley@microchip.com> References: <20220429104040.197161-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a minimal device tree for the PolarFire SoC based Sundance PolarBerry. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/Makefile | 1 + .../dts/microchip/mpfs-polarberry-fabric.dtsi | 16 ++++ .../boot/dts/microchip/mpfs-polarberry.dts | 95 +++++++++++++++++++ 3 files changed, 112 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile index af3a5059b350..39aae7b04f1c 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi new file mode 100644 index 000000000000..49380c428ec9 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2022 Microchip Technology Inc */ + +/ { + fabric_clk3: fabric-clk3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <62500000>; + }; + + fabric_clk1: fabric-clk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts new file mode 100644 index 000000000000..8c635f3358a5 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2022 Microchip Technology Inc */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-polarberry-fabric.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define MTIMER_FREQ 1000000 + +/ { + model = "Sundance PolarBerry"; + compatible = "sundance,polarberry", "microchip,mpfs"; + + aliases { + serial0 = &mmuart0; + ethernet0 = &mac0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + timebase-frequency = ; + }; + + ddrc_cache_lo: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x2e000000>; + status = "okay"; + }; + + ddrc_cache_hi: memory@1000000000 { + device_type = "memory"; + reg = <0x10 0x00000000 0x0 0xC0000000>; + status = "okay"; + }; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&mmuart0 { + status = "okay"; +}; + +&mmc { + status = "okay"; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + card-detect-delay = <200>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +}; + +&mac1 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&phy1>; + phy1: ethernet-phy@5 { + reg = <5>; + ti,fifo-depth = <0x01>; + }; + phy0: ethernet-phy@4 { + reg = <4>; + ti,fifo-depth = <0x01>; + }; +}; + +&mac0 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&phy0>; +}; + +&rtc { + status = "okay"; +}; + +&mbox { + status = "okay"; +}; + +&syscontroller { + status = "okay"; +};