From patchwork Fri Apr 29 10:45:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 568405 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13AAAC4167E for ; Fri, 29 Apr 2022 10:49:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358047AbiD2Kwa (ORCPT ); Fri, 29 Apr 2022 06:52:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47580 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358073AbiD2KvL (ORCPT ); Fri, 29 Apr 2022 06:51:11 -0400 Received: from relay11.mail.gandi.net (relay11.mail.gandi.net [217.70.178.231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0A6DC8BEB; Fri, 29 Apr 2022 03:46:09 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 42C6B10000F; Fri, 29 Apr 2022 10:46:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1651229168; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8ahdxlylHUe3mADgzeD98ByHKZe3nsmtka5ti0feGmk=; b=A8ymcAf4cZE365VPUPzKtLgpGVYVP2s1wHBf1xHUQYmdXcBnGREKeNdd5/ynePp2rUJc8b kkIDxUDSBdcR6cGuQEZ89CakNYkJkMG4CPVP0k2Jw/LtwHiBTsJixpb3n6qOpgJOfcWod7 ejs5tqS1hiN7s+WyNDTOdYV8BIzWm3vw48iNeBc/5x9Kmuof+TnO9OE3N2d3HRLqQ//w84 GWbIJKvpzFsSTmnmVlmTOyjgkbu2oUpw4hGj4JY/x6NxEk3OUNFvW0hRnsrwRI4hyYah3f INzueq2Wly314RRFgzZ0IzvNtZSF0JCSyh04MaBW7mYhmkYBMXwt6W/z1w1aHA== From: Miquel Raynal To: Alessandro Zummo , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm Cc: Miquel Raynal , linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Gareth Williams , Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Thomas Petazzoni , Herve Codina , Clement Leger , Krzysztof Kozlowski Subject: [PATCH v3 1/6] dt-bindings: rtc: rzn1: Describe the RZN1 RTC Date: Fri, 29 Apr 2022 12:45:57 +0200 Message-Id: <20220429104602.368055-2-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220429104602.368055-1-miquel.raynal@bootlin.com> References: <20220429104602.368055-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add new binding file for this RTC. Signed-off-by: Miquel Raynal Reviewed-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven --- .../bindings/rtc/renesas,rzn1-rtc.yaml | 70 +++++++++++++++++++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml diff --git a/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml b/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml new file mode 100644 index 000000000000..2d4741f51663 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/renesas,rzn1-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 SoCs Real-Time Clock DT bindings + +maintainers: + - Miquel Raynal + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + items: + - enum: + - renesas,r9a06g032-rtc + - const: renesas,rzn1-rtc + + reg: + maxItems: 1 + + interrupts: + minItems: 3 + maxItems: 3 + + interrupt-names: + items: + - const: alarm + - const: timer + - const: pps + + clocks: + maxItems: 1 + + clock-names: + const: hclk + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include + #include + rtc@40006000 { + compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc"; + reg = <0x40006000 0x1000>; + interrupts = , + , + ; + interrupt-names = "alarm", "timer", "pps"; + clocks = <&sysctrl R9A06G032_HCLK_RTC>; + clock-names = "hclk"; + power-domains = <&sysctrl>; + start-year = <2000>; + }; From patchwork Fri Apr 29 10:45:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 568407 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A603C433FE for ; Fri, 29 Apr 2022 10:48:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1358330AbiD2KvW (ORCPT ); Fri, 29 Apr 2022 06:51:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358277AbiD2KvN (ORCPT ); Fri, 29 Apr 2022 06:51:13 -0400 Received: from relay11.mail.gandi.net (relay11.mail.gandi.net [217.70.178.231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E491CD667; Fri, 29 Apr 2022 03:46:15 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id C826F100005; Fri, 29 Apr 2022 10:46:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1651229173; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1slGuaD21NO0IdLHU0muSHaPeGaoSzr+MeyyBTYPbnk=; b=mkDm7qKfiaFRxLGN7JuMaePxU6nOTi4ISBFoocbA1w48SQEiGnO7spjUqplbkWGo0oJGk+ /fO9LS1rpHbyuPS8jFqn4uLIQkGKTVyrZ6ObSKyJouAynNSvqnSAPAnO1riydBvpDngw7K ZPNlE80GTmI+j7CZi2MeCFms8esF52IpAytYS0ks4kFX90F/Xz7qp6xArYfG36vodwOzSc cOtm22mnsXBdLBro9CYM63s9MMGMYIaSt7th6J+J3Ia3CFzDcGfqfAIVtrxZ1H63wnfNfS 4d5jife46B5zmT4T4/YjgypZ3oXasUJbBYuiuBm3zpMlX/Tk4+Y66l7MHaTu0w== From: Miquel Raynal To: Alessandro Zummo , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm Cc: Miquel Raynal , linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Gareth Williams , Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Thomas Petazzoni , Herve Codina , Clement Leger Subject: [PATCH v3 3/6] rtc: rzn1: Add alarm support Date: Fri, 29 Apr 2022 12:45:59 +0200 Message-Id: <20220429104602.368055-4-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220429104602.368055-1-miquel.raynal@bootlin.com> References: <20220429104602.368055-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The RZN1 RTC can trigger an interrupt when reaching a particular date up to 7 days ahead. Bring support for this alarm. One drawback though, the granularity is about a minute. Signed-off-by: Miquel Raynal --- drivers/rtc/rtc-rzn1.c | 106 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 105 insertions(+), 1 deletion(-) diff --git a/drivers/rtc/rtc-rzn1.c b/drivers/rtc/rtc-rzn1.c index 19f323f62f20..5efbc1aa9040 100644 --- a/drivers/rtc/rtc-rzn1.c +++ b/drivers/rtc/rtc-rzn1.c @@ -159,14 +159,107 @@ static int rzn1_rtc_set_time(struct device *dev, struct rtc_time *tm) return 0; } +static irqreturn_t rzn1_rtc_alarm_irq(int irq, void *dev_id) +{ + struct rzn1_rtc *rtc = dev_id; + + rtc_update_irq(rtc->rtcdev, 1, RTC_AF | RTC_IRQF); + + return IRQ_HANDLED; +} + +static int rzn1_rtc_alarm_irq_enable(struct device *dev, unsigned int enable) +{ + struct rzn1_rtc *rtc = dev_get_drvdata(dev); + u32 ctl1 = readl(rtc->base + RZN1_RTC_CTL1); + + if (enable) + ctl1 |= RZN1_RTC_CTL1_ALME; + else + ctl1 &= ~RZN1_RTC_CTL1_ALME; + + writel(ctl1, rtc->base + RZN1_RTC_CTL1); + + return 0; +} + +static int rzn1_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct rzn1_rtc *rtc = dev_get_drvdata(dev); + struct rtc_time *tm = &alrm->time; + unsigned int min, hour, wday, delta_days; + time64_t alarm; + u32 ctl1; + int ret; + + ret = rzn1_rtc_read_time(dev, tm); + if (ret) + return ret; + + min = readl(rtc->base + RZN1_RTC_ALM); + hour = readl(rtc->base + RZN1_RTC_ALH); + wday = readl(rtc->base + RZN1_RTC_ALW); + + tm->tm_sec = 0; + tm->tm_min = bcd2bin(min); + tm->tm_hour = bcd2bin(hour); + delta_days = ((fls(wday) - 1) - tm->tm_wday + 7) % 7; + tm->tm_wday = fls(wday) - 1; + + if (delta_days) { + alarm = rtc_tm_to_time64(tm) + (delta_days * 86400); + rtc_time64_to_tm(alarm, tm); + } + + ctl1 = readl(rtc->base + RZN1_RTC_CTL1); + alrm->enabled = !!(ctl1 & RZN1_RTC_CTL1_ALME); + + return 0; +} + +static int rzn1_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct rzn1_rtc *rtc = dev_get_drvdata(dev); + struct rtc_time *tm = &alrm->time, tm_now; + unsigned long alarm, farest; + unsigned int days_ahead, wday; + int ret; + + ret = rzn1_rtc_read_time(dev, &tm_now); + if (ret) + return ret; + + /* We cannot set alarms more than one week ahead */ + farest = rtc_tm_to_time64(&tm_now) + (7 * 86400); + alarm = rtc_tm_to_time64(tm); + if (time_after(alarm, farest)) + return -ERANGE; + + /* Convert alarm day into week day */ + days_ahead = tm->tm_mday - tm_now.tm_mday; + wday = (tm_now.tm_wday + days_ahead) % 7; + + writel(bin2bcd(tm->tm_min), rtc->base + RZN1_RTC_ALM); + writel(bin2bcd(tm->tm_hour), rtc->base + RZN1_RTC_ALH); + writel(BIT(wday), rtc->base + RZN1_RTC_ALW); + + rzn1_rtc_alarm_irq_enable(dev, alrm->enabled); + + return 0; +} + static const struct rtc_class_ops rzn1_rtc_ops = { .read_time = rzn1_rtc_read_time, .set_time = rzn1_rtc_set_time, + .read_alarm = rzn1_rtc_read_alarm, + .set_alarm = rzn1_rtc_set_alarm, + .alarm_irq_enable = rzn1_rtc_alarm_irq_enable, }; static int rzn1_rtc_probe(struct platform_device *pdev) { struct rzn1_rtc *rtc; + int alarm_irq; int ret; rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); @@ -179,6 +272,10 @@ static int rzn1_rtc_probe(struct platform_device *pdev) if (IS_ERR(rtc->base)) return dev_err_probe(&pdev->dev, PTR_ERR(rtc->base), "Missing reg\n"); + alarm_irq = platform_get_irq(pdev, 0); + if (alarm_irq < 0) + return dev_err_probe(&pdev->dev, alarm_irq, "Missing timer IRQ\n"); + rtc->rtcdev = devm_rtc_allocate_device(&pdev->dev); if (IS_ERR(rtc->rtcdev)) return PTR_ERR(rtc); @@ -186,7 +283,7 @@ static int rzn1_rtc_probe(struct platform_device *pdev) rtc->rtcdev->range_min = RTC_TIMESTAMP_BEGIN_2000; rtc->rtcdev->range_max = RTC_TIMESTAMP_END_2099; rtc->rtcdev->ops = &rzn1_rtc_ops; - clear_bit(RTC_FEATURE_ALARM, rtc->rtcdev->features); + set_bit(RTC_FEATURE_ALARM_RES_MINUTE, rtc->rtcdev->features); clear_bit(RTC_FEATURE_UPDATE_INTERRUPT, rtc->rtcdev->features); pm_runtime_enable(&pdev->dev); @@ -202,6 +299,13 @@ static int rzn1_rtc_probe(struct platform_device *pdev) /* Disable all interrupts */ writel(0, rtc->base + RZN1_RTC_CTL1); + ret = devm_request_irq(&pdev->dev, alarm_irq, rzn1_rtc_alarm_irq, 0, + dev_name(&pdev->dev), rtc); + if (ret) { + dev_err(&pdev->dev, "RTC timer interrupt not available\n"); + goto dis_runtime_pm; + } + ret = devm_rtc_register_device(rtc->rtcdev); if (ret) goto dis_runtime_pm; From patchwork Fri Apr 29 10:46:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 568406 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2728C43217 for ; Fri, 29 Apr 2022 10:49:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350282AbiD2Kw3 (ORCPT ); Fri, 29 Apr 2022 06:52:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46116 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1358292AbiD2KvO (ORCPT ); Fri, 29 Apr 2022 06:51:14 -0400 Received: from relay11.mail.gandi.net (relay11.mail.gandi.net [217.70.178.231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1135CE101; Fri, 29 Apr 2022 03:46:17 -0700 (PDT) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 02ECA10000C; Fri, 29 Apr 2022 10:46:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1651229176; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=n7UTh06UyThE/1bsw2IRPyyoiktklBD9/M4mSgyJGow=; b=Yl0m/HvfLqBks9JFsJYgPe80AaJvlolH4Zq0oC/qmV3nrHeHvlSc85+GeeGq3GDGO8C/D6 3bR2QQwVQsuNmTfjQeEnXJ3utg1LrNWW6OQKzD9BXDh0SCWzWrRHp2tsLDJx09ayOsOskI KLgGH5jaaD1ptWiuDxjdX86kQtAufXMSrq1O03xhldtLYihFWkgtiEXmHNsUt9sVN1NdZR gzsCpJdcti4CmbaRLHhYzs85s5AnQo7cvMkIZjHXvLvQuPihD9YaZBtdGMUz4xOf9roBiU yZHUUTnmV7qSQMopfIOyksdy+yYRUBaogXQPuNFWxwtbzhvdttMdQnFJLZ2KUw== From: Miquel Raynal To: Alessandro Zummo , Alexandre Belloni , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm Cc: Miquel Raynal , linux-rtc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Gareth Williams , Milan Stevanovic , Jimmy Lalande , Pascal Eberhard , Thomas Petazzoni , Herve Codina , Clement Leger Subject: [PATCH v3 4/6] rtc: rzn1: Add oscillator offset support Date: Fri, 29 Apr 2022 12:46:00 +0200 Message-Id: <20220429104602.368055-5-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220429104602.368055-1-miquel.raynal@bootlin.com> References: <20220429104602.368055-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The RZN1 RTC can compensate the imprecision of the oscillator up to approximately 190ppm. Seconds can last slightly shorter or longer depending on the configuration. Below ~65ppm of correction, we can change the time spent in a second every minute, which is the most accurate compensation that the RTC can offer. Above, the compensation will be active every 20s. Signed-off-by: Miquel Raynal --- drivers/rtc/rtc-rzn1.c | 73 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/drivers/rtc/rtc-rzn1.c b/drivers/rtc/rtc-rzn1.c index 5efbc1aa9040..6d05d0454a98 100644 --- a/drivers/rtc/rtc-rzn1.c +++ b/drivers/rtc/rtc-rzn1.c @@ -248,12 +248,85 @@ static int rzn1_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) return 0; } +static int rzn1_rtc_read_offset(struct device *dev, long *offset) +{ + struct rzn1_rtc *rtc = dev_get_drvdata(dev); + unsigned int ppb_per_step; + bool subtract; + u32 val; + + val = readl(rtc->base + RZN1_RTC_SUBU); + ppb_per_step = val & RZN1_RTC_SUBU_DEV ? 1017 : 3051; + subtract = val & RZN1_RTC_SUBU_DECR; + val &= 0x3F; + + if (!val) + *offset = 0; + else if (subtract) + *offset = -(((~val) & 0x3F) + 1) * ppb_per_step; + else + *offset = (val - 1) * ppb_per_step; + + return 0; +} + +static int rzn1_rtc_set_offset(struct device *dev, long offset) +{ + struct rzn1_rtc *rtc = dev_get_drvdata(dev); + unsigned int steps, ppb_per_step; + int stepsh, stepsl; + u32 val; + int ret; + + /* + * Check which resolution mode (every 20 or 60s) can be used. + * Between 2 and 124 clock pulses can be added or substracted. + * + * In 20s mode, the minimum resolution is 2 / (32768 * 20) which is + * close to 3051 ppb. In 60s mode, the resolution is closer to 1017. + */ + stepsh = DIV_ROUND_CLOSEST(offset, 1017); + stepsl = DIV_ROUND_CLOSEST(offset, 3051); + + if (stepsh >= -0x3E && stepsh <= 0x3E) { + ppb_per_step = 1017; + steps = stepsh; + val |= RZN1_RTC_SUBU_DEV; + } else if (stepsl >= -0x3E && stepsl <= 0x3E) { + ppb_per_step = 3051; + steps = stepsl; + } else { + return -ERANGE; + } + + if (!steps) + return 0; + + if (steps > 0) { + val |= steps + 1; + } else { + val |= RZN1_RTC_SUBU_DECR; + val |= (~(-steps - 1)) & 0x3F; + } + + ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL2, val, + !(val & RZN1_RTC_CTL2_WUST), 100, 2000000); + if (ret) + return ret; + + writel(val, rtc->base + RZN1_RTC_SUBU); + + return 0; +} + static const struct rtc_class_ops rzn1_rtc_ops = { .read_time = rzn1_rtc_read_time, .set_time = rzn1_rtc_set_time, .read_alarm = rzn1_rtc_read_alarm, .set_alarm = rzn1_rtc_set_alarm, .alarm_irq_enable = rzn1_rtc_alarm_irq_enable, + .read_offset = rzn1_rtc_read_offset, + .set_offset = rzn1_rtc_set_offset, }; static int rzn1_rtc_probe(struct platform_device *pdev)