From patchwork Fri Apr 29 15:12:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 568367 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC9C3C433F5 for ; Fri, 29 Apr 2022 15:13:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378154AbiD2PQe (ORCPT ); Fri, 29 Apr 2022 11:16:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378129AbiD2PQa (ORCPT ); Fri, 29 Apr 2022 11:16:30 -0400 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D65CD4C46 for ; Fri, 29 Apr 2022 08:13:11 -0700 (PDT) Received: by mail-ed1-x52e.google.com with SMTP id a1so9446961edt.3 for ; Fri, 29 Apr 2022 08:13:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=7bnc7xO3az7rccsOJO8obe46CTWWIlyZBBYGgk6otdQ=; b=A8J6mu0UHsKQyge26bU/j8tsK4sQ4qhNOGGgwNNeg3b/b8m++6m1tLlgJHDKHicALb p4nJZXY1d4v8f8AuUlfyGcZxjRymhNtIuoyC+4MpWPMCeyK4H8UD5UatT/Q4SgmPrUsi 6kYTeGSgdbvEDo06m2qTqZHCt9eeOrJpSlHfV3NC8qsgJZqbxxbmv/eJpW86odZ3yA6O zJITUUwmsUV25gT7CW4PExxRMG9glIShIp35heNe4ZM3BygT3v49RskkaPDLJLYgzRYI 96idROj+aMaW+VZ0QS1yB0lt0iEfB4lxrJYUOdePrY03LvdkKLTLcoKE0yPiiNCFTuey t+5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=7bnc7xO3az7rccsOJO8obe46CTWWIlyZBBYGgk6otdQ=; b=7FbcXiKqGgJnBGntYluh++9SgshB5BmD5AkoN1feR1hc3CQFskQTWdcxiD2+7exLxH rQ6mQZU1jZcZ4aiJ07sVVBc4em9Z4lAHEXpASVyF2b7j+QDAbt5ySDFuPrhNaskfJRsj 2KvbJzw071wXPy9HFB1v+ExM39JprE9K9E7Cvocs3pHWUK4KEzqGkC8denj7RHBrIjfP M6+/k1b7RglDS2ne8BVFibeNr4EEY64lsWlf+H+P5wZxZt/WjqV2iyRux4k+iDJKtRBr bkaosZfXhFH2OdsjKhgqEiGvoUdsn3Je9sEiBPQ1LyyB346gPGKIsQNiffeluFxTZfjX S2jA== X-Gm-Message-State: AOAM533o0+PYppbaadOCl2vVE65kmQMx5x2NIMZbGa20drQlxJVDz8C4 gfTeEqf6aNNPxFgXD6YzNObd9w== X-Google-Smtp-Source: ABdhPJxpoO0jVgbjIYzu0YiPS8lmBQC+2VUElZk/qV9jT9SDbwXvH0t1Tfb+3k/tEr45cGvg7pSY4w== X-Received: by 2002:a05:6402:155a:b0:425:c0b1:ab07 with SMTP id p26-20020a056402155a00b00425c0b1ab07mr39234921edx.258.1651245189765; Fri, 29 Apr 2022 08:13:09 -0700 (PDT) Received: from prec5560.. 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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id zp15-20020a17090684ef00b006f3ef214e4esm712677ejb.180.2022.04.29.08.13.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 08:13:09 -0700 (PDT) From: Robert Foss To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, jonathan@marek.ca, tdas@codeaurora.org, anischal@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vinod Koul , Steev Klimaszewski Subject: [PATCH v1 1/9] clk: qcom: rcg2: Cache rate changes for parked RCGs Date: Fri, 29 Apr 2022 17:12:39 +0200 Message-Id: <20220429151247.388837-1-robert.foss@linaro.org> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Bjorn Andersson As GDSCs are turned on and off some associated clocks are momentarily enabled for house keeping purposes. Failure to enable these clocks seems to have been silently ignored in the past, but starting in SM8350 this failure will prevent the GDSC to turn on. At least on SM8350 this operation will enable the RCG per the configuration in CFG_REG. This means that the current model where the current configuration is written back to CF_REG immediately after parking the RCG doesn't work. Instead, keep track of the currently requested rate of the clock and upon enabling the clock reapply the configuration per the saved rate. Fixes: 7ef6f11887bd ("clk: qcom: Configure the RCGs to a safe source as needed") Signed-off-by: Bjorn Andersson Reviewed-by: Vinod Koul Tested-by: Steev Klimaszewski --- drivers/clk/qcom/clk-rcg.h | 2 ++ drivers/clk/qcom/clk-rcg2.c | 32 +++++++++++++++++--------------- 2 files changed, 19 insertions(+), 15 deletions(-) diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h index 00cea508d49e..8b41244b8dbf 100644 --- a/drivers/clk/qcom/clk-rcg.h +++ b/drivers/clk/qcom/clk-rcg.h @@ -140,6 +140,7 @@ extern const struct clk_ops clk_dyn_rcg_ops; * @freq_tbl: frequency table * @clkr: regmap clock handle * @cfg_off: defines the cfg register offset from the CMD_RCGR + CFG_REG + * @current_rate: cached rate for parked RCGs */ struct clk_rcg2 { u32 cmd_rcgr; @@ -150,6 +151,7 @@ struct clk_rcg2 { const struct freq_tbl *freq_tbl; struct clk_regmap clkr; u8 cfg_off; + unsigned long current_rate; }; #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index f675fd969c4d..81fd3a2db709 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -167,6 +167,7 @@ clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask; + unsigned long rate; regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); @@ -186,7 +187,11 @@ clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) hid_div = cfg >> CFG_SRC_DIV_SHIFT; hid_div &= mask; - return calc_rate(parent_rate, m, n, mode, hid_div); + rate = calc_rate(parent_rate, m, n, mode, hid_div); + if (!rcg->current_rate) + rcg->current_rate = rate; + + return rate; } static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f, @@ -978,12 +983,14 @@ static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate, if (!f) return -EINVAL; + rcg->current_rate = rate; + /* - * In case clock is disabled, update the CFG, M, N and D registers - * and don't hit the update bit of CMD register. + * In the case that the shared RCG is parked, current_rate will be + * applied as the clock is unparked again, so just return here. */ if (!__clk_is_enabled(hw->clk)) - return __clk_rcg2_configure(rcg, f); + return 0; return clk_rcg2_shared_force_enable_clear(hw, f); } @@ -997,8 +1004,13 @@ static int clk_rcg2_shared_set_rate_and_parent(struct clk_hw *hw, static int clk_rcg2_shared_enable(struct clk_hw *hw) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); + const struct freq_tbl *f = NULL; int ret; + f = qcom_find_freq(rcg->freq_tbl, rcg->current_rate); + if (!f) + return -EINVAL; + /* * Set the update bit because required configuration has already * been written in clk_rcg2_shared_set_rate() @@ -1007,7 +1019,7 @@ static int clk_rcg2_shared_enable(struct clk_hw *hw) if (ret) return ret; - ret = update_config(rcg); + ret = clk_rcg2_configure(rcg, f); if (ret) return ret; @@ -1017,13 +1029,6 @@ static int clk_rcg2_shared_enable(struct clk_hw *hw) static void clk_rcg2_shared_disable(struct clk_hw *hw) { struct clk_rcg2 *rcg = to_clk_rcg2(hw); - u32 cfg; - - /* - * Store current configuration as switching to safe source would clear - * the SRC and DIV of CFG register - */ - regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); /* * Park the RCG at a safe configuration - sourced off of safe source. @@ -1041,9 +1046,6 @@ static void clk_rcg2_shared_disable(struct clk_hw *hw) update_config(rcg); clk_rcg2_clear_force_enable(hw); - - /* Write back the stored configuration corresponding to current rate */ - regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg); } const struct clk_ops clk_rcg2_shared_ops = { From patchwork Fri Apr 29 15:12:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 568366 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2A02C433F5 for ; Fri, 29 Apr 2022 15:13:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231968AbiD2PQh (ORCPT ); Fri, 29 Apr 2022 11:16:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378142AbiD2PQd (ORCPT ); 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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id zp15-20020a17090684ef00b006f3ef214e4esm712677ejb.180.2022.04.29.08.13.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 08:13:12 -0700 (PDT) From: Robert Foss To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, jonathan@marek.ca, tdas@codeaurora.org, anischal@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vinod Koul Subject: [PATCH v1 2/9] clk: Introduce CLK_ASSUME_ENABLED_WHEN_UNUSED Date: Fri, 29 Apr 2022 17:12:40 +0200 Message-Id: <20220429151247.388837-2-robert.foss@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220429151247.388837-1-robert.foss@linaro.org> References: <20220429151247.388837-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Bjorn Andersson Some clock implementations doesn't provide means of implementing is_enabled(), but still requires to be explicitly disabled when found unused as part of clk_disable_unused(). One such set of clocks are Qualcomm's display RCGs. These can be enabled and disabled automatically by the hardware, so it's not possible to reliably query their configuration. Further more, these clocks need to be disabled when unused, to allow them to be "parked" onto a safe parent. Failure to disable the RCG results in the hardware locking up as clk_disable_unused() traverses up the tree and turns off its source clocks. Add a new flag, CLK_ASSUME_ENABLED_BOOT, which clock drivers can use to signal that these clocks should be disabled even if they don't implement the is_enabled() ops. Signed-off-by: Bjorn Andersson Reviewed-by: Vinod Koul --- drivers/clk/clk.c | 2 +- include/linux/clk-provider.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index ed119182aa1b..9789ec137219 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -1284,7 +1284,7 @@ static void __init clk_disable_unused_subtree(struct clk_core *core) * sequence. call .disable_unused if available, otherwise fall * back to .disable */ - if (clk_core_is_enabled(core)) { + if (clk_core_is_enabled(core) || core->flags & CLK_ASSUME_ENABLED_WHEN_UNUSED) { trace_clk_disable(core); if (core->ops->disable_unused) core->ops->disable_unused(core->hw); diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index c10dc4c659e2..9038022ffebd 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -32,6 +32,8 @@ #define CLK_OPS_PARENT_ENABLE BIT(12) /* duty cycle call may be forwarded to the parent clock */ #define CLK_DUTY_CYCLE_PARENT BIT(13) +/* assume clock is enabled if found unused in late init */ +#define CLK_ASSUME_ENABLED_WHEN_UNUSED BIT(14) struct clk; struct clk_hw; From patchwork Fri Apr 29 15:12:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 568363 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F206C433FE for ; Fri, 29 Apr 2022 15:13:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378198AbiD2PQn (ORCPT ); Fri, 29 Apr 2022 11:16:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37598 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378153AbiD2PQi (ORCPT ); Fri, 29 Apr 2022 11:16:38 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68CF8D4C4A for ; Fri, 29 Apr 2022 08:13:19 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id i27so16030780ejd.9 for ; Fri, 29 Apr 2022 08:13:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fQi0DOXBFPjAV8nVfsEI5OyAGb7iRPNqL8WA0HHoYYo=; b=lKUPKkowXeHzT0Ta2KasThXbya7EFtctvOWcyGz5iwDiqINSSbxHap2PKm+/B9j3eS Ij7rnYLwrjrqQL5zCcpR/12PhxU6TPsXW9DDKLE+9SJ003FrFSA4tw/jrNsnwFiIvJwT cyHO6mVoc+EocyUXyh5Rs9m+yz3Qc9ZAlhkmfktW5doBHs7Z3GyMVcLE49AYoZdBNUnw xBK0dEbo/0uM0L/OFR5xb9sq2BK1FIP0ihGkY7afSyNF71Rka3c8kLTiLXRifZtJG6iE Pq4emV4PIVcxd1BycfaihyUt0UwWTuH8An7LAEZGgyX98tWkv9GSdBsKw0eG17GajR2Y Tj3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fQi0DOXBFPjAV8nVfsEI5OyAGb7iRPNqL8WA0HHoYYo=; b=7DjSlMmc4H2uaNwQ5BUnvhl0PFMtlm42CE4sJzvG4aKojMjkzwA/84GwHDD8N4Di2C lQMqKbsm6HNKp5fUsUuovDl/4Td5nc+sNRizFVPE1seLZopT5kLtGZSENSG9JK07nGSP higsFxYDw+HSUeaO0HFo2tGIBfmr2K0IW08pqoaZYb+bOmrFQPLhsaVqzvcFsp0QXuIu ZAzENJIvVmDwAGYOPcj9PyWBYeW8ASHvJtmGYvgyk2mBtjHRICKjurbhueGdYrRxiLpj RHpwkkq4FIrUyolktFNLgs/38TQSf6Js1veJCqvfKuc+M+lLieMnWoYpq+PWKZlJ+zLM 3bEQ== X-Gm-Message-State: AOAM531yqiMR1l4DA3ZLBfLWV8Xw9Hb3UGcO8GfbGUyboZfc05mwv4F2 8E/fbVZzJ4eJTJmFWgZjPD8N0w== X-Google-Smtp-Source: ABdhPJyiyPakItBCJpcb5vAA9BUIq2lU3LRgIu9Ty3XZQnr+dQcNqoKX4OYcyka0YZu3YtgKamPqZQ== X-Received: by 2002:a17:907:6d9d:b0:6da:7d4c:287f with SMTP id sb29-20020a1709076d9d00b006da7d4c287fmr35626405ejc.741.1651245197955; Fri, 29 Apr 2022 08:13:17 -0700 (PDT) Received: from prec5560.. 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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id zp15-20020a17090684ef00b006f3ef214e4esm712677ejb.180.2022.04.29.08.13.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 08:13:17 -0700 (PDT) From: Robert Foss To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, jonathan@marek.ca, tdas@codeaurora.org, anischal@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Foss Subject: [PATCH v1 5/9] dt-bindings: clock: Add Qcom SM8350 GPUCC bindings Date: Fri, 29 Apr 2022 17:12:43 +0200 Message-Id: <20220429151247.388837-5-robert.foss@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220429151247.388837-1-robert.foss@linaro.org> References: <20220429151247.388837-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SM8350 SoCs. Signed-off-by: Robert Foss --- .../devicetree/bindings/clock/qcom,gpucc.yaml | 2 + include/dt-bindings/clock/qcom,gpucc-sm8350.h | 52 +++++++++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,gpucc-sm8350.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml index 9ebcb1943b0a..4090cc7ea2ae 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -20,6 +20,7 @@ description: | dt-bindings/clock/qcom,gpucc-sm6350.h dt-bindings/clock/qcom,gpucc-sm8150.h dt-bindings/clock/qcom,gpucc-sm8250.h + dt-bindings/clock/qcom,gpucc-sm8350.h properties: compatible: @@ -31,6 +32,7 @@ properties: - qcom,sm6350-gpucc - qcom,sm8150-gpucc - qcom,sm8250-gpucc + - qcom,sm8350-gpucc clocks: items: diff --git a/include/dt-bindings/clock/qcom,gpucc-sm8350.h b/include/dt-bindings/clock/qcom,gpucc-sm8350.h new file mode 100644 index 000000000000..d2294e0d527e --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-sm8350.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H + +/* GPU_CC clocks */ +#define GPU_CC_AHB_CLK 0 +#define GPU_CC_CB_CLK 1 +#define GPU_CC_CRC_AHB_CLK 2 +#define GPU_CC_CX_APB_CLK 3 +#define GPU_CC_CX_GMU_CLK 4 +#define GPU_CC_CX_QDSS_AT_CLK 5 +#define GPU_CC_CX_QDSS_TRIG_CLK 6 +#define GPU_CC_CX_QDSS_TSCTR_CLK 7 +#define GPU_CC_CX_SNOC_DVM_CLK 8 +#define GPU_CC_CXO_AON_CLK 9 +#define GPU_CC_CXO_CLK 10 +#define GPU_CC_FREQ_MEASURE_CLK 11 +#define GPU_CC_GMU_CLK_SRC 12 +#define GPU_CC_GX_GMU_CLK 13 +#define GPU_CC_GX_QDSS_TSCTR_CLK 14 +#define GPU_CC_GX_VSENSE_CLK 15 +#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 16 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 17 +#define GPU_CC_HUB_AON_CLK 18 +#define GPU_CC_HUB_CLK_SRC 19 +#define GPU_CC_HUB_CX_INT_CLK 20 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 21 +#define GPU_CC_MND1X_0_GFX3D_CLK 22 +#define GPU_CC_MND1X_1_GFX3D_CLK 23 +#define GPU_CC_PLL0 24 +#define GPU_CC_PLL1 25 +#define GPU_CC_SLEEP_CLK 26 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CB_BCR 1 +#define GPUCC_GPU_CC_CX_BCR 2 +#define GPUCC_GPU_CC_FAST_HUB_BCR 3 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 +#define GPUCC_GPU_CC_GMU_BCR 5 +#define GPUCC_GPU_CC_GX_BCR 6 +#define GPUCC_GPU_CC_XO_BCR 7 + +/* GPU_CC GDSCRs */ +#define GPU_CX_GDSC 0 +#define GPU_GX_GDSC 1 + +#endif From patchwork Fri Apr 29 15:12:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 568365 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D12BC433F5 for ; Fri, 29 Apr 2022 15:13:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378153AbiD2PQo (ORCPT ); Fri, 29 Apr 2022 11:16:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378193AbiD2PQn (ORCPT ); Fri, 29 Apr 2022 11:16:43 -0400 Received: from mail-ed1-x529.google.com (mail-ed1-x529.google.com [IPv6:2a00:1450:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50804D4C5D for ; Fri, 29 Apr 2022 08:13:21 -0700 (PDT) Received: by mail-ed1-x529.google.com with SMTP id d6so9427660ede.8 for ; Fri, 29 Apr 2022 08:13:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=w/pXKsIVtTt17T7eqOsQpzzU4pjcYkRpODXJuKrygBs=; b=qhoH2FDzI2r9J7YmoLEBPdrwoQpwroyKf0bFdZXPLT1yXXwZQG7W8jtA5HutLf1Tt+ 1rhR4jwZ5e344uRkVQo+e1ujhvHlOQIm6sLTSsSHBz42CWUwBn765BewzMqE3Kk5xHHk n6E3edzZN+jVL2xfNOtkH8vsJB4EVPiUDnZr6sMpg38AYDi842dM4S4Vyvb4r/8U9Bwk 8WsTU669x0kmyeU+/AmufDwrdnxk7kLuEoO8IIyTZ5xbaNlI1/Et1CMrCahdvGBOY3XS xBfCxPNnux+wnD7WXE7UIMNPjSGq8F7x7RjpY32laQBcbpsOtJxkZpjvH7ODhB2bNMsZ FAOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=w/pXKsIVtTt17T7eqOsQpzzU4pjcYkRpODXJuKrygBs=; b=ypcyYjrBo2s+UIhDfBSjstbg4ceVGsOiMTk0SCVtyJwy9T8xaF/oSSwffNjpbURDCz moh/wCNpRrtaMveuhz90UuH9ILIY7G2PWD7rPqDv6Pk6jrAcQXpxjfrdgvQTZVmg5Dam rwoyFeXmLQmDrcZVjyMSlr/xA6k4egMuzT5gnuV3T6xcpbPYFBjnz2ygApMMRRHzg9N3 6b/22s0ms8z1vC2kVj7+IKUui+VFb0WNKWXo9JsE194KSlDIt55iu8lqobVVuig3scwp qimhiorLEilK55yz0hT8aTuK5ExA7wZ4CbezXzG3dZamvsrDqV9BIOg5Q4xcEX1Z1vfm /Tcw== X-Gm-Message-State: AOAM530PTnEYrnHeCUfHcbKylXtBnWi1XX7onZAJn+Uh7Im8sJ1kq45N 1Ur7ABX72p5HHp4lPMAvkXgK6A== X-Google-Smtp-Source: ABdhPJwuEP74LZIyjKBM8JgUaiSPybNLz2UTsmlnFTikNMAUZ25Eu4D/0ImLyuyQT5C3NqoHauTKIQ== X-Received: by 2002:a05:6402:3484:b0:426:156:94e6 with SMTP id v4-20020a056402348400b00426015694e6mr17846939edc.401.1651245199458; Fri, 29 Apr 2022 08:13:19 -0700 (PDT) Received: from prec5560.. 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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id zp15-20020a17090684ef00b006f3ef214e4esm712677ejb.180.2022.04.29.08.13.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 08:13:19 -0700 (PDT) From: Robert Foss To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, jonathan@marek.ca, tdas@codeaurora.org, anischal@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 6/9] clk: qcom: add support for SM8350 DISPCC Date: Fri, 29 Apr 2022 17:12:44 +0200 Message-Id: <20220429151247.388837-6-robert.foss@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220429151247.388837-1-robert.foss@linaro.org> References: <20220429151247.388837-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jonathan Marek Add support to the SM8350 display clock controller by extending the SM8250 display clock controller, which is almost identical but has some minor differences. Signed-off-by: Jonathan Marek --- drivers/clk/qcom/Kconfig | 4 +-- drivers/clk/qcom/dispcc-sm8250.c | 61 +++++++++++++++++++++++++++++++- 2 files changed, 62 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 9b1f54e634b9..1752ca0ee405 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -609,11 +609,11 @@ config SM_DISPCC_6125 splash screen config SM_DISPCC_8250 - tristate "SM8150 and SM8250 Display Clock Controller" + tristate "SM8150/SM8250/SM8350 Display Clock Controller" depends on SM_GCC_8150 || SM_GCC_8250 help Support for the display clock controller on Qualcomm Technologies, Inc - SM8150 and SM8250 devices. + SM8150/SM8250/SM8350 devices. Say Y if you want to support display devices and functionality such as splash screen. diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c index 22d9cbabecab..95f86ffcc3b3 100644 --- a/drivers/clk/qcom/dispcc-sm8250.c +++ b/drivers/clk/qcom/dispcc-sm8250.c @@ -43,6 +43,10 @@ static struct pll_vco vco_table[] = { { 249600000, 2000000000, 0 }, }; +static struct pll_vco lucid_5lpe_vco[] = { + { 249600000, 1750000000, 0 }, +}; + static struct alpha_pll_config disp_cc_pll0_config = { .l = 0x47, .alpha = 0xE000, @@ -1228,6 +1232,7 @@ static const struct of_device_id disp_cc_sm8250_match_table[] = { { .compatible = "qcom,sc8180x-dispcc" }, { .compatible = "qcom,sm8150-dispcc" }, { .compatible = "qcom,sm8250-dispcc" }, + { .compatible = "qcom,sm8350-dispcc" }, { } }; MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table); @@ -1258,7 +1263,7 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) return PTR_ERR(regmap); } - /* note: trion == lucid, except for the prepare() op */ + /* Apply differences for SM8150 and SM8350 */ BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID); if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") || of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) { @@ -1270,8 +1275,62 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024; disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0; disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops; + } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) { + static struct clk_rcg2 * const rcgs[] = { + &disp_cc_mdss_byte0_clk_src, + &disp_cc_mdss_byte1_clk_src, + &disp_cc_mdss_dp_aux1_clk_src, + &disp_cc_mdss_dp_aux_clk_src, + &disp_cc_mdss_dp_link1_clk_src, + &disp_cc_mdss_dp_link_clk_src, + &disp_cc_mdss_dp_pixel1_clk_src, + &disp_cc_mdss_dp_pixel2_clk_src, + &disp_cc_mdss_dp_pixel_clk_src, + &disp_cc_mdss_esc0_clk_src, + &disp_cc_mdss_mdp_clk_src, + &disp_cc_mdss_pclk0_clk_src, + &disp_cc_mdss_pclk1_clk_src, + &disp_cc_mdss_rot_clk_src, + &disp_cc_mdss_vsync_clk_src, + }; + static struct clk_regmap_div * const divs[] = { + &disp_cc_mdss_byte0_div_clk_src, + &disp_cc_mdss_byte1_div_clk_src, + &disp_cc_mdss_dp_link1_div_clk_src, + &disp_cc_mdss_dp_link_div_clk_src, + }; + unsigned int i; + static bool offset_applied; + + /* only apply the offsets once (in case of deferred probe) */ + if (!offset_applied) { + for (i = 0; i < ARRAY_SIZE(rcgs); i++) + rcgs[i]->cmd_rcgr -= 4; + + for (i = 0; i < ARRAY_SIZE(divs); i++) { + divs[i]->reg -= 4; + divs[i]->width = 4; + } + + disp_cc_mdss_ahb_clk.halt_reg -= 4; + disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4; + + offset_applied = true; + } + + disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0; + + disp_cc_pll0_config.config_ctl_hi1_val = 0x2A9A699C; + disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000; + disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops; + disp_cc_pll0.vco_table = lucid_5lpe_vco; + disp_cc_pll1_config.config_ctl_hi1_val = 0x2A9A699C; + disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000; + disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops; + disp_cc_pll1.vco_table = lucid_5lpe_vco; } + /* note for SM8350: downstream lucid_5lpe configure differs slightly */ clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); From patchwork Fri Apr 29 15:12:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Foss X-Patchwork-Id: 568364 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DC84AC433F5 for ; Fri, 29 Apr 2022 15:13:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378218AbiD2PQr (ORCPT ); Fri, 29 Apr 2022 11:16:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37922 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378222AbiD2PQq (ORCPT ); Fri, 29 Apr 2022 11:16:46 -0400 Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4233D4C4F for ; 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[176.74.57.43]) by smtp.gmail.com with ESMTPSA id zp15-20020a17090684ef00b006f3ef214e4esm712677ejb.180.2022.04.29.08.13.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 08:13:24 -0700 (PDT) From: Robert Foss To: bjorn.andersson@linaro.org, agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, jonathan@marek.ca, tdas@codeaurora.org, anischal@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Foss Subject: [PATCH v1 9/9] arm64: dts: qcom: sm8350: Add DISPCC node Date: Fri, 29 Apr 2022 17:12:47 +0200 Message-Id: <20220429151247.388837-9-robert.foss@linaro.org> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220429151247.388837-1-robert.foss@linaro.org> References: <20220429151247.388837-1-robert.foss@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the dispcc clock-controller DT node for sm8350. Signed-off-by: Robert Foss --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index c49735d1b458..252fdef927cb 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -3,7 +3,9 @@ * Copyright (c) 2020, Linaro Limited */ +#include #include +#include #include #include #include @@ -2533,6 +2535,29 @@ usb_2_dwc3: usb@a800000 { }; }; + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8350-dispcc"; + reg = <0 0x0af00000 0 0x10000>; + mmcx-supply = <&mmcx_reg>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + clock-names = "bi_tcxo", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dsi1_phy_pll_out_byteclk", + "dsi1_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + adsp: remoteproc@17300000 { compatible = "qcom,sm8350-adsp-pas"; reg = <0 0x17300000 0 0x100>;