From patchwork Fri Apr 29 21:42:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 568332 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69EF8C4167B for ; Fri, 29 Apr 2022 21:42:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238609AbiD2VqQ (ORCPT ); Fri, 29 Apr 2022 17:46:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57510 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238637AbiD2VqP (ORCPT ); Fri, 29 Apr 2022 17:46:15 -0400 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B86A978FE3 for ; Fri, 29 Apr 2022 14:42:54 -0700 (PDT) Received: by mail-lj1-x22f.google.com with SMTP id 17so11997796lji.1 for ; Fri, 29 Apr 2022 14:42:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WbPm7wPFz42k3w9HjVTRf/Wo4cb2U+ygFCZJLREQuWI=; b=c82XR8chvTx0ayhTAPNs1n2FMh/H4yVn5Vitbl4A+wtGjE8fDcZgXWDDycoV1z8q0a qvu+5qA25yMdD1bCuTdQ8wgVjgDSvKYSR2l6MJvCl1DQTdWt8LZuKbyyjqRv2le6pM8z tlmF2y2jE9oe+mN0AXTuxAzmrit+tEVblyEaOM5/iTHh/iQvkhO9Q8qCoZeJMYNFVzdS VMilk/8KuPA6qP5aq/xBgAmHlET8U8QScy+QYV49q/TWXI+WkRMKSN8pNrsTJWh4VNPi 3fDChBJU5k8plzXZgcoP1sG4iBTMUX604Aga94jrpd93aeW3v3glLsBtWRbAFRrkTTAq 2I4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WbPm7wPFz42k3w9HjVTRf/Wo4cb2U+ygFCZJLREQuWI=; b=UaM3UcjpTCttvzfSGMp4wJGl/auV1VFLRftXQJXme4eYfYXd49iCQCgwKdlhg88Uto v4rksP/hFppAZijwEH6ex5LxNMbn1TEIjQiTVu9T1gkbHG/7EWsALJZ4HYHwmAVHjEQu GweNDmmHUYDGrTI+9XeEozet9yooKj69KJg/RNXV+CURCl8aQ4T39aNwdsvkCmajyjpi D+EjbOSFwnZFDFF25iE9m52ISLtZSEQ8+3jsHlc24xzzBv1ouJTNEnJVcz6//FPAvOar hzn/3+X0HoHt6wIOU7cfUVOCKGfelaEdWNe2NXKvTpEb2obmf58yw1Tk+t2Lfb8PmlyM TfEw== X-Gm-Message-State: AOAM5308116tzBA2Cel07W1OI3Eg2VmF5mzHeNK+EJuW1ZJyL/rgYd/5 VXeeCgF3QRhzviwG8BvupvRgEg== X-Google-Smtp-Source: ABdhPJyPJJ/vuHiUdGNPITvMM7UFkeYlT4CiD9o0gX6e4HdkBHt/8FtoRxuHUajfqArKisGWUlkDRw== X-Received: by 2002:a05:651c:54c:b0:24f:2919:25ac with SMTP id q12-20020a05651c054c00b0024f291925acmr782134ljp.122.1651268572952; Fri, 29 Apr 2022 14:42:52 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id g4-20020a19ac04000000b0047255d211f6sm30520lfc.293.2022.04.29.14.42.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 14:42:52 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 2/7] PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi() Date: Sat, 30 Apr 2022 00:42:45 +0300 Message-Id: <20220429214250.3728510-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429214250.3728510-1-dmitry.baryshkov@linaro.org> References: <20220429214250.3728510-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The subdrivers pass -ESOMETHING if they do not want the core to touch MSI IRQ. dw_pcie_host_init() also checks if (msi_irq > 0) rather than just if (msi_irq). So let's make dw_pcie_free_msi() also check that msi_irq is greater than zero. Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-designware-host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 2fa86f32d964..43d1d6116007 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -257,7 +257,7 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) static void dw_pcie_free_msi(struct pcie_port *pp) { - if (pp->msi_irq) + if (pp->msi_irq > 0) irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL); irq_domain_remove(pp->msi_domain); From patchwork Fri Apr 29 21:42:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 568331 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33ED9C433EF for ; Fri, 29 Apr 2022 21:43:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238677AbiD2VqS (ORCPT ); Fri, 29 Apr 2022 17:46:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238675AbiD2VqR (ORCPT ); Fri, 29 Apr 2022 17:46:17 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2953779396 for ; Fri, 29 Apr 2022 14:42:56 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id x33so16271868lfu.1 for ; Fri, 29 Apr 2022 14:42:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ncVhMJxrohn0+P1cFmOcnIFJEP0t7Z52SvJtNUy/BIs=; b=kSx8B5MYfuey4jDbsS/+ZnbpWUK2aYadezjOYORGZO7ZMCnbSzJEx+qjmYl4jCkBTP NgcQUoKQh8FUG1ZLnHV6dJM1decZ/GZ9SH76nDJY+TW9r+Qej48E5wXQKcLuRz3c0MxF 9Mf1YmC2uEoNbARiCHawAfNQmyyyfRelRQrjAprm+w5yg1UpUL+PkFRGKOnAMpIPEsGw H2gXXniOUJ3bb7sQfc/7Am/RExBpGuyPDp7ZPG5mYxNMV/T+vnKdjjh51PaUVTGrXEOz plx9CPa+pufDSZd+YBIgHSPbbks5NO2WSl4+h5kOBzNI/jMLKbO7xX1pESblv73aJdEW 27sA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ncVhMJxrohn0+P1cFmOcnIFJEP0t7Z52SvJtNUy/BIs=; b=SyG+ONNoDEh5e4sDckvqaQ94HoZ4k2JY3BMCveeDZ55NCJXVU8+1/bJoAMpfn3Sgbm 6GlckAKfRb9drRNgaYfqrTD7vjl/9DVMSyU8r5zvjn+/iwZO7mJAPoAbVprqQ77G0KYT oWIZb6J7G6ZVJXj8kDx7OqjKp3pKJ6rFFSCeKs8gmUKGZ4mySljDD2aGkob0A1D+JU5W FKzkbgqabLwZWOT5WJqLqPiKgHBNE3s/mzkQKEC9uGW+ls5OdiFr1Z8FDaXL4lt62QU4 63W2/NQqvK1fHF6tx7M9XFutpMO+ZjHn0CIHgfN/xa5UzsSBUJind2D90/8hC2u05mpQ +PZQ== X-Gm-Message-State: AOAM531t+Spz/uyELR+5k4e3TsCVSHxShxEPhO4UzOc8HMOBXbnGPvPf Sy94RHSQjDf2svhQb8BQ3pkl6g== X-Google-Smtp-Source: ABdhPJzkBzz2G5DWzhONhXDruSg7+Bk4LQdmYe9bzBfn6j9UQ2ibE3/hmIHstMCJACe4hozziai3YA== X-Received: by 2002:ac2:4ac9:0:b0:471:f6da:640d with SMTP id m9-20020ac24ac9000000b00471f6da640dmr900074lfp.286.1651268574342; Fri, 29 Apr 2022 14:42:54 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id g4-20020a19ac04000000b0047255d211f6sm30520lfc.293.2022.04.29.14.42.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 14:42:54 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 4/7] PCI: dwc: Export several functions useful for MSI implentations Date: Sat, 30 Apr 2022 00:42:47 +0300 Message-Id: <20220429214250.3728510-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429214250.3728510-1-dmitry.baryshkov@linaro.org> References: <20220429214250.3728510-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Supporting multiple MSI interrupts on Qualcomm hardware would benefit from having these functions being exported rather than static. Note that both designware and qcom driver can not be built as modules, so no need to use EXPORT_SYMBOL here. Signed-off-by: Dmitry Baryshkov --- .../pci/controller/dwc/pcie-designware-host.c | 62 ++++++++++++------- drivers/pci/controller/dwc/pcie-designware.h | 11 ++++ 2 files changed, 49 insertions(+), 24 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 92dcaeabe2bf..c3b8ab278a00 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -255,7 +255,39 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) return 0; } -static void dw_pcie_free_msi(struct pcie_port *pp) +int dw_pcie_allocate_msi(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + int ret; + + ret = dw_pcie_allocate_domains(pp); + if (ret) + return ret; + + if (pp->msi_irq > 0) + irq_set_chained_handler_and_data(pp->msi_irq, + dw_chained_msi_isr, + pp); + + ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); + if (ret) + dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); + + pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg, + sizeof(pp->msi_msg), + DMA_FROM_DEVICE, + DMA_ATTR_SKIP_CPU_SYNC); + ret = dma_mapping_error(pci->dev, pp->msi_data); + if (ret) { + dev_err(pci->dev, "Failed to map MSI data\n"); + pp->msi_data = 0; + return ret; + } + + return 0; +} + +void dw_pcie_free_msi(struct pcie_port *pp) { if (pp->msi_irq > 0) irq_set_chained_handler_and_data(pp->msi_irq, NULL, NULL); @@ -357,6 +389,9 @@ int dw_pcie_host_init(struct pcie_port *pp) return -EINVAL; } + /* this can be overridden by msi_host_init() if necessary */ + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; + if (pp->ops->msi_host_init) { ret = pp->ops->msi_host_init(pp); if (ret < 0) @@ -377,30 +412,9 @@ int dw_pcie_host_init(struct pcie_port *pp) } } - pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; - - ret = dw_pcie_allocate_domains(pp); - if (ret) + ret = dw_pcie_allocate_msi(pp); + if (ret < 0) return ret; - - if (pp->msi_irq > 0) - irq_set_chained_handler_and_data(pp->msi_irq, - dw_chained_msi_isr, - pp); - - ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32)); - if (ret) - dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n"); - - pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg, - sizeof(pp->msi_msg), - DMA_FROM_DEVICE, - DMA_ATTR_SKIP_CPU_SYNC); - if (dma_mapping_error(pci->dev, pp->msi_data)) { - dev_err(pci->dev, "Failed to map MSI data\n"); - pp->msi_data = 0; - goto err_free_msi; - } } } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index e1c48b71e0d2..f72447f15dc5 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -374,6 +374,8 @@ void dw_pcie_host_deinit(struct pcie_port *pp); int dw_pcie_allocate_domains(struct pcie_port *pp); void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where); +int dw_pcie_allocate_msi(struct pcie_port *pp); +void dw_pcie_free_msi(struct pcie_port *pp); #else static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) { @@ -403,6 +405,15 @@ static inline void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, { return NULL; } + +static int dw_pcie_allocate_msi(struct pcie_port *pp) +{ + return -EINVAL; +} + +static void dw_pcie_free_msi(struct pcie_port *pp) +{ +} #endif #ifdef CONFIG_PCIE_DW_EP From patchwork Fri Apr 29 21:42:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 568330 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98447C3527D for ; Fri, 29 Apr 2022 21:43:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238269AbiD2VqU (ORCPT ); Fri, 29 Apr 2022 17:46:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238675AbiD2VqS (ORCPT ); Fri, 29 Apr 2022 17:46:18 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 900537B112 for ; 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Fri, 29 Apr 2022 14:42:56 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id g4-20020a19ac04000000b0047255d211f6sm30520lfc.293.2022.04.29.14.42.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Apr 2022 14:42:56 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam Cc: Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v5 7/7] arm64: dts: qcom: sm8250: provide additional MSI interrupts Date: Sat, 30 Apr 2022 00:42:50 +0300 Message-Id: <20220429214250.3728510-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220429214250.3728510-1-dmitry.baryshkov@linaro.org> References: <20220429214250.3728510-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On SM8250 each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe0 host. Tested on Qualcomm RB5 platform with first group of MSI interrupts being used by the PME and attached ath11k WiFi chip using second group of MSI interrupts. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 410272a1e19b..0659ac45c651 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1807,8 +1807,15 @@ pcie0: pci@1c00000 { ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi", "msi2", "msi3", "msi4", "msi5", "msi6", "msi7", "msi8"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */