From patchwork Fri Dec 21 16:02:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 154399 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1086935ljp; Fri, 21 Dec 2018 08:02:55 -0800 (PST) X-Google-Smtp-Source: ALg8bN7wXLBP+E0F9HVE8jgBmK1mIKJI7HwKlICiz79lcLfP2Qaz/WJ4X5Jw6VxmuZKdXze0qjBQ X-Received: by 2002:a63:9d05:: with SMTP id i5mr2733703pgd.98.1545408175840; Fri, 21 Dec 2018 08:02:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545408175; cv=none; d=google.com; s=arc-20160816; b=spTeD5wRg0RCo0o2ZXn18oewPRThoUmOGzWKcWMoX1hnjW7zaBA/9IEupT/XAru4ai FYC8irGmmyxWSVfTpcSON2F87J2+8trqZms6S+dVlCrdqNC1zDYvnDNXBsUO1NaDHgVe QzlgB+QpTMBLlcAnLiCSWzQFqps7O6eyYV046xXU4vmqw8tudxQrgbGqy5+igZcaRSwJ CuGz203fRglrPC6+MIZ+YAqmigV0wnGBj1p7mR77ZTz0U6dg2HJKjjfn4ZZy7Ziv6biM qyEs560VRlHLcjIU7jFycr9R/ry+Da59QlGCsyXCtOaKL/5XX9DP3MF+qYHY1vQJwnNN gZpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FLkfbrFTeHQRtZznQmsDFo42KqctA5AQOYQ6mqTjbJM=; b=VI+mYWltKed+Ju9Wgyl+Z3EMTlvScROgoEGnOHnT0kVR0eomCY9f/jNHRNy0edEs64 jCPAIwxCu0P5qLolMKKwjqgcT0kimj1mQM/0zRwBmDseEuLxO2FUWf/0ZDxENypHSYQG Hd3UWEgOHbIW7+nDCQj4BI/SclM8wHTQMz7iPZ3z9/P7tCYYIs4lD8dNM8+ljujjs/ij Iz3CaTtmJaj/zd/nUcymb+XbtnEULMIA6uRLwp/J4aoUDrjNVuZNCr2JfkGUUyqYSbo2 oSs9mbGuNeXz7MlWYQbuul6tWj7goe0c/omGfWUwczA6T+UkuaWX4EbQHou38nBt7OnP ySEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=wnppx2t5; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m142si23227506pfd.171.2018.12.21.08.02.55; Fri, 21 Dec 2018 08:02:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=wnppx2t5; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388024AbeLUQCz (ORCPT + 6 others); Fri, 21 Dec 2018 11:02:55 -0500 Received: from mail-wr1-f68.google.com ([209.85.221.68]:42932 "EHLO mail-wr1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387962AbeLUQCy (ORCPT ); Fri, 21 Dec 2018 11:02:54 -0500 Received: by mail-wr1-f68.google.com with SMTP id q18so5777447wrx.9 for ; Fri, 21 Dec 2018 08:02:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FLkfbrFTeHQRtZznQmsDFo42KqctA5AQOYQ6mqTjbJM=; b=wnppx2t5Vr1TlkjvF86pUCcvQUgNVK1bUbdZZ5+VOROVCe7dKGOkSE580fscLyag31 oHt8voN8AayeXZkDWH17hC1Hv83KFWhYBtEjkuSqneVUjx2bEz7IzpUqhuVZrLKxD2+c AneJc37CrhmrD/Ihd7EWiG8Zc/Icj5m97qABWqtEU3h3Xbh0iZqYpJ03R9gjIm7e4JFt Uv2oLI4k+HETpfRUOi/S1GVQUo+1rbthcDX37UXAJatRoI4Un3JcSdz6G3CXlgYpESoA cIlPauMhw4aTU1ejJCKw/VnWGNqFM3crDgRMn8j4Hz2yGnHB94SX0km4H2UDMTHyS9bR HWww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FLkfbrFTeHQRtZznQmsDFo42KqctA5AQOYQ6mqTjbJM=; b=Gxpwd2rqNpUgTHhlCqyCwnKGkC3sUvp0sh9MN2ml87riVHtKZ7SlqWmNxhMk3sWdB4 HXffSf0zkpF64YIfYviHCtOsDLXF9P8dpTNY33TFf9efbf8FqsZI4bODR4cu3dPj24nx rZP+t2M4YRTHgQomq5ODgxMRSzJ7oWTQN2KmUalY0pyx88FM0nwGHuqzauKmZII9j89D sNgMLwIvnndobGG18/HzgnnJsxQxdjGUDJ/gvtLaSeADgTckKVO+RoEmFu679YJdLCxk AYxcRvnqTgxEBmI1dqHX/eWJ6ds8Hsd1VtNpfy3v/w2G+1O7GUHMpHGQjpbdvwhv2Tn4 fRLA== X-Gm-Message-State: AJcUukdM+UOol7Cti2gJucdkE0p8mroh8GISgeMC6jKSW3YFvn4DmbZw N8m6RCudYXgPv92yWKDc3HCzhQ== X-Received: by 2002:adf:9382:: with SMTP id 2mr3140125wrp.269.1545408172554; Fri, 21 Dec 2018 08:02:52 -0800 (PST) Received: from boomer.local ([2a01:e34:eeb6:4690:106b:bae3:31ed:7561]) by smtp.googlemail.com with ESMTPSA id y138sm13044021wmc.16.2018.12.21.08.02.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 21 Dec 2018 08:02:51 -0800 (PST) From: Jerome Brunet To: Neil Armstrong , Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-clk@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 3/5] clk: meson: add dual divider clock driver Date: Fri, 21 Dec 2018 17:02:37 +0100 Message-Id: <20181221160239.26265-4-jbrunet@baylibre.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181221160239.26265-1-jbrunet@baylibre.com> References: <20181221160239.26265-1-jbrunet@baylibre.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the dual divider driver. This special divider make a weighted average between 2 dividers to reach fractional divider values. Signed-off-by: Jerome Brunet --- drivers/clk/meson/Makefile | 2 +- drivers/clk/meson/clk-dualdiv.c | 130 ++++++++++++++++++++++++++++++++ drivers/clk/meson/clkc.h | 19 +++++ 3 files changed, 150 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/meson/clk-dualdiv.c -- 2.19.2 diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index a849aa809825..f1fcafc046d5 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -3,7 +3,7 @@ # obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o vid-pll-div.o -obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-input.o +obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-input.o clk-dualdiv.o obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o sclk-div.o obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o diff --git a/drivers/clk/meson/clk-dualdiv.c b/drivers/clk/meson/clk-dualdiv.c new file mode 100644 index 000000000000..4d9e161de627 --- /dev/null +++ b/drivers/clk/meson/clk-dualdiv.c @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2017 BayLibre, SAS + * Author: Neil Armstrong + * Author: Jerome Brunet + */ + +/* + * The AO Domain embeds a dual/divider to generate a more precise + * 32,768KHz clock for low-power suspend mode and CEC. + * ______ ______ + * | | | | + * | Div1 |-| Cnt1 | + * /|______| |______|\ + * -| ______ ______ X--> Out + * \| | | |/ + * | Div2 |-| Cnt2 | + * |______| |______| + * + * The dividing can be switched to single or dual, with a counter + * for each divider to set when the switching is done. + */ + +#include +#include "clkc.h" + +static inline struct meson_clk_dualdiv_data * +meson_clk_dualdiv_data(struct clk_regmap *clk) +{ + return (struct meson_clk_dualdiv_data *)clk->data; +} + +static unsigned long +__dualdiv_param_to_rate(unsigned long parent_rate, + const struct meson_clk_dualdiv_param *p) +{ + if (!p->dual) + return DIV_ROUND_CLOSEST(parent_rate, p->n1); + + return DIV_ROUND_CLOSEST(parent_rate * (p->m1 + p->m2), + p->n1 * p->m1 + p->n2 * p->m2); +} + +static unsigned long meson_clk_dualdiv_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_dualdiv_data *dualdiv = meson_clk_dualdiv_data(clk); + struct meson_clk_dualdiv_param setting; + + setting.dual = meson_parm_read(clk->map, &dualdiv->dual); + setting.n1 = meson_parm_read(clk->map, &dualdiv->n1) + 1; + setting.m1 = meson_parm_read(clk->map, &dualdiv->m1) + 1; + setting.n2 = meson_parm_read(clk->map, &dualdiv->n2) + 1; + setting.m2 = meson_parm_read(clk->map, &dualdiv->m2) + 1; + + return __dualdiv_param_to_rate(parent_rate, &setting); +} + +static const struct meson_clk_dualdiv_param * +__dualdiv_get_setting(unsigned long rate, unsigned long parent_rate, + struct meson_clk_dualdiv_data *dualdiv) +{ + const struct meson_clk_dualdiv_param *table = dualdiv->table; + unsigned long best = 0, now = 0; + unsigned int i, best_i = 0; + + if (!table) + return NULL; + + for (i = 0; table[i].n1; i++) { + now = __dualdiv_param_to_rate(parent_rate, &table[i]); + + /* If we get an exact match, don't bother any further */ + if (now == rate) { + return &table[i]; + } else if (abs(now - rate) < abs(best - rate)) { + best = now; + best_i = i; + } + } + + return (struct meson_clk_dualdiv_param *)&table[best_i]; +} + +static long meson_clk_dualdiv_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_dualdiv_data *dualdiv = meson_clk_dualdiv_data(clk); + const struct meson_clk_dualdiv_param *setting = + __dualdiv_get_setting(rate, *parent_rate, dualdiv); + + if (!setting) + return meson_clk_dualdiv_recalc_rate(hw, *parent_rate); + + return __dualdiv_param_to_rate(*parent_rate, setting); +} + +static int meson_clk_dualdiv_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_dualdiv_data *dualdiv = meson_clk_dualdiv_data(clk); + const struct meson_clk_dualdiv_param *setting = + __dualdiv_get_setting(rate, parent_rate, dualdiv); + + if (!setting) + return -EINVAL; + + meson_parm_write(clk->map, &dualdiv->dual, setting->dual); + meson_parm_write(clk->map, &dualdiv->n1, setting->n1 - 1); + meson_parm_write(clk->map, &dualdiv->m1, setting->m1 - 1); + meson_parm_write(clk->map, &dualdiv->n2, setting->n2 - 1); + meson_parm_write(clk->map, &dualdiv->m2, setting->m2 - 1); + + return 0; +} + +const struct clk_ops meson_clk_dualdiv_ops = { + .recalc_rate = meson_clk_dualdiv_recalc_rate, + .round_rate = meson_clk_dualdiv_round_rate, + .set_rate = meson_clk_dualdiv_set_rate, +}; +EXPORT_SYMBOL_GPL(meson_clk_dualdiv_ops); + +const struct clk_ops meson_clk_dualdiv_ro_ops = { + .recalc_rate = meson_clk_dualdiv_recalc_rate, +}; +EXPORT_SYMBOL_GPL(meson_clk_dualdiv_ro_ops); diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index 6183b22c4bf2..e3cd442db739 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -110,6 +110,23 @@ struct clk_regmap _name = { \ }, \ }; +struct meson_clk_dualdiv_param { + unsigned int n1; + unsigned int n2; + unsigned int m1; + unsigned int m2; + unsigned int dual; +}; + +struct meson_clk_dualdiv_data { + struct parm n1; + struct parm n2; + struct parm m1; + struct parm m2; + struct parm dual; + const struct meson_clk_dualdiv_param *table; +}; + /* clk_ops */ extern const struct clk_ops meson_clk_pll_ro_ops; extern const struct clk_ops meson_clk_pll_ops; @@ -118,6 +135,8 @@ extern const struct clk_ops meson_clk_mpll_ro_ops; extern const struct clk_ops meson_clk_mpll_ops; extern const struct clk_ops meson_clk_phase_ops; extern const struct clk_ops meson_vid_pll_div_ro_ops; +extern const struct clk_ops meson_clk_dualdiv_ops; +extern const struct clk_ops meson_clk_dualdiv_ro_ops; struct clk_hw *meson_clk_hw_register_input(struct device *dev, const char *of_name, From patchwork Fri Dec 21 16:02:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 154401 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp1087088ljp; Fri, 21 Dec 2018 08:03:03 -0800 (PST) X-Google-Smtp-Source: AFSGD/WdITP2IHwcolRFu7KbeDAOUME5E/gjEkGEnbdHQ7CBPYdI1Hn1JdiZuRY7A5kwHbeVfK7H X-Received: by 2002:a62:1b83:: with SMTP id b125mr3240403pfb.42.1545408183555; Fri, 21 Dec 2018 08:03:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545408183; cv=none; d=google.com; s=arc-20160816; b=XFhDzM1wsDjzEZiZ5vcm+kMfZ20eB4u76cHFINwdNSeuWst7DnEqn7ZTxIUYSeXbXx e5tzVY1lYq69QUyKWTLiXrWW82V363/htDaBlSB+37EfYdVOMNEcqOZJPFar7IK/E/bX l741kWnpHp5lY5CmmzeQG3aCRHlrluCEHo0G0h1VSnMQFH8duVP3ZaWK9fPnmVlT7fKd OF7tjYwmODKX/Ms7QHFd/0BZ6UkIZm3nfv8ishINzArMFESUt7li1UEM1Sy4Rkc9nQTn wiKJ0inJEEzCJGtuR9ukEkP1CH9wibKydKGr8dDCZrlzL0XG3EX6jRzNhJmIcbqd5qh+ CcVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=zzbm13PIonVfBVmeY6obszSgV2a/9581FnWBBbtOFLc=; b=oIuN7dWnn6jjuG9AKtGDwbMbFyxplRzYR3ezz566bivRA5Q6+skKg4x8shCIgdZYsl zfdKvzbx3t5N4RLNpQzwHq8OotdpaRgP3duZEYiwLcSbCx1hmTMTXE1y2EyPdqviHOVi BpAfhJfGhjO8ynWi6eJ0T7vlLNu+ZVut/vuEu/UANRYuZgzoERRFI2Frue+HsrWwVGGw YMNIumTEmeUZexsndkRmQNrQexH38ccyo/ND9zRDmxWtt39cOr/j0ICcfFG1VFsTNsB8 NeVDqwEKwHCCDThkGA/BKqmucA/NIA/BCOMnsDgd97fveV1HDwq3lJWy6PN1PzsOcKYo 4fIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=jNZ6w6hk; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g8si15708070pgo.166.2018.12.21.08.03.03; Fri, 21 Dec 2018 08:03:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=jNZ6w6hk; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388092AbeLUQDB (ORCPT + 6 others); Fri, 21 Dec 2018 11:03:01 -0500 Received: from mail-wm1-f66.google.com ([209.85.128.66]:37013 "EHLO mail-wm1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388057AbeLUQDA (ORCPT ); Fri, 21 Dec 2018 11:03:00 -0500 Received: by mail-wm1-f66.google.com with SMTP id g67so6206170wmd.2 for ; Fri, 21 Dec 2018 08:02:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zzbm13PIonVfBVmeY6obszSgV2a/9581FnWBBbtOFLc=; b=jNZ6w6hkm+oei4av6eSl2KsaPY58pjfpG87YY97wtzz3HnJFGzJX7OOZwQ4m1SDUDa ypHBmcKa8JRvr/gPKNlPSxmTyIhHsl3eS3g0Xm9bSyQhT4nVf8wEMptfRXCUFO88MO1Z nnJUWtIiobDI2NcdC7IKyZBT3NAMtmq3eZcqm+ch7zZKR7BFy94eEMghWkPgi0RXnqkE lnAskn9/an8bXQ52lfKAe+MamurRinnRcNMSrKkPM6UduNb/9edWQlZ2BmQvNAftmmN/ PcwaUdLuJ0fXZpsCHWHR+QSkiNBGTMRhTL7ylvxZ0BgU762cOr1/fyeev3yrB/ucCNCQ +ZlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zzbm13PIonVfBVmeY6obszSgV2a/9581FnWBBbtOFLc=; b=lqzKU4gy/fUl9FzMqAkD5xZSCV3AgJYG/2Dl1zFmJlwV0nvLKp+tuBEsljiOnSuAYz SxC8al5GgLRdAPapcUBzCXMAt2M5/hHcLreKJEioi7PMgXUkBFPbWU2JXj+5Nn//Q6Cx OHLbXlBEWPg7WzA8p77OGDkGmUU9JlirfhRUW+x3cZjOYvLLd4/r4jE+X3i5wo6v8ONT kVECzr921umTiMqLs/py5oq46z8DlF1VPNTHG7wxWaYZeVfZcfu+betQQYtYPs/4TWl/ MWv8eij6pRMvi8y6Qach/ZMgXCHcBRS6c0AtGgGhSwds6scYUUic2Z5eaALsQj4bVLSq m9yg== X-Gm-Message-State: AA+aEWYvJ0R/DKzMD0BbDtsYXWps2HjZohuwSAx9o/bkzmVm4U927TKw C8dFjkKTtfpfcvHQb+fB5luYXg== X-Received: by 2002:a1c:5dd1:: with SMTP id r200mr3487899wmb.93.1545408178072; Fri, 21 Dec 2018 08:02:58 -0800 (PST) Received: from boomer.local ([2a01:e34:eeb6:4690:106b:bae3:31ed:7561]) by smtp.googlemail.com with ESMTPSA id y138sm13044021wmc.16.2018.12.21.08.02.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 21 Dec 2018 08:02:57 -0800 (PST) From: Jerome Brunet To: Neil Armstrong , Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-clk@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 5/5] clk: meson: axg-ao: add 32k generation subtree Date: Fri, 21 Dec 2018 17:02:39 +0100 Message-Id: <20181221160239.26265-6-jbrunet@baylibre.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181221160239.26265-1-jbrunet@baylibre.com> References: <20181221160239.26265-1-jbrunet@baylibre.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the clock subtree generating the 32k clock in amlogic axg ao block. Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg-aoclk.c | 175 +++++++++++++++++++++++++++++++--- drivers/clk/meson/axg-aoclk.h | 13 +-- 2 files changed, 163 insertions(+), 25 deletions(-) -- 2.19.2 diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c index 29e088542387..5f518be144ce 100644 --- a/drivers/clk/meson/axg-aoclk.c +++ b/drivers/clk/meson/axg-aoclk.c @@ -12,10 +12,23 @@ #include #include #include -#include "clk-regmap.h" +#include "clkc.h" #include "meson-aoclk.h" #include "axg-aoclk.h" +/* + * AO Configuration Clock registers offsets + * Register offsets from the data sheet must be multiplied by 4. + */ +#define AO_RTI_PWR_CNTL_REG1 0x0C +#define AO_RTI_PWR_CNTL_REG0 0x10 +#define AO_RTI_GEN_CNTL_REG0 0x40 +#define AO_OSCIN_CNTL 0x58 +#define AO_CRT_CLK_CNTL1 0x68 +#define AO_SAR_CLK 0x90 +#define AO_RTC_ALT_CLK_CNTL0 0x94 +#define AO_RTC_ALT_CLK_CNTL1 0x98 + #define AXG_AO_GATE(_name, _bit) \ static struct clk_regmap axg_aoclk_##_name = { \ .data = &(struct clk_regmap_gate_data) { \ @@ -39,17 +52,141 @@ AXG_AO_GATE(uart2, 5); AXG_AO_GATE(ir_blaster, 6); AXG_AO_GATE(saradc, 7); +static struct clk_regmap axg_aoclk_cts_oscin = { + .data = &(struct clk_regmap_gate_data){ + .offset = AO_RTI_PWR_CNTL_REG0, + .bit_idx = 14, + }, + .hw.init = &(struct clk_init_data){ + .name = "cts_oscin", + .ops = &clk_regmap_gate_ro_ops, + .parent_names = (const char *[]){ "xtal" }, + .num_parents = 1, + }, +}; + +static struct clk_regmap axg_aoclk_32k_pre = { + .data = &(struct clk_regmap_gate_data){ + .offset = AO_RTC_ALT_CLK_CNTL0, + .bit_idx = 31, + }, + .hw.init = &(struct clk_init_data){ + .name = "axg_ao_32k_pre", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "cts_oscin" }, + .num_parents = 1, + }, +}; + +static const struct meson_clk_dualdiv_param axg_32k_div_table[] = { + { + .dual = 1, + .n1 = 733, + .m1 = 8, + .n2 = 732, + .m2 = 11, + }, {} +}; + +static struct clk_regmap axg_aoclk_32k_div = { + .data = &(struct meson_clk_dualdiv_data){ + .n1 = { + .reg_off = AO_RTC_ALT_CLK_CNTL0, + .shift = 0, + .width = 12, + }, + .n2 = { + .reg_off = AO_RTC_ALT_CLK_CNTL0, + .shift = 12, + .width = 12, + }, + .m1 = { + .reg_off = AO_RTC_ALT_CLK_CNTL1, + .shift = 0, + .width = 12, + }, + .m2 = { + .reg_off = AO_RTC_ALT_CLK_CNTL1, + .shift = 12, + .width = 12, + }, + .dual = { + .reg_off = AO_RTC_ALT_CLK_CNTL0, + .shift = 28, + .width = 1, + }, + .table = axg_32k_div_table, + }, + .hw.init = &(struct clk_init_data){ + .name = "axg_ao_32k_div", + .ops = &meson_clk_dualdiv_ops, + .parent_names = (const char *[]){ "axg_ao_32k_pre" }, + .num_parents = 1, + }, +}; + +static struct clk_regmap axg_aoclk_32k_sel = { + .data = &(struct clk_regmap_mux_data) { + .offset = AO_RTC_ALT_CLK_CNTL1, + .mask = 0x1, + .shift = 24, + .flags = CLK_MUX_ROUND_CLOSEST, + }, + .hw.init = &(struct clk_init_data){ + .name = "axg_ao_32k_sel", + .ops = &clk_regmap_mux_ops, + .parent_names = (const char *[]){ "axg_ao_32k_div", + "axg_ao_32k_pre" }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap axg_aoclk_32k = { + .data = &(struct clk_regmap_gate_data){ + .offset = AO_RTC_ALT_CLK_CNTL0, + .bit_idx = 30, + }, + .hw.init = &(struct clk_init_data){ + .name = "axg_ao_32k", + .ops = &clk_regmap_gate_ops, + .parent_names = (const char *[]){ "axg_ao_32k_sel" }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + }, +}; + +static struct clk_regmap axg_aoclk_cts_rtc_oscin = { + .data = &(struct clk_regmap_mux_data) { + .offset = AO_RTI_PWR_CNTL_REG0, + .mask = 0x1, + .shift = 10, + .flags = CLK_MUX_ROUND_CLOSEST, + }, + .hw.init = &(struct clk_init_data){ + .name = "axg_ao_cts_rtc_oscin", + .ops = &clk_regmap_mux_ops, + .parent_names = (const char *[]){ "axg_ao_32k", + "axg_ext_32k" }, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + }, +}; + static struct clk_regmap axg_aoclk_clk81 = { .data = &(struct clk_regmap_mux_data) { .offset = AO_RTI_PWR_CNTL_REG0, .mask = 0x1, .shift = 8, + .flags = CLK_MUX_ROUND_CLOSEST, }, .hw.init = &(struct clk_init_data){ .name = "axg_ao_clk81", .ops = &clk_regmap_mux_ro_ops, - .parent_names = (const char *[]){ "clk81", "ao_alt_xtal"}, + .parent_names = (const char *[]){ "clk81", + "axg_ao_cts_rtc_oscin"}, .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, }, }; @@ -106,17 +243,23 @@ static const unsigned int axg_aoclk_reset[] = { }; static struct clk_regmap *axg_aoclk_regmap[] = { - [CLKID_AO_REMOTE] = &axg_aoclk_remote, - [CLKID_AO_I2C_MASTER] = &axg_aoclk_i2c_master, - [CLKID_AO_I2C_SLAVE] = &axg_aoclk_i2c_slave, - [CLKID_AO_UART1] = &axg_aoclk_uart1, - [CLKID_AO_UART2] = &axg_aoclk_uart2, - [CLKID_AO_IR_BLASTER] = &axg_aoclk_ir_blaster, - [CLKID_AO_SAR_ADC] = &axg_aoclk_saradc, - [CLKID_AO_CLK81] = &axg_aoclk_clk81, - [CLKID_AO_SAR_ADC_SEL] = &axg_aoclk_saradc_mux, - [CLKID_AO_SAR_ADC_DIV] = &axg_aoclk_saradc_div, - [CLKID_AO_SAR_ADC_CLK] = &axg_aoclk_saradc_gate, + &axg_aoclk_remote, + &axg_aoclk_i2c_master, + &axg_aoclk_i2c_slave, + &axg_aoclk_uart1, + &axg_aoclk_uart2, + &axg_aoclk_ir_blaster, + &axg_aoclk_saradc, + &axg_aoclk_cts_oscin, + &axg_aoclk_32k_pre, + &axg_aoclk_32k_div, + &axg_aoclk_32k_sel, + &axg_aoclk_32k, + &axg_aoclk_cts_rtc_oscin, + &axg_aoclk_clk81, + &axg_aoclk_saradc_mux, + &axg_aoclk_saradc_div, + &axg_aoclk_saradc_gate, }; static const struct clk_hw_onecell_data axg_aoclk_onecell_data = { @@ -132,6 +275,12 @@ static const struct clk_hw_onecell_data axg_aoclk_onecell_data = { [CLKID_AO_SAR_ADC_SEL] = &axg_aoclk_saradc_mux.hw, [CLKID_AO_SAR_ADC_DIV] = &axg_aoclk_saradc_div.hw, [CLKID_AO_SAR_ADC_CLK] = &axg_aoclk_saradc_gate.hw, + [CLKID_AO_CTS_OSCIN] = &axg_aoclk_cts_oscin.hw, + [CLKID_AO_32K_PRE] = &axg_aoclk_32k_pre.hw, + [CLKID_AO_32K_DIV] = &axg_aoclk_32k_div.hw, + [CLKID_AO_32K_SEL] = &axg_aoclk_32k_sel.hw, + [CLKID_AO_32K] = &axg_aoclk_32k.hw, + [CLKID_AO_CTS_RTC_OSCIN] = &axg_aoclk_cts_rtc_oscin.hw, }, .num = NR_CLKS, }; diff --git a/drivers/clk/meson/axg-aoclk.h b/drivers/clk/meson/axg-aoclk.h index 91384d8dd844..3cc27e85170f 100644 --- a/drivers/clk/meson/axg-aoclk.h +++ b/drivers/clk/meson/axg-aoclk.h @@ -10,18 +10,7 @@ #ifndef __AXG_AOCLKC_H #define __AXG_AOCLKC_H -#define NR_CLKS 11 -/* AO Configuration Clock registers offsets - * Register offsets from the data sheet must be multiplied by 4. - */ -#define AO_RTI_PWR_CNTL_REG1 0x0C -#define AO_RTI_PWR_CNTL_REG0 0x10 -#define AO_RTI_GEN_CNTL_REG0 0x40 -#define AO_OSCIN_CNTL 0x58 -#define AO_CRT_CLK_CNTL1 0x68 -#define AO_SAR_CLK 0x90 -#define AO_RTC_ALT_CLK_CNTL0 0x94 -#define AO_RTC_ALT_CLK_CNTL1 0x98 +#define NR_CLKS 17 #include #include