From patchwork Sat Apr 30 13:09:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 568293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CCB4C433F5 for ; Sat, 30 Apr 2022 13:13:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382701AbiD3NQX (ORCPT ); Sat, 30 Apr 2022 09:16:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382691AbiD3NQU (ORCPT ); Sat, 30 Apr 2022 09:16:20 -0400 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BE95C7DE1A for ; Sat, 30 Apr 2022 06:12:57 -0700 (PDT) Received: by mail-wm1-x32f.google.com with SMTP id n126-20020a1c2784000000b0038e8af3e788so6150740wmn.1 for ; Sat, 30 Apr 2022 06:12:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod-ie.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U51TZQhHKAPu6F0ygHwpPoWdzkMjxCa4kGnNd6Hzk/o=; b=b0NKL9VwC3e8+DspbbgveqAFU8bLQvyX69E9r037zGadc4FwpXgqITKvvl+0SX57Ju iyd2yvK458NMGSY35dGv+++xES/M1jS4JlNfGizyR4RATqiId3ETfHip/UjmZYM01zIq ZUALlaJYdOdy0lFYEeOz7P1F34Z23Fh8y8AgDcP1xtsLq3h3SDRmczx02MN+TIKrhcr8 Zr3jtMzfpdO3CE6ZQO5CrsRbsJ2N7pRxDf7S48XXzKPKusBmNKR2NPAwiwZ9vochTqjP +4W3DBHd/+HWnJhjnMlk/89d1UXC9fF29oBpkmilBYu2uYeiHS/VI6wFnvTepFO2KT6g 6c0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U51TZQhHKAPu6F0ygHwpPoWdzkMjxCa4kGnNd6Hzk/o=; b=7FbbO/UFi6lIlT8nVgDtfpwK5yknZH4vwfeZvMTmV9V/iNwA7fW1DE1cb8PPQM8Zf7 GLA3rOaGn8XhgwIFU+Aw3GGBMaY3HYh/BsPOL9Uipnmy0rdVFEwhUQK0cma5nZi0+7gK l4yrEJijeC/nd2UkVJGBC+k1ZJBYzj1TZzZSatFrvS4Zrgwnwr+/OAPLsA6IwlRq85O9 KnCFYCAWOFBcEjDPZ2xoLlrZ261FIqDoutQEgp9SYQjvaeREeS5ggTNh8tMMpqdPbHnb n7DMFtpE/7Ybw3adxqD8nz0hteBN14aIQIuki1VjQ1T9p/awqexaEXC3IInc9mYMzcfa vWIQ== X-Gm-Message-State: AOAM530TgSoZgPiuRa4LiRcE0n37SAElpq5cIUgzscAfpYYxPrrH61fV RPvOUVwZH4MyTZTreUd/SpOAOQ== X-Google-Smtp-Source: ABdhPJyhZkGAtnEZF26eRlmNAzd28Gd/+hWFcNPXa+U5piOfk+rl/XVZsDmWUL3JznznT7nfvKwsSw== X-Received: by 2002:a1c:f018:0:b0:37b:c13c:3128 with SMTP id a24-20020a1cf018000000b0037bc13c3128mr7518375wmb.157.1651324376333; Sat, 30 Apr 2022 06:12:56 -0700 (PDT) Received: from henark71.. ([109.77.36.132]) by smtp.gmail.com with ESMTPSA id p9-20020adfa209000000b0020c5253d8ebsm2004439wra.55.2022.04.30.06.12.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 06:12:55 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley Subject: [PATCH v2 3/8] riscv: dts: microchip: remove soc vendor from filenames Date: Sat, 30 Apr 2022 14:09:18 +0100 Message-Id: <20220430130922.3504268-4-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220430130922.3504268-1-mail@conchuod.ie> References: <20220430130922.3504268-1-mail@conchuod.ie> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Having the SoC vendor both as the directory and in the filename adds little. Remove microchip from the filenames so that the files will resemble the other directories in riscv (and arm64). The new names follow a soc-board.dts & soc{,-fabric}.dtsi pattern. Signed-off-by: Conor Dooley Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/Makefile | 2 +- .../microchip/{microchip-mpfs-fabric.dtsi => mpfs-fabric.dtsi} | 0 .../{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} | 2 +- .../riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} | 2 +- 4 files changed, 3 insertions(+), 3 deletions(-) rename arch/riscv/boot/dts/microchip/{microchip-mpfs-fabric.dtsi => mpfs-fabric.dtsi} (100%) rename arch/riscv/boot/dts/microchip/{microchip-mpfs-icicle-kit.dts => mpfs-icicle-kit.dts} (98%) rename arch/riscv/boot/dts/microchip/{microchip-mpfs.dtsi => mpfs.dtsi} (99%) diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile index 855c1502d912..af3a5059b350 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi similarity index 100% rename from arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi rename to arch/riscv/boot/dts/microchip/mpfs-fabric.dtsi diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts similarity index 98% rename from arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts rename to arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts index c71d6aa6137a..84b0015dfd47 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -3,7 +3,7 @@ /dts-v1/; -#include "microchip-mpfs.dtsi" +#include "mpfs.dtsi" /* Clock frequency (in Hz) of the rtcclk */ #define RTCCLK_FREQ 1000000 diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi similarity index 99% rename from arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi rename to arch/riscv/boot/dts/microchip/mpfs.dtsi index bf21a2edd180..cc3386068c2d 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -3,7 +3,7 @@ /dts-v1/; #include "dt-bindings/clock/microchip,mpfs-clock.h" -#include "microchip-mpfs-fabric.dtsi" +#include "mpfs-fabric.dtsi" / { #address-cells = <2>; From patchwork Sat Apr 30 13:09:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 568292 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E949BC433FE for ; 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([109.77.36.132]) by smtp.gmail.com with ESMTPSA id p9-20020adfa209000000b0020c5253d8ebsm2004439wra.55.2022.04.30.06.12.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 06:13:00 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley Subject: [PATCH v2 7/8] dt-bindings: riscv: microchip: add polarberry compatible string Date: Sat, 30 Apr 2022 14:09:22 +0100 Message-Id: <20220430130922.3504268-8-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220430130922.3504268-1-mail@conchuod.ie> References: <20220430130922.3504268-1-mail@conchuod.ie> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Add a binding for the Sundance Polarberry board. Signed-off-by: Conor Dooley Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/microchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index c9d8fcc7a69e..7f9296991a56 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -21,6 +21,7 @@ properties: - items: - enum: - microchip,mpfs-icicle-kit + - sundance,polarberry - const: microchip,mpfs - items: - const: microchip,mpfs-icicle-reference-rtlv2203 From patchwork Sat Apr 30 13:09:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 568291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B4A4C433F5 for ; Sat, 30 Apr 2022 13:13:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1382707AbiD3NQ0 (ORCPT ); Sat, 30 Apr 2022 09:16:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382712AbiD3NQZ (ORCPT ); Sat, 30 Apr 2022 09:16:25 -0400 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AE0757E5B1 for ; Sat, 30 Apr 2022 06:13:03 -0700 (PDT) Received: by mail-wr1-x42d.google.com with SMTP id c11so4219129wrn.8 for ; Sat, 30 Apr 2022 06:13:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=conchuod-ie.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5BDpWQnhgIgr6un23nDrSpiOtZvz8Bid/I/OR7bUXBg=; b=SlG01VQDuxSxdPy8VMdSmhznbCqvszukWiPbnb3FyMJXyipQCen4pPNN94SZggFHBR Khv8/STbGnjHar2BvWcMavvK+nWHNx4/vLDyhSmKF1w724sCgNYYjRtvGQEwbJnjRTnI SsCBr2A7+YyYPewKZbXskdXlem0Tx0wsiuw0sTypY8DTgT8EJBv4p9x1e8jA5Gfnv02n YJkDQH5oaeAP9EjFiV4q4h3/aZgXkSeR+WJ8b1+dsG8AI3hq2n081ke8V2vUU6UX3Evk bcIsgmakIN3lF27zSgQVwm4S1yL2dE9uKV+ImcWStQjPfAsY4OfloiF484vCfyGRcmmN 27hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5BDpWQnhgIgr6un23nDrSpiOtZvz8Bid/I/OR7bUXBg=; b=2T1Px2Bo1QoieLIqNW4UXyDkbrp+CVSzWeLspvvxPeC31igoq74Mhd5q0CzB1SJF02 tNPs4UYhI1AKVsVFG7tG29LThRgoZRe0+7zFngV9EuxGRLIT2NSR68rXI/uOOdczZH4n U3F4dY5umYsvYX3mp531Uk22vLRuVvOHcbbnB/foIaJKA6RYxL5bJcB/X5nvoa9znOWl YQYkfTR9sBUy2sB0OD2ZU9QgrxeaZEN07Ya3YNrVc87qGQsYazTN9bxMdE0HdOeDMDaf ObYa4p9h83kGF4OLWAEpjMTzBxirOp6Q+38kIz+TbDnpx+J36ES7ntgsmnLiv/4N8VtW OwMA== X-Gm-Message-State: AOAM533HagWW4/YO0c6UL8AhmFJy6SbrcyX9YNfOlzyRgZG+SzpnlJ5N ZXoEvYISGoWWmmMhZzJzdNnaZA== X-Google-Smtp-Source: ABdhPJzGWomTAcKYy8TjYtr6rv50Fq2fu7zj7OZUjLU0Hb9oHeoK5Z30y35gwYrn24hopjf/OilbsA== X-Received: by 2002:a05:6000:1689:b0:20c:4fa1:ffb7 with SMTP id y9-20020a056000168900b0020c4fa1ffb7mr3111374wrd.48.1651324382219; Sat, 30 Apr 2022 06:13:02 -0700 (PDT) Received: from henark71.. ([109.77.36.132]) by smtp.gmail.com with ESMTPSA id p9-20020adfa209000000b0020c5253d8ebsm2004439wra.55.2022.04.30.06.13.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 06:13:01 -0700 (PDT) From: Conor Dooley To: krzk+dt@kernel.org, palmer@dabbelt.com, robh+dt@kernel.org Cc: conor.dooley@microchip.com, Cyril.Jean@microchip.com, daire.mcnamara@microchip.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, palmer@rivosinc.com, arnd@arndb.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley Subject: [PATCH v2 8/8] riscv: dts: microchip: add the sundance polarberry Date: Sat, 30 Apr 2022 14:09:23 +0100 Message-Id: <20220430130922.3504268-9-mail@conchuod.ie> X-Mailer: git-send-email 2.36.0 In-Reply-To: <20220430130922.3504268-1-mail@conchuod.ie> References: <20220430130922.3504268-1-mail@conchuod.ie> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Add a minimal device tree for the PolarFire SoC based Sundance PolarBerry. Signed-off-by: Conor Dooley Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/Makefile | 1 + .../dts/microchip/mpfs-polarberry-fabric.dtsi | 16 ++++ .../boot/dts/microchip/mpfs-polarberry.dts | 95 +++++++++++++++++++ 3 files changed, 112 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-polarberry.dts diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile index af3a5059b350..39aae7b04f1c 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi new file mode 100644 index 000000000000..49380c428ec9 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2022 Microchip Technology Inc */ + +/ { + fabric_clk3: fabric-clk3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <62500000>; + }; + + fabric_clk1: fabric-clk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts new file mode 100644 index 000000000000..96ec589d1571 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2022 Microchip Technology Inc */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-polarberry-fabric.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define MTIMER_FREQ 1000000 + +/ { + model = "Sundance PolarBerry"; + compatible = "sundance,polarberry", "microchip,mpfs"; + + aliases { + serial0 = &mmuart0; + ethernet0 = &mac1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + timebase-frequency = ; + }; + + ddrc_cache_lo: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x2e000000>; + status = "okay"; + }; + + ddrc_cache_hi: memory@1000000000 { + device_type = "memory"; + reg = <0x10 0x00000000 0x0 0xC0000000>; + status = "okay"; + }; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&mmuart0 { + status = "okay"; +}; + +&mmc { + status = "okay"; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + card-detect-delay = <200>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +}; + +&mac1 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&phy1>; + phy1: ethernet-phy@5 { + reg = <5>; + ti,fifo-depth = <0x01>; + }; + phy0: ethernet-phy@4 { + reg = <4>; + ti,fifo-depth = <0x01>; + }; +}; + +&mac0 { + status = "disabled"; + phy-mode = "sgmii"; + phy-handle = <&phy0>; +}; + +&rtc { + status = "okay"; +}; + +&mbox { + status = "okay"; +}; + +&syscontroller { + status = "okay"; +};