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Fri, 21 Dec 2018 14:32:50 +0000 (GMT) X-AuditID: cbfec7f2-5e3ff70000001159-ef-5c1cf9928643 Received: from eusync4.samsung.com ( [203.254.199.214]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 66.AC.04128.199FC1C5; Fri, 21 Dec 2018 14:32:49 +0000 (GMT) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0PK3006BBCEKWR10@eusync4.samsung.com>; Fri, 21 Dec 2018 14:32:49 +0000 (GMT) From: Marek Szyprowski To: linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Beomho Seo , Seung-Woo Kim , Sylwester Nawrocki , Lee Jones , Greg Kroah-Hartman Subject: [PATCH v2 1/4] mfd: exynos-lpass: Enable UART module support Date: Fri, 21 Dec 2018 15:32:28 +0100 Message-id: <20181221143228.934-1-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-reply-to: <20181221103907.GK13248@dell> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrLIsWRmVeSWpSXmKPExsWy7djP87qTfsrEGEzdZmOxccZ6VovTn7ax WzQvXs9mcf78BnaL+1+PMlpc3jWHzWLG+X1MFmcW97JbrD1yl93i8Jt2VosZk1+yOXB7bFrV yeZx59oeNo/9c9ewe/RtWcXo8XmTXABrFJdNSmpOZllqkb5dAlfG8c1H2AvW81b0rrnH2MC4 kruLkZNDQsBEYumHlWxdjFwcQgIrGCUm7jvDDuF8ZpToPf6TsYuRA6xqwX9NkAYhgWWMEiuO GUPUNDBJzHi5ggkkwSZgKNH1tosNxBYRSJZ4NvcII0gRs8BDJomOi99YQBLCAq4Ss84uZQWx WQRUJVbt6QRr4BWwljhx+Tg7xEnyEqs3HGAGsTkFtCR+dpxnBRkkIbCCTeL/+n9sEEUuEv+O XWGBsIUlXh3fAtUsI3F5cjcLREMzo0T7jFnsEE4Po8TWOTuguq0lDh+/CHYGswCfxKRt05kh /uSV6GgTgijxkPjbdYEF4udaibPPu1gnMEouYGRYxSieWlqcm55abJiXWq5XnJhbXJqXrpec n7uJERipp/8d/7SD8eulpEOMAhyMSjy8E77JxAixJpYVV+YeYpTgYFYS4e2wBQrxpiRWVqUW 5ccXleakFh9ilOZgURLnrWZ4EC0kkJ5YkpqdmlqQWgSTZeLglGpg9LOK3lBu+ZbFxN75BvPN t0dStbK3K+b8bP393jv1vb7q83znRSJmT3zSdVuu7r/QYNAbHrAuIyk2rUrk+KcN6t9EDdfV 7ViRsnPxXdur+TuPsdt7TkhvqK/neMdv9/WP+ab7s0o1wics4nPPOPtO1lLr37Qq47kFbdwW 4Soxv1y9zsWdFNunxFKckWioxVxUnAgAGmlgy9ACAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprFLMWRmVeSWpSXmKPExsVy+t/xa7oTf8rEGOybYmWxccZ6VovTn7ax WzQvXs9mcf78BnaL+1+PMlpc3jWHzWLG+X1MFmcW97JbrD1yl93i8Jt2VosZk1+yOXB7bFrV yeZx59oeNo/9c9ewe/RtWcXo8XmTXABrFJdNSmpOZllqkb5dAlfG8c1H2AvW81b0rrnH2MC4 kruLkYNDQsBEYsF/zS5GLg4hgSWMErffXWeGcJqYJBovHmTpYuTkYBMwlOh628UGYosIJEvs +vuCFaSIWeAxk8SUlhdgRcICrhKzzi5lBbFZBFQlVu3pBGvgFbCWOHH5ODuILSEgL7F6wwFm EJtTQEviZ8d5VpArhAQ0Jb585prAyLOAkWEVo0hqaXFuem6xkV5xYm5xaV66XnJ+7iZGYIht O/Zzyw7GrnfBhxgFOBiVeHgnfJOJEWJNLCuuzD3EKMHBrCTC22ELFOJNSaysSi3Kjy8qzUkt PsQozcGiJM573qAySkggPbEkNTs1tSC1CCbLxMEp1cCYaC4tPMv78CPOlmpRyeCbL+s7H+R9 37TE6YKk4KY3HC7xf3jePNFq/qpxspfx43Xta4c3eTzii2mTKFZPDcnt9ZquZK7FfiM2vffy wm/Nh24VXrDwv+OlkT9j7t7LB7xbTrF9UupdzCPCwePb2cMrVtXQpm3a+NXx6TTtiFNu++21 you+rldiKc5INNRiLipOBAB5jaCRLQIAAA== X-CMS-MailID: 20181221143250eucas1p120b2d4dbcb990c5893e0fa4c6a7dd861 X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20181221143250eucas1p120b2d4dbcb990c5893e0fa4c6a7dd861 References: <20181221103907.GK13248@dell> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org From: Beomho Seo This patch enables proper interrupts routing between UART module in Exynos Audio SubSystem and the rest of the SoC. This routing is completely transparent for UART device and CPU/GIC. UART driver requests interrupts from the respective controller and enables/masks/handles it by itself via standard methods. There are boards (for example TM2), which use UART module in Exynos Audio SubStem for communication with BlueTooth chip. Signed-off-by: Beomho Seo [mszyprow: rephrased commit message, added UART reset] Signed-off-by: Marek Szyprowski Reviewed-by: Sylwester Nawrocki --- Changelog v2: - rephrased and extended commit message --- drivers/mfd/exynos-lpass.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c index ca829f85672f..2713de989f05 100644 --- a/drivers/mfd/exynos-lpass.c +++ b/drivers/mfd/exynos-lpass.c @@ -82,11 +82,13 @@ static void exynos_lpass_enable(struct exynos_lpass *lpass) LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S); regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, - LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S); + LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S | + LPASS_INTR_UART); exynos_lpass_core_sw_reset(lpass, LPASS_I2S_SW_RESET); exynos_lpass_core_sw_reset(lpass, LPASS_DMA_SW_RESET); exynos_lpass_core_sw_reset(lpass, LPASS_MEM_SW_RESET); + exynos_lpass_core_sw_reset(lpass, LPASS_UART_SW_RESET); } static void exynos_lpass_disable(struct exynos_lpass *lpass)