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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id 5-20020a170902c20500b0015e8d4eb282sm1740910pll.204.2022.04.30.10.53.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 10:53:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 01/17] target/m68k: Raise the TRAPn exception with the correct pc Date: Sat, 30 Apr 2022 10:53:26 -0700 Message-Id: <20220430175342.370628-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220430175342.370628-1-richard.henderson@linaro.org> References: <20220430175342.370628-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Rather than adjust the PC in all of the consumers, raise the exception with the correct PC in the first place. Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- linux-user/m68k/cpu_loop.c | 1 - target/m68k/op_helper.c | 9 --------- target/m68k/translate.c | 2 +- 3 files changed, 1 insertion(+), 11 deletions(-) diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index d1bf8548b7..56417f7401 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -56,7 +56,6 @@ void cpu_loop(CPUM68KState *env) { abi_long ret; n = env->dregs[0]; - env->pc += 2; ret = do_syscall(env, n, env->dregs[1], diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 8decc61240..d30f988ae0 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -217,11 +217,6 @@ static void cf_interrupt_all(CPUM68KState *env, int is_hw) cpu_loop_exit(cs); return; } - if (cs->exception_index >= EXCP_TRAP0 - && cs->exception_index <= EXCP_TRAP15) { - /* Move the PC after the trap instruction. */ - retaddr += 2; - } } vector = cs->exception_index << 2; @@ -304,10 +299,6 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) /* Return from an exception. */ m68k_rte(env); return; - case EXCP_TRAP0 ... EXCP_TRAP15: - /* Move the PC after the trap instruction. */ - retaddr += 2; - break; } } diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 4026572ed8..6d6d026e3c 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4860,7 +4860,7 @@ DISAS_INSN(wdebug) DISAS_INSN(trap) { - gen_exception(s, s->base.pc_next, EXCP_TRAP0 + (insn & 0xf)); + gen_exception(s, s->pc, EXCP_TRAP0 + (insn & 0xf)); } static void gen_load_fcr(DisasContext *s, TCGv res, int reg) From patchwork Sat Apr 30 17:53:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 568148 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp7371318map; Sat, 30 Apr 2022 10:59:05 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyYkeoydGCFlvs8Ci7wFTPF0yll9oex9eF6IbMGNv+an8CeoYY924zZE/5dh2AwFNduE+bz X-Received: by 2002:ae9:ee09:0:b0:69f:5b81:f544 with SMTP id i9-20020ae9ee09000000b0069f5b81f544mr3356744qkg.641.1651341545189; Sat, 30 Apr 2022 10:59:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1651341545; cv=none; d=google.com; s=arc-20160816; b=dDXpGz746haztMKf0nJn3uCVFjtk9NAl78xG3rHNgZzuft9qHboEGsjrXspGiJboPZ NAYv6aNAPKgvcCNbVRH765bwyv5ND6yZhKSFORhPIt1waXFJZvoiGlF3ig9T4LK2kpxB ZFKW5J5QMk5a7dzdG2Sa6H4kcr5FpBHTiLCYDzIo4UXTufPbKEisndLbSFyDiFH+Duib Rt/va1LJIwY2ic3JXKHIT4sC9vLhPZm7Qt6N6ixb3CnWZDGceUOwSCLkNo6DlReJF7BW 9D3VLeiN+ciDuNwVBEAEFHJVAo4K9cizNER9MRUxdqaK6yAAmQnXjt2/s5KXHqYtaH2q IyPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hV+IA21ry8VojR25e1IAEE42j7p287jopA93G1Fi9U8=; b=WdyTuRNk1VC55UtCAu0qgp5mDUKKap1ZltuM208WSEDtPSQ2Nyv+fA2ihxadLSenUQ AfgeRjGM/fD6kcGnlbb24TMy77lA/7ewZGk4Y+LPMMpun0U+NpUMnf2EjoEZiQOsZuhF ilA1ZNp3Ftl8jBSRzIUM/hBaFiqej53AYFOLGCRO40CUhXOhd6ENeQFGGtNe+sFJ3NhZ +dX6zpA1/P6uRg2+3IUbOSkBmSWJaKlNfBAWedPiEcl2NLn7vHepbCzkjDsGfRaxtZtP P9/1refuQxe8GV0mtqciCP+G9/ylmWWnD78iN2Cw7S9l/GbwxqQNmNrxBkL4c3feXWO5 ksjQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ASrKMOiC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id 5-20020a170902c20500b0015e8d4eb282sm1740910pll.204.2022.04.30.10.53.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 10:53:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 02/17] target/m68k: Switch over exception type in m68k_interrupt_all Date: Sat, 30 Apr 2022 10:53:27 -0700 Message-Id: <20220430175342.370628-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220430175342.370628-1-richard.henderson@linaro.org> References: <20220430175342.370628-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Replace an if ladder with a switch for clarity. Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/m68k/op_helper.c | 49 +++++++++++++++++++++++++---------------- 1 file changed, 30 insertions(+), 19 deletions(-) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index d30f988ae0..2b94a6ec84 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -333,7 +333,8 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) sp &= ~1; } - if (cs->exception_index == EXCP_ACCESS) { + switch (cs->exception_index) { + case EXCP_ACCESS: if (env->mmu.fault) { cpu_abort(cs, "DOUBLE MMU FAULT\n"); } @@ -391,29 +392,39 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) "ssw: %08x ea: %08x sfc: %d dfc: %d\n", env->mmu.ssw, env->mmu.ar, env->sfc, env->dfc); } - } else if (cs->exception_index == EXCP_ADDRESS) { + break; + + case EXCP_ADDRESS: do_stack_frame(env, &sp, 2, oldsr, 0, retaddr); - } else if (cs->exception_index == EXCP_ILLEGAL || - cs->exception_index == EXCP_DIV0 || - cs->exception_index == EXCP_CHK || - cs->exception_index == EXCP_TRAPCC || - cs->exception_index == EXCP_TRACE) { + break; + + case EXCP_ILLEGAL: + case EXCP_DIV0: + case EXCP_CHK: + case EXCP_TRAPCC: + case EXCP_TRACE: /* FIXME: addr is not only env->pc */ do_stack_frame(env, &sp, 2, oldsr, env->pc, retaddr); - } else if (is_hw && oldsr & SR_M && - cs->exception_index >= EXCP_SPURIOUS && - cs->exception_index <= EXCP_INT_LEVEL_7) { - do_stack_frame(env, &sp, 0, oldsr, 0, retaddr); - oldsr = sr; - env->aregs[7] = sp; - cpu_m68k_set_sr(env, sr &= ~SR_M); - sp = env->aregs[7]; - if (!m68k_feature(env, M68K_FEATURE_UNALIGNED_DATA)) { - sp &= ~1; + break; + + case EXCP_SPURIOUS ... EXCP_INT_LEVEL_7: + if (is_hw && oldsr & SR_M) { + do_stack_frame(env, &sp, 0, oldsr, 0, retaddr); + oldsr = sr; + env->aregs[7] = sp; + cpu_m68k_set_sr(env, sr &= ~SR_M); + sp = env->aregs[7]; + if (!m68k_feature(env, M68K_FEATURE_UNALIGNED_DATA)) { + sp &= ~1; + } + do_stack_frame(env, &sp, 1, oldsr, 0, retaddr); + break; } - do_stack_frame(env, &sp, 1, oldsr, 0, retaddr); - } else { + /* fall through */ + + default: do_stack_frame(env, &sp, 0, oldsr, 0, retaddr); + break; } env->aregs[7] = sp; From patchwork Sat Apr 30 17:53:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 568145 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp7369515map; Sat, 30 Apr 2022 10:55:03 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzSuRLkouLt60Ku3rmXnti8gxz+o0lcSTUn3uvWVlxktLd+aGTMYlKxdugD1t0xmCpS4lmF X-Received: by 2002:a05:620a:1250:b0:69e:c3f9:b18c with SMTP id a16-20020a05620a125000b0069ec3f9b18cmr3393979qkl.753.1651341302996; Sat, 30 Apr 2022 10:55:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1651341302; cv=none; d=google.com; s=arc-20160816; b=mvIdny8tH0Rj432glPLryCMyStIFxBtjKtEwz2xt6pzCCe0oj8XZ23/LvnONhqfrrR EucFCFtVmqxNQcccxQUteyxFaGRSOzoOaWgIogyIThVyYwxsver0/Jcun0axP8bgRlgh z5a4o95h90aJ6Tr3DcfwoBm/EIJx28OMh9Abo15h6ScQKTaKeDqQlqx9RXWbiCJce6EF /enO7fbaDO9C49sGEJPLzle5jqB4TK478LHrhpoOZ7KtvvK69E1GFNdDkh++PNmCbR9W i2ID8b51QlU659JxiAZEccTXMUco75ApmT7X9gYnRutO0o7EoxhsJ8F1ibBw4E13R+dL B55Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=3NUt6cycfWH/ENZGNIvXT39oA5d9WYzXAuV4uBUZ0DU=; b=DeOLHssGMyLePTCDF0x0GRnu5J8uLv3zXOpmDfiTOYgeoYzoF6Q1yb4hdBGUDv1hk6 97Yth87QBDjem6aGkKuWil7As4rVwIPqKldqiTg0gOji5VkAYCFSO4EpiWgmeYLycmNr GbvSKwpl4z9tPvWmG9Er05wT51fo+hIMERi0d+vpPbI9Ycc9vhOCZJ8jtwxnA2AinDvP pkqDiNEiF/TNhE6im7fRTUPP9dfX5dD40kKqiyVvy14DD632NugquopBv8iF8Ik5nXTQ TKCzYD5DrzizYtlgSNnwS0+8QXWxDaId8S5EW104gFqwlPET1qIkWAH2UQXOkVZ5Nb81 2ZVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E7yw6I8z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id 5-20020a170902c20500b0015e8d4eb282sm1740910pll.204.2022.04.30.10.53.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 10:53:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 03/17] target/m68k: Fix coding style in m68k_interrupt_all Date: Sat, 30 Apr 2022 10:53:28 -0700 Message-Id: <20220430175342.370628-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220430175342.370628-1-richard.henderson@linaro.org> References: <20220430175342.370628-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add parenthesis around & vs &&. Remove assignment to sr in function call argument -- note that sr is unused after the call, so the assignment was never needed, only the result of the & expression. Suggested-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier --- target/m68k/op_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 2b94a6ec84..0f41c2dce3 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -408,11 +408,11 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) break; case EXCP_SPURIOUS ... EXCP_INT_LEVEL_7: - if (is_hw && oldsr & SR_M) { + if (is_hw && (oldsr & SR_M)) { do_stack_frame(env, &sp, 0, oldsr, 0, retaddr); oldsr = sr; env->aregs[7] = sp; - cpu_m68k_set_sr(env, sr &= ~SR_M); + cpu_m68k_set_sr(env, sr & ~SR_M); sp = env->aregs[7]; if (!m68k_feature(env, M68K_FEATURE_UNALIGNED_DATA)) { sp &= ~1; From patchwork Sat Apr 30 17:53:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 568146 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp7369529map; Sat, 30 Apr 2022 10:55:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJymksWK+dbygSZ68omtoJXn/OtT9c1PptzRnd9AvPLtI39tRRFxgKn6ie6+2oKdLVeFmnnI X-Received: by 2002:ac8:7c54:0:b0:2f3:6fd1:ff92 with SMTP id o20-20020ac87c54000000b002f36fd1ff92mr4316163qtv.312.1651341304555; Sat, 30 Apr 2022 10:55:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1651341304; cv=none; d=google.com; s=arc-20160816; b=ukOs5yIywxEwmApoBqN16q7U0b0BOx3l+BNLN2eqYGRh7h8zHXommWDHeLXAgjvh3g etjePHA/NZU/UCxqjgxA7a8K/s5TA+Iy04+h0YatnMTbLmWI9OxOGxClvKfEsxeRMqy/ BHGHU6DuyOFwj69eL2O1whoKP4tZhI31bnqW3yrCu/yJ5I8yCICQwEm48qujHWrhKTrO 0i/XE1LY+wPYcVeDEHkdVK+PfETvPzLUai9rcU4Dt4W1EzH+K+efcRFWXnj2GK0qlpTO fK8/tTkNRY8Uom1wKcbOjNb2Pqta4W9fFgb8emgkog/WKmhZDDrjg0y+7z5dRY114yJb S2VA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1b49PBr+T1730mSFSrp1OrknmNb0ysNKYnsC6xH7ni4=; b=RwwfwzH2YQtqpE9bAqQvN7ZWalM3ldgYg9hTjimTEN1nHHakkZIdTELjOpWop04PSY AU1pff9CNVv8cMithOUjNYdTrBFHmBq9TQgEYAlSyFusON02OVLco7unM7MeIFnxKBj8 jmzYWOz/QyjGqPrC0j7GGwOTt3CchQmos2boR8w6VZWtjZREos4NashXrQLVKTuHDr2H pdKUfzASQgZGkldWJywWYwCfvMeYD3Kra1W8bY6k3O4mU24jsyfhb7++Q/70bTU46yVL Ey+kaA1g3N4IghkYGui43MbA+TUa2Om8H0Gq5WdLRF3UpE18W39y75AZ3IZ6VogIf/ea Lp9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="cojVkoZ/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id 5-20020a170902c20500b0015e8d4eb282sm1740910pll.204.2022.04.30.10.53.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 10:53:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 04/17] linux-user/m68k: Handle EXCP_TRAP1 through EXCP_TRAP15 Date: Sat, 30 Apr 2022 10:53:29 -0700 Message-Id: <20220430175342.370628-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220430175342.370628-1-richard.henderson@linaro.org> References: <20220430175342.370628-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These are raised by guest instructions, and should not fall through into the default abort case. Signed-off-by: Richard Henderson --- linux-user/m68k/cpu_loop.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index 56417f7401..6ca3e1e63a 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -44,6 +44,7 @@ void cpu_loop(CPUM68KState *env) case EXCP_ILLEGAL: case EXCP_LINEA: case EXCP_LINEF: + case EXCP_TRAP0 + 1 ... EXCP_TRAP0 + 14: force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc); break; case EXCP_CHK: @@ -76,6 +77,7 @@ void cpu_loop(CPUM68KState *env) /* just indicate that signals should be handled asap */ break; case EXCP_DEBUG: + case EXCP_TRAP15: force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc); break; case EXCP_ATOMIC: From patchwork Sat Apr 30 17:53:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 568147 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp7371312map; Sat, 30 Apr 2022 10:59:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzxzA7ZLQcNmXkqOF1VLIiaWI+8tSYBxq79yfb1l4YpfZwPuIy8LGeK+dvDwHSIMaWchIKk X-Received: by 2002:a05:620a:2805:b0:67d:5c7e:c43a with SMTP id f5-20020a05620a280500b0067d5c7ec43amr3511112qkp.84.1651341543897; Sat, 30 Apr 2022 10:59:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1651341543; cv=none; d=google.com; s=arc-20160816; b=IOmtx9CIBaLe3Ea9QU88m3beUjxSRAg+3GDo88PD7wmD5/CfMwTMkGKpqgxdtAvgPb wyJ8Q6ieE0IAFhVa3q+KjB7wRiTnNh2sMqYv//bmtPlZS8359Fgu6xhv0AP951Jlr+vd Ok6wEQQhL8wdwTRCe2vdfvCGOnwSW2koxNu71uPpngvWAe3iL7B4Vfc2FM87Mbkl+rxu gMnu+GdhWN7Bjk5nSd/lu5z95STop9m2nwpzsV02/toTPhOi3cuYrv1DdQwaIfxIpCGW p91Yw+KBi/5bpwpqohEDhUbsZlQibSJWKRD8LDak4fwE+JxwFhlX39XoKJvO6/zX9UdT fopA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=dBQmcYvQNWemNoz94qCXnnbynO5dcM+A32yDVQduyko=; b=jGFTYVj3U5Mb/KGZurviS/mSSRIYiKKASj9MdPpOBWTLwUu6sGWgd0z27BON7qna3F uirN5MGh/Y+s3z24Pa4ECNI53PKzEeE/Gbl6wOwqWCzMu548eHO7AyAMYeprB3WdDms8 8AP/7V7FteORs+RYlV2lMJp8N/zKqNqEaunlrdfBlMeUlIYEBva6NNh/RP7nbuPpGmqI CKFjjvL1V0qm9y9SOIZcirvrSdbr8u4lrRHjuiFScJGeJ2wO1K8mibNqtd8QRsPmNi2M vDTt+HMuIMHb/53MD05CKqF2z0c04mdutkuLqoOlEF8y2qIJZsRGWt/w90JdAWBmyPd/ SiYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PY+NS7nA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id 5-20020a170902c20500b0015e8d4eb282sm1740910pll.204.2022.04.30.10.53.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 10:53:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 05/17] target/m68k: Remove retaddr in m68k_interrupt_all Date: Sat, 30 Apr 2022 10:53:30 -0700 Message-Id: <20220430175342.370628-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220430175342.370628-1-richard.henderson@linaro.org> References: <20220430175342.370628-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The only value this variable holds is now env->pc. Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/m68k/op_helper.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 0f41c2dce3..777869790b 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -287,12 +287,9 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) { CPUState *cs = env_cpu(env); uint32_t sp; - uint32_t retaddr; uint32_t vector; uint16_t sr, oldsr; - retaddr = env->pc; - if (!is_hw) { switch (cs->exception_index) { case EXCP_RTE: @@ -385,7 +382,7 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) sp -= 4; cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0); - do_stack_frame(env, &sp, 7, oldsr, 0, retaddr); + do_stack_frame(env, &sp, 7, oldsr, 0, env->pc); env->mmu.fault = false; if (qemu_loglevel_mask(CPU_LOG_INT)) { qemu_log(" " @@ -395,7 +392,7 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) break; case EXCP_ADDRESS: - do_stack_frame(env, &sp, 2, oldsr, 0, retaddr); + do_stack_frame(env, &sp, 2, oldsr, 0, env->pc); break; case EXCP_ILLEGAL: @@ -404,12 +401,12 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) case EXCP_TRAPCC: case EXCP_TRACE: /* FIXME: addr is not only env->pc */ - do_stack_frame(env, &sp, 2, oldsr, env->pc, retaddr); + do_stack_frame(env, &sp, 2, oldsr, env->pc, env->pc); break; case EXCP_SPURIOUS ... EXCP_INT_LEVEL_7: if (is_hw && (oldsr & SR_M)) { - do_stack_frame(env, &sp, 0, oldsr, 0, retaddr); + do_stack_frame(env, &sp, 0, oldsr, 0, env->pc); oldsr = sr; env->aregs[7] = sp; cpu_m68k_set_sr(env, sr & ~SR_M); @@ -417,13 +414,13 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) if (!m68k_feature(env, M68K_FEATURE_UNALIGNED_DATA)) { sp &= ~1; } - do_stack_frame(env, &sp, 1, oldsr, 0, retaddr); + do_stack_frame(env, &sp, 1, oldsr, 0, env->pc); break; } /* fall through */ default: - do_stack_frame(env, &sp, 0, oldsr, 0, retaddr); + do_stack_frame(env, &sp, 0, oldsr, 0, env->pc); break; } From patchwork Sat Apr 30 17:53:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 568152 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp7373334map; Sat, 30 Apr 2022 11:02:40 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwHRcCv+7DHwPdJPq9lD7Uk/ns+no3EzOo2EDd9UkYQ26iP6dT2Q3slQdTErMf+wxcAwMwM X-Received: by 2002:a05:6214:621:b0:432:5e0d:cb64 with SMTP id a1-20020a056214062100b004325e0dcb64mr3844218qvx.65.1651341760186; Sat, 30 Apr 2022 11:02:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1651341760; cv=none; d=google.com; s=arc-20160816; b=G9HYfnuKoHt5Na/YOEVHvZ4YowceUckQN3SIl634Dc4E4WLqlbUtW8CCfYNowyCWDj WsAtCpeguWx/bdlqsDlGljIvMIPZxelxF5EJuBv7BGvR+nKx9JbS4ydiwAXf6FdhIO2z 3KSfCNJ2JN/y9NEpnoyUAFE8BLBilxE9ppyzqhG5pTM3uAhLZayiVBUTjQZDtOm1hpz2 DJD0//LSuNrTR6lyxTBmhQqwcPPdNSybquiexzMMM+BE5fah3951HsY6XcWjHGR+++8z l45lfLAI3W6q35CDBmqZOyLTg81/vu93bjuQAIGUQcPkg0mCwGAd0IxeI/AcOxDJNZne xpjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=pV7AUSBmQ/5B1DI3laiJ3NZUsISLiXaxdnniwS0N5G4=; b=Fv7WbON0VYnBw+kvlQhnl9CubDlRlo6ULSzx1wpch+H/5KzTCCjVbcecaBxDQWiGOb 0OUDdGK8MOsE+iiPXM/AhMIjLkq0EVm9nJewLWqiWPy8kajDHjBuNuWNK8nL4110jXE4 pjSGrllLaYh56l4FG4ZA7uDqyIpv9N8bPBcV3QC17ZBzsamDmm6JGHD2fJuRxRGDn6pc JZemxuErutPQU5c+OgICEkeu/kv6mToe2rzYZf7wAOa3e+YhJ20Zq83mLItEc8HAmJz6 ELzRQ/KbhsxuH+Wolgf1HEr1C06KLGUqewWrgtMHxEz3n8SfacGpYdJI0QPg7gJ6eqRW y6Dw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bCmOPnAD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id 5-20020a170902c20500b0015e8d4eb282sm1740910pll.204.2022.04.30.10.53.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 10:53:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 06/17] target/m68k: Fix address argument for EXCP_CHK Date: Sat, 30 Apr 2022 10:53:31 -0700 Message-Id: <20220430175342.370628-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220430175342.370628-1-richard.henderson@linaro.org> References: <20220430175342.370628-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" According to the M68040 Users Manual, section 8.4.3, Six word stack frame (format 2), CHK, CHK2 (and others) are supposed to record the next insn in PC and the address of the trapping instruction in ADDRESS. Create a raise_exception_format2 function to centralize recording of the trapping pc in mmu.ar, plus advancing to the next insn. Update m68k_interrupt_all to pass mmu.ar to do_stack_frame. Update cpu_loop to pass mmu.ar to siginfo.si_addr, as the kernel does in trap_c(). Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/cpu.h | 6 +++++ linux-user/m68k/cpu_loop.c | 2 +- target/m68k/op_helper.c | 54 ++++++++++++++++++++------------------ 3 files changed, 36 insertions(+), 26 deletions(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 9b3bf7a448..558c3c67d6 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -122,6 +122,12 @@ typedef struct CPUArchState { /* MMU status. */ struct { + /* + * Holds the "address" value in between raising an exception + * and creation of the exception stack frame. + * Used for both Format 7 exceptions (Access, i.e. mmu) + * and Format 2 exceptions (chk, div0, trapcc, etc). + */ uint32_t ar; uint32_t ssw; /* 68040 */ diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index 6ca3e1e63a..5d9c1f3753 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -48,7 +48,7 @@ void cpu_loop(CPUM68KState *env) force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc); break; case EXCP_CHK: - force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, env->pc); + force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, env->mmu.ar); break; case EXCP_DIV0: force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->pc); diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 777869790b..750d65576f 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -397,13 +397,16 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) case EXCP_ILLEGAL: case EXCP_DIV0: - case EXCP_CHK: case EXCP_TRAPCC: case EXCP_TRACE: /* FIXME: addr is not only env->pc */ do_stack_frame(env, &sp, 2, oldsr, env->pc, env->pc); break; + case EXCP_CHK: + do_stack_frame(env, &sp, 2, oldsr, env->mmu.ar, env->pc); + break; + case EXCP_SPURIOUS ... EXCP_INT_LEVEL_7: if (is_hw && (oldsr & SR_M)) { do_stack_frame(env, &sp, 0, oldsr, 0, env->pc); @@ -548,6 +551,29 @@ void HELPER(raise_exception)(CPUM68KState *env, uint32_t tt) raise_exception(env, tt); } +G_NORETURN static void +raise_exception_format2(CPUM68KState *env, int tt, int ilen, uintptr_t raddr) +{ + CPUState *cs = env_cpu(env); + + cs->exception_index = tt; + + /* Recover PC and CC_OP for the beginning of the insn. */ + cpu_restore_state(cs, raddr, true); + + /* Flags are current in env->cc_*, or are undefined. */ + env->cc_op = CC_OP_FLAGS; + + /* + * Remember original pc in mmu.ar, for the Format 2 stack frame. + * Adjust PC to end of the insn. + */ + env->mmu.ar = env->pc; + env->pc += ilen; + + cpu_loop_exit(cs); +} + void HELPER(divuw)(CPUM68KState *env, int destr, uint32_t den) { uint32_t num = env->dregs[destr]; @@ -1065,18 +1091,7 @@ void HELPER(chk)(CPUM68KState *env, int32_t val, int32_t ub) env->cc_c = 0 <= ub ? val < 0 || val > ub : val > ub && val < 0; if (val < 0 || val > ub) { - CPUState *cs = env_cpu(env); - - /* Recover PC and CC_OP for the beginning of the insn. */ - cpu_restore_state(cs, GETPC(), true); - - /* flags have been modified by gen_flush_flags() */ - env->cc_op = CC_OP_FLAGS; - /* Adjust PC to end of the insn. */ - env->pc += 2; - - cs->exception_index = EXCP_CHK; - cpu_loop_exit(cs); + raise_exception_format2(env, EXCP_CHK, 2, GETPC()); } } @@ -1097,17 +1112,6 @@ void HELPER(chk2)(CPUM68KState *env, int32_t val, int32_t lb, int32_t ub) env->cc_c = lb <= ub ? val < lb || val > ub : val > ub && val < lb; if (env->cc_c) { - CPUState *cs = env_cpu(env); - - /* Recover PC and CC_OP for the beginning of the insn. */ - cpu_restore_state(cs, GETPC(), true); - - /* flags have been modified by gen_flush_flags() */ - env->cc_op = CC_OP_FLAGS; - /* Adjust PC to end of the insn. */ - env->pc += 4; - - cs->exception_index = EXCP_CHK; - cpu_loop_exit(cs); + raise_exception_format2(env, EXCP_CHK, 4, GETPC()); } } From patchwork Sat Apr 30 17:53:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 568150 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp7371330map; Sat, 30 Apr 2022 10:59:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwl3yJQlW655xawqaX0wyoeGlf76wunkrmiIotjwii06MvJa7JmaRc9pBexjuy1bMSSAfyf X-Received: by 2002:a05:620a:2456:b0:69f:b58e:55de with SMTP id h22-20020a05620a245600b0069fb58e55demr3464228qkn.736.1651341547035; Sat, 30 Apr 2022 10:59:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1651341547; cv=none; d=google.com; s=arc-20160816; b=ZAL348mD7F8tqU2X0Uu/ZP4oJwMdvciy6fDnIq4LXh9s7+327vbJ+y2+8EkznF7X2x 0igf+pXivsLciO65g0tQJhdm+PL0ym/e4qIhl9FswA34UzkjNs7Fv2iDrXiljGCW8qbg Q4ctPv2LkLCkKTXYWEONe2krw+K/u8O98emJSBck5J+NX1tF+gU/Gx4/Y/g0EINQJfaz /xJ/3MaNc4AP8patR11sVsF+bT1p3D/GquT17HsthF3wRKe7G9xivEuSxtJSSHxzigcH eBSZYR6ffwu6YMwU6VffqN52hV0BLA0gtA2ftgBhKbPt9e/UyvM2uX6VUjDyYXCMnIVZ 1LNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=aLxm3+X9E1D8CAxVGxUtiz9SexB3X2/3TU/vGizDvg4=; b=g5oqEgVhSgtWdkBpEEmFSqnAj+1Xd5ViBNpBupkFNgzvaS+EGXJ+FlJiVncv3ctFLs 5yYgFlwpbk0uBRk4crGZFK+3Z8TC7NCOE9Ug3RtTAI7sUG8rDmSPNZ5Kzc28qadO5Yme VkmGRxAy+8WtW0m3NwzfCTv2eblBMcXLJWy/+XwbQDGYfEcX/robwYvEs3/XyCOi1167 tuQW7iTXhyrWV8TXp8o3o/81Dgk8RymlNf+cCehqxgCq1Lhyfrk8Tdj4actu+ETsd6VN UHtQcMu9gDBcJvMtExanPF1Y/PKsW9Hi53Yu8rpJzryypq9YRX6HZFYIWl8LECCQP4n5 GwDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LWvFx4ok; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id 5-20020a170902c20500b0015e8d4eb282sm1740910pll.204.2022.04.30.10.53.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 10:53:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 07/17] target/m68k: Fix pc, c flag, and address argument for EXCP_DIV0 Date: Sat, 30 Apr 2022 10:53:32 -0700 Message-Id: <20220430175342.370628-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220430175342.370628-1-richard.henderson@linaro.org> References: <20220430175342.370628-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" According to the M68040 Users Manual, section 8.4.3, Six word stack frame (format 2), Zero Div (and others) is supposed to record the next insn in PC and the address of the trapping instruction in ADDRESS. While the N, Z and V flags are documented to be undefine on DIV0, the C flag is documented as always cleared. Update helper_div* to take the instruction length as an argument and use raise_exception_format2. Hoist the reset of the C flag above the division by zero check. Update m68k_interrupt_all to pass mmu.ar to do_stack_frame. Update cpu_loop to pass mmu.ar to siginfo.si_addr, as the kernel does in trap_c(). Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/helper.h | 12 +++++----- linux-user/m68k/cpu_loop.c | 2 +- target/m68k/op_helper.c | 48 +++++++++++++++++++++++--------------- target/m68k/translate.c | 33 +++++++++++++------------- 4 files changed, 52 insertions(+), 43 deletions(-) diff --git a/target/m68k/helper.h b/target/m68k/helper.h index 0a6b4146f6..f016c4c1c2 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -1,12 +1,12 @@ DEF_HELPER_1(bitrev, i32, i32) DEF_HELPER_1(ff1, i32, i32) DEF_HELPER_FLAGS_2(sats, TCG_CALL_NO_RWG_SE, i32, i32, i32) -DEF_HELPER_3(divuw, void, env, int, i32) -DEF_HELPER_3(divsw, void, env, int, s32) -DEF_HELPER_4(divul, void, env, int, int, i32) -DEF_HELPER_4(divsl, void, env, int, int, s32) -DEF_HELPER_4(divull, void, env, int, int, i32) -DEF_HELPER_4(divsll, void, env, int, int, s32) +DEF_HELPER_4(divuw, void, env, int, i32, int) +DEF_HELPER_4(divsw, void, env, int, s32, int) +DEF_HELPER_5(divul, void, env, int, int, i32, int) +DEF_HELPER_5(divsl, void, env, int, int, s32, int) +DEF_HELPER_5(divull, void, env, int, int, i32, int) +DEF_HELPER_5(divsll, void, env, int, int, s32, int) DEF_HELPER_2(set_sr, void, env, i32) DEF_HELPER_3(cf_movec_to, void, env, i32, i32) DEF_HELPER_3(m68k_movec_to, void, env, i32, i32) diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index 5d9c1f3753..45419d4471 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -51,7 +51,7 @@ void cpu_loop(CPUM68KState *env) force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, env->mmu.ar); break; case EXCP_DIV0: - force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->pc); + force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->mmu.ar); break; case EXCP_TRAP0: { diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 750d65576f..729ee0e934 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -396,7 +396,6 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) break; case EXCP_ILLEGAL: - case EXCP_DIV0: case EXCP_TRAPCC: case EXCP_TRACE: /* FIXME: addr is not only env->pc */ @@ -404,6 +403,7 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) break; case EXCP_CHK: + case EXCP_DIV0: do_stack_frame(env, &sp, 2, oldsr, env->mmu.ar, env->pc); break; @@ -574,18 +574,19 @@ raise_exception_format2(CPUM68KState *env, int tt, int ilen, uintptr_t raddr) cpu_loop_exit(cs); } -void HELPER(divuw)(CPUM68KState *env, int destr, uint32_t den) +void HELPER(divuw)(CPUM68KState *env, int destr, uint32_t den, int ilen) { uint32_t num = env->dregs[destr]; uint32_t quot, rem; + env->cc_c = 0; /* always cleared, even if div0 */ + if (den == 0) { - raise_exception_ra(env, EXCP_DIV0, GETPC()); + raise_exception_format2(env, EXCP_DIV0, ilen, GETPC()); } quot = num / den; rem = num % den; - env->cc_c = 0; /* always cleared, even if overflow */ if (quot > 0xffff) { env->cc_v = -1; /* @@ -601,18 +602,19 @@ void HELPER(divuw)(CPUM68KState *env, int destr, uint32_t den) env->cc_v = 0; } -void HELPER(divsw)(CPUM68KState *env, int destr, int32_t den) +void HELPER(divsw)(CPUM68KState *env, int destr, int32_t den, int ilen) { int32_t num = env->dregs[destr]; uint32_t quot, rem; + env->cc_c = 0; /* always cleared, even if overflow/div0 */ + if (den == 0) { - raise_exception_ra(env, EXCP_DIV0, GETPC()); + raise_exception_format2(env, EXCP_DIV0, ilen, GETPC()); } quot = num / den; rem = num % den; - env->cc_c = 0; /* always cleared, even if overflow */ if (quot != (int16_t)quot) { env->cc_v = -1; /* nothing else is modified */ @@ -629,18 +631,20 @@ void HELPER(divsw)(CPUM68KState *env, int destr, int32_t den) env->cc_v = 0; } -void HELPER(divul)(CPUM68KState *env, int numr, int regr, uint32_t den) +void HELPER(divul)(CPUM68KState *env, int numr, int regr, + uint32_t den, int ilen) { uint32_t num = env->dregs[numr]; uint32_t quot, rem; + env->cc_c = 0; /* always cleared, even if div0 */ + if (den == 0) { - raise_exception_ra(env, EXCP_DIV0, GETPC()); + raise_exception_format2(env, EXCP_DIV0, ilen, GETPC()); } quot = num / den; rem = num % den; - env->cc_c = 0; env->cc_z = quot; env->cc_n = quot; env->cc_v = 0; @@ -657,18 +661,20 @@ void HELPER(divul)(CPUM68KState *env, int numr, int regr, uint32_t den) } } -void HELPER(divsl)(CPUM68KState *env, int numr, int regr, int32_t den) +void HELPER(divsl)(CPUM68KState *env, int numr, int regr, + int32_t den, int ilen) { int32_t num = env->dregs[numr]; int32_t quot, rem; + env->cc_c = 0; /* always cleared, even if overflow/div0 */ + if (den == 0) { - raise_exception_ra(env, EXCP_DIV0, GETPC()); + raise_exception_format2(env, EXCP_DIV0, ilen, GETPC()); } quot = num / den; rem = num % den; - env->cc_c = 0; env->cc_z = quot; env->cc_n = quot; env->cc_v = 0; @@ -685,19 +691,21 @@ void HELPER(divsl)(CPUM68KState *env, int numr, int regr, int32_t den) } } -void HELPER(divull)(CPUM68KState *env, int numr, int regr, uint32_t den) +void HELPER(divull)(CPUM68KState *env, int numr, int regr, + uint32_t den, int ilen) { uint64_t num = deposit64(env->dregs[numr], 32, 32, env->dregs[regr]); uint64_t quot; uint32_t rem; + env->cc_c = 0; /* always cleared, even if overflow/div0 */ + if (den == 0) { - raise_exception_ra(env, EXCP_DIV0, GETPC()); + raise_exception_format2(env, EXCP_DIV0, ilen, GETPC()); } quot = num / den; rem = num % den; - env->cc_c = 0; /* always cleared, even if overflow */ if (quot > 0xffffffffULL) { env->cc_v = -1; /* @@ -720,19 +728,21 @@ void HELPER(divull)(CPUM68KState *env, int numr, int regr, uint32_t den) env->dregs[numr] = quot; } -void HELPER(divsll)(CPUM68KState *env, int numr, int regr, int32_t den) +void HELPER(divsll)(CPUM68KState *env, int numr, int regr, + int32_t den, int ilen) { int64_t num = deposit64(env->dregs[numr], 32, 32, env->dregs[regr]); int64_t quot; int32_t rem; + env->cc_c = 0; /* always cleared, even if overflow/div0 */ + if (den == 0) { - raise_exception_ra(env, EXCP_DIV0, GETPC()); + raise_exception_format2(env, EXCP_DIV0, ilen, GETPC()); } quot = num / den; rem = num % den; - env->cc_c = 0; /* always cleared, even if overflow */ if (quot != (int32_t)quot) { env->cc_v = -1; /* diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 6d6d026e3c..d775345bfa 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -1601,6 +1601,7 @@ DISAS_INSN(divw) int sign; TCGv src; TCGv destr; + TCGv ilen; /* divX.w ,Dn 32/16 -> 16r:16q */ @@ -1609,20 +1610,20 @@ DISAS_INSN(divw) /* dest.l / src.w */ SRC_EA(env, src, OS_WORD, sign, NULL); - destr = tcg_const_i32(REG(insn, 9)); + destr = tcg_constant_i32(REG(insn, 9)); + ilen = tcg_constant_i32(s->pc - s->base.pc_next); if (sign) { - gen_helper_divsw(cpu_env, destr, src); + gen_helper_divsw(cpu_env, destr, src, ilen); } else { - gen_helper_divuw(cpu_env, destr, src); + gen_helper_divuw(cpu_env, destr, src, ilen); } - tcg_temp_free(destr); set_cc_op(s, CC_OP_FLAGS); } DISAS_INSN(divl) { - TCGv num, reg, den; + TCGv num, reg, den, ilen; int sign; uint16_t ext; @@ -1639,15 +1640,14 @@ DISAS_INSN(divl) /* divX.l , Dr:Dq 64/32 -> 32r:32q */ SRC_EA(env, den, OS_LONG, 0, NULL); - num = tcg_const_i32(REG(ext, 12)); - reg = tcg_const_i32(REG(ext, 0)); + num = tcg_constant_i32(REG(ext, 12)); + reg = tcg_constant_i32(REG(ext, 0)); + ilen = tcg_constant_i32(s->pc - s->base.pc_next); if (sign) { - gen_helper_divsll(cpu_env, num, reg, den); + gen_helper_divsll(cpu_env, num, reg, den, ilen); } else { - gen_helper_divull(cpu_env, num, reg, den); + gen_helper_divull(cpu_env, num, reg, den, ilen); } - tcg_temp_free(reg); - tcg_temp_free(num); set_cc_op(s, CC_OP_FLAGS); return; } @@ -1656,15 +1656,14 @@ DISAS_INSN(divl) /* divXl.l , Dr:Dq 32/32 -> 32r:32q */ SRC_EA(env, den, OS_LONG, 0, NULL); - num = tcg_const_i32(REG(ext, 12)); - reg = tcg_const_i32(REG(ext, 0)); + num = tcg_constant_i32(REG(ext, 12)); + reg = tcg_constant_i32(REG(ext, 0)); + ilen = tcg_constant_i32(s->pc - s->base.pc_next); if (sign) { - gen_helper_divsl(cpu_env, num, reg, den); + gen_helper_divsl(cpu_env, num, reg, den, ilen); } else { - gen_helper_divul(cpu_env, num, reg, den); + gen_helper_divul(cpu_env, num, reg, den, ilen); } - tcg_temp_free(reg); - tcg_temp_free(num); set_cc_op(s, CC_OP_FLAGS); } From patchwork Sat Apr 30 17:53:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 568151 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp7373261map; Sat, 30 Apr 2022 11:02:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyWmatXXdu+Q8ihw0V5tMf2ghlpf1yhThhljuDqevSnyEnH4yCLeHGGkJJGxIIYJ4baiN9V X-Received: by 2002:a05:620a:2544:b0:680:a53b:ec1a with SMTP id s4-20020a05620a254400b00680a53bec1amr3583157qko.544.1651341753979; Sat, 30 Apr 2022 11:02:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id 5-20020a170902c20500b0015e8d4eb282sm1740910pll.204.2022.04.30.10.53.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 10:53:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 08/17] target/m68k: Fix address argument for EXCP_TRACE Date: Sat, 30 Apr 2022 10:53:33 -0700 Message-Id: <20220430175342.370628-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220430175342.370628-1-richard.henderson@linaro.org> References: <20220430175342.370628-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" According to the M68040 Users Manual, section 8.4.3, Six word stack frame (format 2), Trace (and others) is supposed to record the next insn in PC and the address of the trapping instruction in ADDRESS. Create gen_raise_exception_format2 to record the trapping pc in env->mmu.ar. Update m68k_interrupt_all to pass the value to do_stack_frame. Update cpu_loop to handle EXCP_TRACE. Signed-off-by: Richard Henderson Reviewed-by: Laurent Vivier --- linux-user/m68k/cpu_loop.c | 3 +++ target/m68k/op_helper.c | 2 +- target/m68k/translate.c | 49 +++++++++++++++++++++++++------------- 3 files changed, 36 insertions(+), 18 deletions(-) diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index 45419d4471..000bb44cc3 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -53,6 +53,9 @@ void cpu_loop(CPUM68KState *env) case EXCP_DIV0: force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->mmu.ar); break; + case EXCP_TRACE: + force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_TRACE, env->mmu.ar); + break; case EXCP_TRAP0: { abi_long ret; diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 729ee0e934..3cb71c9140 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -397,13 +397,13 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) case EXCP_ILLEGAL: case EXCP_TRAPCC: - case EXCP_TRACE: /* FIXME: addr is not only env->pc */ do_stack_frame(env, &sp, 2, oldsr, env->pc, env->pc); break; case EXCP_CHK: case EXCP_DIV0: + case EXCP_TRACE: do_stack_frame(env, &sp, 2, oldsr, env->mmu.ar, env->pc); break; diff --git a/target/m68k/translate.c b/target/m68k/translate.c index d775345bfa..399d9232e4 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -114,6 +114,7 @@ typedef struct DisasContext { DisasContextBase base; CPUM68KState *env; target_ulong pc; + target_ulong pc_prev; CCOp cc_op; /* Current CC operation */ int cc_op_synced; TCGv_i64 mactmp; @@ -298,6 +299,21 @@ static void gen_raise_exception(int nr) tcg_temp_free_i32(tmp); } +static void gen_raise_exception_format2(DisasContext *s, int nr, + target_ulong this_pc) +{ + /* + * Pass the address of the insn to the exception handler, + * for recording in the Format $2 (6-word) stack frame. + * Re-use mmu.ar for the purpose, since that's only valid + * after tlb_fill. + */ + tcg_gen_st_i32(tcg_constant_i32(this_pc), cpu_env, + offsetof(CPUM68KState, mmu.ar)); + gen_raise_exception(nr); + s->base.is_jmp = DISAS_NORETURN; +} + static void gen_exception(DisasContext *s, uint32_t dest, int nr) { update_cc_op(s); @@ -1494,12 +1510,13 @@ static void gen_exit_tb(DisasContext *s) } while (0) /* Generate a jump to an immediate address. */ -static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest) +static void gen_jmp_tb(DisasContext *s, int n, target_ulong dest, + target_ulong src) { if (unlikely(s->ss_active)) { update_cc_op(s); tcg_gen_movi_i32(QREG_PC, dest); - gen_raise_exception(EXCP_TRACE); + gen_raise_exception_format2(s, EXCP_TRACE, src); } else if (translator_use_goto_tb(&s->base, dest)) { tcg_gen_goto_tb(n); tcg_gen_movi_i32(QREG_PC, dest); @@ -1548,9 +1565,9 @@ DISAS_INSN(dbcc) tcg_gen_addi_i32(tmp, tmp, -1); gen_partset_reg(OS_WORD, reg, tmp); tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, -1, l1); - gen_jmp_tb(s, 1, base + offset); + gen_jmp_tb(s, 1, base + offset, s->base.pc_next); gen_set_label(l1); - gen_jmp_tb(s, 0, s->pc); + gen_jmp_tb(s, 0, s->pc, s->base.pc_next); } DISAS_INSN(undef_mac) @@ -3096,13 +3113,13 @@ DISAS_INSN(branch) /* Bcc */ TCGLabel *l1 = gen_new_label(); gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1); - gen_jmp_tb(s, 1, base + offset); + gen_jmp_tb(s, 1, base + offset, s->base.pc_next); gen_set_label(l1); - gen_jmp_tb(s, 0, s->pc); + gen_jmp_tb(s, 0, s->pc, s->base.pc_next); } else { /* Unconditional branch. */ update_cc_op(s); - gen_jmp_tb(s, 0, base + offset); + gen_jmp_tb(s, 0, base + offset, s->base.pc_next); } } @@ -5485,9 +5502,9 @@ DISAS_INSN(fbcc) l1 = gen_new_label(); update_cc_op(s); gen_fjmpcc(s, insn & 0x3f, l1); - gen_jmp_tb(s, 0, s->pc); + gen_jmp_tb(s, 0, s->pc, s->base.pc_next); gen_set_label(l1); - gen_jmp_tb(s, 1, base + offset); + gen_jmp_tb(s, 1, base + offset, s->base.pc_next); } DISAS_INSN(fscc) @@ -6158,6 +6175,8 @@ static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) dc->env = env; dc->pc = dc->base.pc_first; + /* This value will always be filled in properly before m68k_tr_tb_stop. */ + dc->pc_prev = 0xdeadbeef; dc->cc_op = CC_OP_DYNAMIC; dc->cc_op_synced = 1; dc->done_mac = 0; @@ -6191,6 +6210,7 @@ static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) do_writebacks(dc); do_release(dc); + dc->pc_prev = dc->base.pc_next; dc->base.pc_next = dc->pc; if (dc->base.is_jmp == DISAS_NEXT) { @@ -6225,17 +6245,12 @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) break; case DISAS_TOO_MANY: update_cc_op(dc); - if (dc->ss_active) { - tcg_gen_movi_i32(QREG_PC, dc->pc); - gen_raise_exception(EXCP_TRACE); - } else { - gen_jmp_tb(dc, 0, dc->pc); - } + gen_jmp_tb(dc, 0, dc->pc, dc->pc_prev); break; case DISAS_JUMP: /* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */ if (dc->ss_active) { - gen_raise_exception(EXCP_TRACE); + gen_raise_exception_format2(dc, EXCP_TRACE, dc->pc_prev); } else { tcg_gen_lookup_and_goto_ptr(); } @@ -6246,7 +6261,7 @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) * other state that may require returning to the main loop. */ if (dc->ss_active) { - gen_raise_exception(EXCP_TRACE); + gen_raise_exception_format2(dc, EXCP_TRACE, dc->pc_prev); } else { tcg_gen_exit_tb(NULL, 0); } From patchwork Sat Apr 30 17:53:34 2022 Content-Type: text/plain; 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id 5-20020a170902c20500b0015e8d4eb282sm1740910pll.204.2022.04.30.10.53.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 10:53:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 09/17] target/m68k: Fix stack frame for EXCP_ILLEGAL Date: Sat, 30 Apr 2022 10:53:34 -0700 Message-Id: <20220430175342.370628-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220430175342.370628-1-richard.henderson@linaro.org> References: <20220430175342.370628-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" According to the M68040 Users Manual, section 8.4.3, Four word stack frame (format 0), includes Illegal Instruction. Use the correct frame format, which does not use the ADDR argument. Signed-off-by: Richard Henderson Reviewed-by: Laurent Vivier --- target/m68k/op_helper.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 3cb71c9140..aa62158eb9 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -391,11 +391,14 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) } break; + case EXCP_ILLEGAL: + do_stack_frame(env, &sp, 0, oldsr, 0, env->pc); + break; + case EXCP_ADDRESS: do_stack_frame(env, &sp, 2, oldsr, 0, env->pc); break; - case EXCP_ILLEGAL: case EXCP_TRAPCC: /* FIXME: addr is not only env->pc */ do_stack_frame(env, &sp, 2, oldsr, env->pc, env->pc); From patchwork Sat Apr 30 17:53:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 568156 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp7376436map; Sat, 30 Apr 2022 11:08:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw7ZIDtohQaXJg+NvRxElnOBYMI62yBtxSrvnQP4RZ28AgnDBT6GQNXsgUIxuX0V/L3kBWd X-Received: by 2002:a05:622a:610a:b0:2f1:cce:15fb with SMTP id hg10-20020a05622a610a00b002f10cce15fbmr4296582qtb.436.1651342086250; Sat, 30 Apr 2022 11:08:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1651342086; cv=none; d=google.com; s=arc-20160816; b=Y7qkT+7VRE2AAgjklokThgY6vdO3cANjECTZFVNxM08Mb/qqohVuTWuf+i0v4d9Z3M x8XVMPp1bPuP0u85sfP/NL+8N+DQJU86xvQW+j9bSXhgWuUPVXTjzS/z0KOoAh54ot1F EkiB3MfnqD1yuijSWPofVHRSjxwU+Yzhf8EHh03+ma6njUv36XjBQqZdfRrG/iN9XHVs oQ4wFB+R+vnGiATUe06KRPA3PWf4WEpbxfOFeGmVtKt57mKCFAFfvXWBE1CNtdzCpugF v63yeLpGtr0tmeajIB1hs617K0AqEGxEUyrUD2oEfGZRbap26gCbK4HbFqNuoN1RKeZW /v1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kDs65ZOPg5Kkkmp8VxOfy5lQsAHsaoUz3vkTXU8oqCw=; b=c8TspXm3CCJgOINNX9VxQWsjnc+oK0ARsFzkAgxSHs0x9Tnp3V/Q8Vd3RVA4SIvQG3 s4OVlGQxjBYE+xMohV9ED3xg1QzbHl1KCSSbmdzy4nR0WSRkstbZ13cncevxDwF12qdS FRqtiOXlq96eVhMcr37JsP8gP6XLDRQf8O0kBpxu8PyT9Nq5w99oqgzuecRL9QusC99S uh6/wVRagyIxwlpbeWsUc3vcRqu417s2R7RdvPQT0nerJ1vVazCxmgYsz25ZzNSKh7sA yNFFTuWaJLKB6vIzPMxEe+C+Ku4LO7qRc/Ep4NAKLsyN2reWX7OA9LwmmpRXP2NQ9Qf2 wf6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GTy5pZSv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id 5-20020a170902c20500b0015e8d4eb282sm1740910pll.204.2022.04.30.10.53.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 10:53:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 10/17] target/m68k: Implement TRAPcc Date: Sat, 30 Apr 2022 10:53:35 -0700 Message-Id: <20220430175342.370628-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220430175342.370628-1-richard.henderson@linaro.org> References: <20220430175342.370628-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Resolves: https://gitlab.com/qemu-project/qemu/-/issues/754 Signed-off-by: Richard Henderson Reviewed-by: Laurent Vivier --- target/m68k/cpu.h | 2 ++ linux-user/m68k/cpu_loop.c | 1 + target/m68k/cpu.c | 1 + target/m68k/op_helper.c | 6 +---- target/m68k/translate.c | 49 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 54 insertions(+), 5 deletions(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 558c3c67d6..4d8f48e8c7 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -534,6 +534,8 @@ enum m68k_features { M68K_FEATURE_MOVEC, /* Unaligned data accesses (680[2346]0) */ M68K_FEATURE_UNALIGNED_DATA, + /* TRAPcc insn. (680[2346]0, and CPU32) */ + M68K_FEATURE_TRAPCC, }; static inline int m68k_feature(CPUM68KState *env, int feature) diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index 000bb44cc3..5007b24c03 100644 --- a/linux-user/m68k/cpu_loop.c +++ b/linux-user/m68k/cpu_loop.c @@ -48,6 +48,7 @@ void cpu_loop(CPUM68KState *env) force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc); break; case EXCP_CHK: + case EXCP_TRAPCC: force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, env->mmu.ar); break; case EXCP_DIV0: diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index c7aeb7da9c..5f778773d1 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -162,6 +162,7 @@ static void m68020_cpu_initfn(Object *obj) m68k_set_feature(env, M68K_FEATURE_CHK2); m68k_set_feature(env, M68K_FEATURE_MSP); m68k_set_feature(env, M68K_FEATURE_UNALIGNED_DATA); + m68k_set_feature(env, M68K_FEATURE_TRAPCC); } /* diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index aa62158eb9..61948d92bb 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -399,14 +399,10 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw) do_stack_frame(env, &sp, 2, oldsr, 0, env->pc); break; - case EXCP_TRAPCC: - /* FIXME: addr is not only env->pc */ - do_stack_frame(env, &sp, 2, oldsr, env->pc, env->pc); - break; - case EXCP_CHK: case EXCP_DIV0: case EXCP_TRACE: + case EXCP_TRAPCC: do_stack_frame(env, &sp, 2, oldsr, env->mmu.ar, env->pc); break; diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 399d9232e4..c4fe8abc03 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4879,6 +4879,54 @@ DISAS_INSN(trap) gen_exception(s, s->pc, EXCP_TRAP0 + (insn & 0xf)); } +static void do_trapcc(DisasContext *s, DisasCompare *c) +{ + if (c->tcond != TCG_COND_NEVER) { + TCGLabel *over = NULL; + + update_cc_op(s); + + if (c->tcond != TCG_COND_ALWAYS) { + /* Jump over if !c. */ + over = gen_new_label(); + tcg_gen_brcond_i32(tcg_invert_cond(c->tcond), c->v1, c->v2, over); + } + + tcg_gen_movi_i32(QREG_PC, s->pc); + gen_raise_exception_format2(s, EXCP_TRAPCC, s->base.pc_next); + + if (over != NULL) { + gen_set_label(over); + s->base.is_jmp = DISAS_NEXT; + } + } + free_cond(c); +} + +DISAS_INSN(trapcc) +{ + DisasCompare c; + + /* Consume and discard the immediate operand. */ + switch (extract32(insn, 0, 3)) { + case 2: /* trapcc.w */ + (void)read_im16(env, s); + break; + case 3: /* trapcc.l */ + (void)read_im32(env, s); + break; + case 4: /* trapcc (no operand) */ + break; + default: + /* Illegal insn */ + disas_undef(env, s, insn); + return; + } + + gen_cc_cond(&c, s, extract32(insn, 8, 4)); + do_trapcc(s, &c); +} + static void gen_load_fcr(DisasContext *s, TCGv res, int reg) { switch (reg) { @@ -6050,6 +6098,7 @@ void register_m68k_insns (CPUM68KState *env) INSN(scc, 50c0, f0f8, CF_ISA_A); /* Scc.B Dx */ INSN(scc, 50c0, f0c0, M68000); /* Scc.B */ INSN(dbcc, 50c8, f0f8, M68000); + INSN(trapcc, 50f8, f0f8, TRAPCC); INSN(tpf, 51f8, fff8, CF_ISA_A); /* Branch instructions. */ From patchwork Sat Apr 30 17:53:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 568153 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp7373426map; 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id 5-20020a170902c20500b0015e8d4eb282sm1740910pll.204.2022.04.30.10.53.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 10:53:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 11/17] target/m68k: Implement TPF in terms of TRAPcc Date: Sat, 30 Apr 2022 10:53:36 -0700 Message-Id: <20220430175342.370628-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220430175342.370628-1-richard.henderson@linaro.org> References: <20220430175342.370628-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" TPF stands for "trap false", and is a long-form nop for ColdFire. Re-use the immediate consumption code from trapcc; the insn will already expand to a nop because of the TCG_COND_NEVER test within do_trapcc. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier --- target/m68k/translate.c | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index c4fe8abc03..bb5ed1b7b1 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -3075,22 +3075,6 @@ DISAS_INSN(addsubq) tcg_temp_free(dest); } -DISAS_INSN(tpf) -{ - switch (insn & 7) { - case 2: /* One extension word. */ - s->pc += 2; - break; - case 3: /* Two extension words. */ - s->pc += 4; - break; - case 4: /* No extension words. */ - break; - default: - disas_undef(env, s, insn); - } -} - DISAS_INSN(branch) { int32_t offset; @@ -6099,7 +6083,7 @@ void register_m68k_insns (CPUM68KState *env) INSN(scc, 50c0, f0c0, M68000); /* Scc.B */ INSN(dbcc, 50c8, f0f8, M68000); INSN(trapcc, 50f8, f0f8, TRAPCC); - INSN(tpf, 51f8, fff8, CF_ISA_A); + INSN(trapcc, 51f8, fff8, CF_ISA_A); /* TPF (trapf) */ /* Branch instructions. */ BASE(branch, 6000, f000); From patchwork Sat Apr 30 17:53:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 568155 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp7375342map; Sat, 30 Apr 2022 11:06:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJykMlCxZNeXs+6knf8+FZIDPu7oLwTZxa3O06cSaoMxmpn+N2e5yF3oTOoZDkx6WDPo1iFV X-Received: by 2002:a05:622a:13:b0:2f3:64ce:c72a with SMTP id x19-20020a05622a001300b002f364cec72amr4307983qtw.620.1651341961446; Sat, 30 Apr 2022 11:06:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1651341961; cv=none; d=google.com; s=arc-20160816; b=mqENbulSEo1O+hLm0mDq0d/UDvJQYntq9WX84Lw1Gok546ENDMoei65k8kSrwU2YqN wQ5Y3nCGeE2s7gQN0aMUH0uhF/xgE53EHh9cAuz1uT0Vd0ophwqH41K2XJNO7UpTsMxQ 2mysg4YDq2CG93Z4z6JJGSal8r1j5sVLMc4wOXPFUQ0UC20QOjkqOEwkBCXB7MWpcrMQ fkLW/y7ZVWmWiBZP21WbTwYTVLEKgK8OZ5MYhoPb3WT/z6cqJSzeXvICa/rfonuPZJ7d x/FwmKN0w4RkloOa7B8hPMMCcBkMxclKjaEoSgWXaOnQRhah/wPm5zvN7ykXuAMuIeeG ckEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8VjWHa4+EEAsb2rxF9krBBAxcFamsv8YuijfZ6HxZ44=; b=WwXpk88VCrhp5dh7POG88PAobk8HrU5BvRO2m2N8lyKgqPX3C4k19AB/C6h1nWM6Ty XAa2c7rLjVDialKBAOVfwbZs1Kxk7GX2CXG4Tbh3nyZwAQWJLSqQ3aXBmlTk+hzJAvVY ufNXXXAoEzwLTwFmVEEioPqlpAINZToQ9yGpwhAZsyepbF6Ml+lkieMRcTWk2+kaeJmE GzIddX5O38P2XuTQBpTl1uaYon1Xrkqzq17pkFsPIGWabjKV+iWYFS7/8aSjtwM83vaM r+NUmeGKAK6CN7I6ishQBq74zRPyzkg3Sq5+j10QUvaoPRsJjXcSwI/+3T6P0cV6Jdda e/qg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yuurYXXg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id 5-20020a170902c20500b0015e8d4eb282sm1740910pll.204.2022.04.30.10.53.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 10:53:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 12/17] target/m68k: Implement TRAPV Date: Sat, 30 Apr 2022 10:53:37 -0700 Message-Id: <20220430175342.370628-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220430175342.370628-1-richard.henderson@linaro.org> References: <20220430175342.370628-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Laurent Vivier --- target/m68k/translate.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index bb5ed1b7b1..0cd7ef89e3 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4911,6 +4911,14 @@ DISAS_INSN(trapcc) do_trapcc(s, &c); } +DISAS_INSN(trapv) +{ + DisasCompare c; + + gen_cc_cond(&c, s, 9); /* V set */ + do_trapcc(s, &c); +} + static void gen_load_fcr(DisasContext *s, TCGv res, int reg) { switch (reg) { @@ -6074,6 +6082,7 @@ void register_m68k_insns (CPUM68KState *env) BASE(nop, 4e71, ffff); INSN(rtd, 4e74, ffff, RTD); BASE(rts, 4e75, ffff); + INSN(trapv, 4e76, ffff, M68000); INSN(rtr, 4e77, ffff, M68000); BASE(jump, 4e80, ffc0); BASE(jump, 4ec0, ffc0); From patchwork Sat Apr 30 17:53:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 568158 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp7378012map; Sat, 30 Apr 2022 11:10:47 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx4wlS5XPiLZ617u7lH1HXp9aqV4xmO/aiX9CddrqsYncL7NK1YIbBcVkc0u+W36Yh08LSh X-Received: by 2002:a05:6214:27ec:b0:443:fd5b:ba92 with SMTP id jt12-20020a05621427ec00b00443fd5bba92mr4166800qvb.80.1651342247517; Sat, 30 Apr 2022 11:10:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1651342247; cv=none; d=google.com; s=arc-20160816; b=d1WhWtspWwqq76LKjgTdZs+BY/rxunOlMubXq6BgZTA0STLVuKerrfpsUpWAPlFjcm zcKjEu41HsKmmPYgNvzGhKHVE2EOK9i5Jc2d/rNQRnTV4EX6F8a1bphKLh7E9VosusRA VtT7imkQpYjXVFEQNlcaSgC7VPpOTrYPN2flLu4/TC/Ack/KOKTFvmIQIV0wQyXL+wiy DLgD+qM1bk0cRDx0JRzQwVeokMgETjSLKO9exYm48l3JxmtP5LcS4Kf80iL1WHXXT8Zt IpiNynshnZul8jDsrABkek+a5wreOlwgwWWo3RIiyqYOkIUY8J0ASXQQtKS9PnoiAVDN GnoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DjrjylQ1BROO/szmSr2u/qgefotDd4xpG3+xntl3yXw=; b=EzkOFtIOSNFuoeBR8+kiAWiBGZqBFpTaSVGhFpyormUZuLF2+kASCRT0O+QXbUYqld 4rjT0AV+IdET2DOJfp3QEYUythzRI9Qy+XYSF5/TsTl70ifK0ocyMJNqN+IVM43/Llv5 iaTRCrVrintS1aS1DJx28qG/D0xd0AZ6AaMGB8ODTdtvt8rlnvQwTBJ5xcjP13qvO1/8 HLsZAB6s+Qmydb/AD+TyqQZKPBsL7BjdQM37pV7wygvfWaYYuAhhhbSCLps4ehPwc8Xi 1uC7dJBrV4HB6+RuIAisEgo6tICYwEodRp3bDZRUL//oaIDNip7mWUjaH9znM1GlG3o3 FzGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=K+WmoVS9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id 5-20020a170902c20500b0015e8d4eb282sm1740910pll.204.2022.04.30.10.53.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 10:53:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 13/17] target/m68k: Implement FTRAPcc Date: Sat, 30 Apr 2022 10:53:38 -0700 Message-Id: <20220430175342.370628-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220430175342.370628-1-richard.henderson@linaro.org> References: <20220430175342.370628-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Laurent Vivier --- target/m68k/translate.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 0cd7ef89e3..a3141d7f77 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -5567,6 +5567,35 @@ DISAS_INSN(fscc) tcg_temp_free(tmp); } +DISAS_INSN(ftrapcc) +{ + DisasCompare c; + uint16_t ext; + int cond; + + ext = read_im16(env, s); + cond = ext & 0x3f; + + /* Consume and discard the immediate operand. */ + switch (extract32(insn, 0, 3)) { + case 2: /* ftrapcc.w */ + (void)read_im16(env, s); + break; + case 3: /* ftrapcc.l */ + (void)read_im32(env, s); + break; + case 4: /* ftrapcc (no operand) */ + break; + default: + /* Illegal insn */ + disas_undef(env, s, insn); + return; + } + + gen_fcc_cond(&c, s, cond); + do_trapcc(s, &c); +} + #if defined(CONFIG_SOFTMMU) DISAS_INSN(frestore) { @@ -6190,6 +6219,7 @@ void register_m68k_insns (CPUM68KState *env) INSN(fbcc, f280, ffc0, CF_FPU); INSN(fpu, f200, ffc0, FPU); INSN(fscc, f240, ffc0, FPU); + INSN(ftrapcc, f278, fff8, FPU); INSN(fbcc, f280, ff80, FPU); #if defined(CONFIG_SOFTMMU) INSN(frestore, f340, ffc0, CF_FPU); From patchwork Sat Apr 30 17:53:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 568160 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp7379014map; Sat, 30 Apr 2022 11:12:31 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzA3js35aP+BvJIQfUEVg2AUPp8W9yRnnbPEDSnsoQv/CmWgKGwKsK0QWuOxrhxQxLVt9+x X-Received: by 2002:a37:6906:0:b0:69f:5a68:c2cd with SMTP id e6-20020a376906000000b0069f5a68c2cdmr3403642qkc.298.1651342351549; Sat, 30 Apr 2022 11:12:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1651342351; cv=none; d=google.com; s=arc-20160816; b=MOEGza/RD+UN+/YD022cKWqPW/66eQvKwns1ZjMMPybko1183Of8lk79vzhKAKkfc9 ljJ82mme3M6MOiX8Z2dya7PeJ3BjMchhXo3UI24HzXIZ9uItezSpekxiGW6s+U+0mlqL PkoJjZVkErw9fb0osND4BIgkntdtfVppH9m5FJRT+TlkCulmaL2oX1EE7PaUTID3gXaW 5fRn/yewdqz6K7tWNquMacWMG3mytr99L4CU76euHFmSQ8NOZFqGFQPHvqrkNJlJuJ39 uFhEOrWV52kb+Q8B/Z/Kpx1iS+2Swt/pIAmLC7qZlPHMUmEPGx0mxdYZPep9ryJ8+WOx vJwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=oS4SpFhfIqgKlDgeO+bhyHZ/w+64dvw7Bn99nQxMQ8M=; b=UwUYdAazRejjZiqks1EMLheL1TXVNzqEnimxyj1uCLcuwmgQTqLBJQx2z0OirlNsi3 RZSl/LDsKR2AiZ0wfjcC8q3RKMqVwbh3fBUk4kpuyH3YPgc1Ld4jippRZvRy+gJ4viq2 B74gwvl33yIs7/H1MVAB1tNzm4xfj+xFpIr4GpAruanJySlPy1FfwHm/QshXlY80rla9 rRft8aum/0h0uUnXLtiGPvr8zMtYrZoXY4KjjUNvG71gxGU0OtFW/7Pe7BiVYbdUqfV2 dFpda7FJm1bQNxo6B9UJCeF4D2/Lc8dX+rjwsW24/TE2q+zmpjMIV0IB0n23AAn0CoHj ScqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sSQ+qxw4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id 5-20020a170902c20500b0015e8d4eb282sm1740910pll.204.2022.04.30.10.53.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 10:53:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 14/17] tests/tcg/m68k: Add trap.c Date: Sat, 30 Apr 2022 10:53:39 -0700 Message-Id: <20220430175342.370628-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220430175342.370628-1-richard.henderson@linaro.org> References: <20220430175342.370628-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Test various trap instructions: chk, div, trap, trapv, trapcc, ftrapcc, and the signals and addresses that we expect from them. Signed-off-by: Richard Henderson Reviewed-by: Laurent Vivier --- tests/tcg/m68k/trap.c | 129 +++++++++++++++++++++++++++++++++ tests/tcg/m68k/Makefile.target | 3 + 2 files changed, 132 insertions(+) create mode 100644 tests/tcg/m68k/trap.c diff --git a/tests/tcg/m68k/trap.c b/tests/tcg/m68k/trap.c new file mode 100644 index 0000000000..08ab56b2ca --- /dev/null +++ b/tests/tcg/m68k/trap.c @@ -0,0 +1,129 @@ +/* + * Test m68k trap addresses. + */ + +#define _GNU_SOURCE 1 +#include +#include +#include + +static int expect_sig; +static int expect_si_code; +static void *expect_si_addr; +static greg_t expect_mc_pc; +static volatile int got_signal; + +static void sig_handler(int sig, siginfo_t *si, void *puc) +{ + ucontext_t *uc = puc; + mcontext_t *mc = &uc->uc_mcontext; + + assert(sig == expect_sig); + assert(si->si_code == expect_si_code); + assert(si->si_addr == expect_si_addr); + assert(mc->gregs[R_PC] == expect_mc_pc); + + got_signal = 1; +} + +#define FMT_INS [ad] "a"(&expect_si_addr), [pc] "a"(&expect_mc_pc) +#define FMT0_STR(S) \ + "move.l #1f, (%[ad])\n\tmove.l #1f, (%[pc])\n" S "\n1:\n" +#define FMT2_STR(S) \ + "move.l #0f, (%[ad])\n\tmove.l #1f, (%[pc])\n" S "\n1:\n" + +#define CHECK_SIG do { assert(got_signal); got_signal = 0; } while (0) + +int main(int argc, char **argv) +{ + struct sigaction act = { + .sa_sigaction = sig_handler, + .sa_flags = SA_SIGINFO + }; + int t0, t1; + + sigaction(SIGILL, &act, NULL); + sigaction(SIGTRAP, &act, NULL); + sigaction(SIGFPE, &act, NULL); + + expect_sig = SIGFPE; + expect_si_code = FPE_INTOVF; + asm volatile(FMT2_STR("0:\tchk %0, %1") : : "d"(0), "d"(-1), FMT_INS); + CHECK_SIG; + +#if 0 + /* FIXME: chk2 not correctly translated. */ + int bounds[2] = { 0, 1 }; + asm volatile(FMT2_STR("0:\tchk2.l %0, %1") + : : "m"(bounds), "d"(2), FMT_INS); + CHECK_SIG; +#endif + + asm volatile(FMT2_STR("cmp.l %0, %1\n0:\ttrapv") + : : "d"(INT_MIN), "d"(1), FMT_INS); + CHECK_SIG; + + asm volatile(FMT2_STR("cmp.l %0, %0\n0:\ttrapeq") + : : "d"(0), FMT_INS); + CHECK_SIG; + + asm volatile(FMT2_STR("cmp.l %0, %0\n0:\ttrapeq.w #0x1234") + : : "d"(0), FMT_INS); + CHECK_SIG; + + asm volatile(FMT2_STR("cmp.l %0, %0\n0:\ttrapeq.l #0x12345678") + : : "d"(0), FMT_INS); + CHECK_SIG; + + asm volatile(FMT2_STR("fcmp.x %0, %0\n0:\tftrapeq") + : : "f"(0.0L), FMT_INS); + CHECK_SIG; + + expect_si_code = FPE_INTDIV; + + asm volatile(FMT2_STR("0:\tdivs.w %1, %0") + : "=d"(t0) : "d"(0), "0"(1), FMT_INS); + CHECK_SIG; + + asm volatile(FMT2_STR("0:\tdivsl.l %2, %1:%0") + : "=d"(t0), "=d"(t1) : "d"(0), "0"(1), FMT_INS); + CHECK_SIG; + + expect_sig = SIGILL; + expect_si_code = ILL_ILLOPN; + asm volatile(FMT0_STR("trap #1") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #2") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #3") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #4") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #5") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #6") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #7") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #8") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #9") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #10") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #11") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #12") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #13") : : FMT_INS); + CHECK_SIG; + asm volatile(FMT0_STR("trap #14") : : FMT_INS); + CHECK_SIG; + + expect_sig = SIGTRAP; + expect_si_code = TRAP_BRKPT; + asm volatile(FMT0_STR("trap #15") : : FMT_INS); + CHECK_SIG; + + return 0; +} diff --git a/tests/tcg/m68k/Makefile.target b/tests/tcg/m68k/Makefile.target index 62f109eef4..1163c7ef03 100644 --- a/tests/tcg/m68k/Makefile.target +++ b/tests/tcg/m68k/Makefile.target @@ -3,5 +3,8 @@ # m68k specific tweaks - specifically masking out broken tests # +VPATH += $(SRC_PATH)/tests/tcg/m68k +TESTS += trap + # On m68k Linux supports 4k and 8k pages (but 8k is currently broken) EXTRA_RUNS+=run-test-mmap-4096 # run-test-mmap-8192 From patchwork Sat Apr 30 17:53:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 568149 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp7371327map; 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id 5-20020a170902c20500b0015e8d4eb282sm1740910pll.204.2022.04.30.10.53.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 10:53:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 15/17] linux-user/strace: Fix print_syscall_err Date: Sat, 30 Apr 2022 10:53:40 -0700 Message-Id: <20220430175342.370628-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220430175342.370628-1-richard.henderson@linaro.org> References: <20220430175342.370628-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Errors are not all negative numbers, but only the top 4k. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/strace.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/linux-user/strace.c b/linux-user/strace.c index 2cdbf030ba..dc4f810bd3 100644 --- a/linux-user/strace.c +++ b/linux-user/strace.c @@ -684,12 +684,12 @@ print_ipc(void *cpu_env, const struct syscallname *name, */ static bool -print_syscall_err(abi_long ret) +print_syscall_err(abi_ulong ret) { const char *errstr; qemu_log(" = "); - if (ret < 0) { + if (ret > (abi_ulong)-4096) { errstr = target_strerror(-ret); if (errstr) { qemu_log("-1 errno=%d (%s)", (int)-ret, errstr); From patchwork Sat Apr 30 17:53:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 568157 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp7376462map; Sat, 30 Apr 2022 11:08:08 -0700 (PDT) X-Google-Smtp-Source: ABdhPJySfPTPnDCgSf/hE+uq9mfo0Hz1Mx+KvdkSCZH2u+wMxbNqMcsvYwUzNNJBwnGN44N7E8Ml X-Received: by 2002:a05:620a:1436:b0:69f:8c1c:d145 with SMTP id k22-20020a05620a143600b0069f8c1cd145mr3540372qkj.671.1651342088818; Sat, 30 Apr 2022 11:08:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1651342088; cv=none; d=google.com; s=arc-20160816; b=F6UQgCXgHEKE0FZbYPSfMl7+XmqOn8DwNXPsriPfpWkpwVLHgKs0RLhZVNGOdFUmKf XWvUGxNnbm8YUqXfaUC0wpkCnbSzOaeZBsey9EeJlRfnYFfwLRrnGL2BDIotIX8Ooqgs zMUEnYFin2j9eeipTL6wT+bs3rqRXtasXpD53EXMrqXBkpZiS9y9/vT+8xHd7pYD78Ey 4D3h+Het8KcEqTzw/AgK+6slFuSIDQqjlyzCM6gEXEmO9bDzOUr2PwcVTFZjqcNNjNFP VjNrno74yMBRUVYZb2N7weYVQjEhUs0MMO6dvgkUlY/1PktUl1NTvgp9A38heWB5+lVJ ZvXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=gj8aT9K8/vY1AA3/2X3YXf7zoSHmmenH8vDdjGXjcZ8=; b=xRyIwS8r9U0q5wDIWRKaVcYHjEv9Ugi4S5e8eKBi94+A5kvpdoEmRCMu0U3E4NxI+B Qp9Ng5r0M+qvkjzZXvwgZfgX7GVZoSgk2rcfFzgaNzQ6ItrxCGG9pUnDdNdGq6J+oorS X52w19XXvnaex+zuHf/ykPNYt6Mu63UoQ2u2YvxhcDCcMZCA7nDsgs0XZVRCw6RREV0K NeQ/CXcGYyYYYH6i6Y/FxM6jyc0u7YFcFWS7AZJNSWuu8dzQ7qQTuT0QZ6rK1HfB68rX wnJBR62hyMSAkW+ljRtMfegUi8r8jKbuQ3CvKK1rfLR86Bzsu0Yxy32ZNd/hI/s6dSaw akDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=v7QxhdWa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id 5-20020a170902c20500b0015e8d4eb282sm1740910pll.204.2022.04.30.10.53.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 10:53:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 16/17] linux-user/strace: Adjust get_thread_area for m68k Date: Sat, 30 Apr 2022 10:53:41 -0700 Message-Id: <20220430175342.370628-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220430175342.370628-1-richard.henderson@linaro.org> References: <20220430175342.370628-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Unlike i386, m68k get_thread_area has no arguments. Signed-off-by: Richard Henderson Reviewed-by: Laurent Vivier --- linux-user/strace.list | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/linux-user/strace.list b/linux-user/strace.list index 278596acd1..72e17b1acf 100644 --- a/linux-user/strace.list +++ b/linux-user/strace.list @@ -384,8 +384,13 @@ { TARGET_NR_getsockopt, "getsockopt" , NULL, NULL, NULL }, #endif #ifdef TARGET_NR_get_thread_area +#if defined(TARGET_I386) && defined(TARGET_ABI32) { TARGET_NR_get_thread_area, "get_thread_area", "%s(0x"TARGET_ABI_FMT_lx")", NULL, NULL }, +#elif defined(TARGET_M68K) +{ TARGET_NR_get_thread_area, "get_thread_area" , "%s()", + NULL, print_syscall_ret_addr }, +#endif #endif #ifdef TARGET_NR_gettid { TARGET_NR_gettid, "gettid" , "%s()", NULL, NULL }, From patchwork Sat Apr 30 17:53:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 568159 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp7378038map; Sat, 30 Apr 2022 11:10:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxli9YfPtFd0deXu22KM7Cg/vr1OESx4NvokAs4G6Du/hq1Nl39tNjbgD5Lp8+d+j2/Ok/x X-Received: by 2002:ac8:7d09:0:b0:2f3:677f:dd76 with SMTP id g9-20020ac87d09000000b002f3677fdd76mr4305724qtb.326.1651342250027; Sat, 30 Apr 2022 11:10:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1651342250; cv=none; d=google.com; s=arc-20160816; b=gUPMXtbnhvJJCXHwewwutdOFYDbxw9CiCVQPEjtG7ktV8o8pz0MI7hDTILx9/zTcnX Y0ql3OIbkcnDjpPBO46mxNP4ok5NKFbapsg/PeNz+xRRTjUN/XGqpeXfBq9KqdBtjoPn meQ/rOjfzfELkKnX3vGUUNPJYjqzU2E4OF+MOpNnGp0op4vBK8flrKFqBQrZFG7tJJfS LzOIizvb8CSFmNnMmayGAxCLttCqBg1++Y1Zn1MDzqQXibirESBXfEvH1wyyXrwOZEKA gLaRT4xc4Gg0NZlNASQIzd/0QvKq/DCLHsMhDSlst19/K5AdAxwKXiC3nEPyVk1YokuJ uDHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qLuJ3kY0B/Vq78Y89l2hbdJvKBIIYeH0UMXub8wd6WI=; b=ox8NZpMoa548cR2Pp/k0mYUprJ3OetfaURgv8bmFinaWp8t5p6cnR4m7jf1XjaAYvn r33USvBPoOhodY13bt8Z2mfa94TXucNcCXXz8cYZL2vk+33rvyOdPTUOj/x6cEPoYvOE iUJ71Zcr6OlLI4UcwxESBJ9+FHic+9HP5K8uFo3JOijukMJBfFQSla3YLDNd+XA/XibU 1PubSVec/J3BeOwiwz0fkhUzDknc1d2TXTJsVo1DPnJp1on90jElj+t6i7V4EYKiL6H/ xa3+1ycjYDVFW3yo3HlEwx26+dJI1aECacWJy2Jf97FqtXQ/vrsVO2ecDy2/whKbi2OL V4xQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gQVkNqF3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id 5-20020a170902c20500b0015e8d4eb282sm1740910pll.204.2022.04.30.10.53.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 10:53:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 17/17] target/m68k: Mark helper_raise_exception as noreturn Date: Sat, 30 Apr 2022 10:53:42 -0700 Message-Id: <20220430175342.370628-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220430175342.370628-1-richard.henderson@linaro.org> References: <20220430175342.370628-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Also mark raise_exception_ra and raise_exception, lest we generate a warning about helper_raise_exception returning. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier --- target/m68k/helper.h | 2 +- target/m68k/op_helper.c | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/target/m68k/helper.h b/target/m68k/helper.h index f016c4c1c2..c9bed2b884 100644 --- a/target/m68k/helper.h +++ b/target/m68k/helper.h @@ -109,7 +109,7 @@ DEF_HELPER_3(set_mac_extu, void, env, i32, i32) DEF_HELPER_2(flush_flags, void, env, i32) DEF_HELPER_2(set_ccr, void, env, i32) DEF_HELPER_FLAGS_1(get_ccr, TCG_CALL_NO_WG_SE, i32, env) -DEF_HELPER_2(raise_exception, void, env, i32) +DEF_HELPER_2(raise_exception, noreturn, env, i32) DEF_HELPER_FLAGS_3(bfffo_reg, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index 61948d92bb..d9937ca8dc 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -532,7 +532,8 @@ bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request) #endif /* !CONFIG_USER_ONLY */ -static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr) +G_NORETURN static void +raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr) { CPUState *cs = env_cpu(env); @@ -540,7 +541,7 @@ static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr) cpu_loop_exit_restore(cs, raddr); } -static void raise_exception(CPUM68KState *env, int tt) +G_NORETURN static void raise_exception(CPUM68KState *env, int tt) { raise_exception_ra(env, tt, 0); }