From patchwork Sat Jun 3 04:04:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ding Tianhong X-Patchwork-Id: 101296 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp41540qgd; Fri, 2 Jun 2017 21:05:08 -0700 (PDT) X-Received: by 10.99.61.199 with SMTP id k190mr10339759pga.57.1496462708286; Fri, 02 Jun 2017 21:05:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496462708; cv=none; d=google.com; s=arc-20160816; b=DtKO+qLqfPXdtr+BEBpr77YdA3TXjBSL2vN0qc3RL+iiYlDSx+QIuAWJolbQNOTW4B RGGhNFcYMpkk7ve2S+U3oWHp1sZi+22Nv0kARUWyB1EZCP1ejm6NV+d/y00xEs3lWFU6 sbOuLJjFbfAXMyFDvfZhSiOEMBTY2rOrILOGWczocRpZMcozSU6xyaPBitiKXvQOHNA6 8lL2rz0Zo63jtsTqAmJXmJsvCpfoygww8PDv4HkvQTzD+an6EIWTP0kuejCQjB6Jgicv TrG64Fo0moCkYNjgsl/Krl3UGDsdzLm0tG1tYtl/kOq0oi9qv6Hlpr1gqq4a0QV2MJa/ aVyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=44Bg9U8BvSrRj6nBK+KhCZq/21LLygqY4TTP9eCfKbk=; b=EgRLdkk3irsMqvvGn8k+OjPS37eFiwIvqBtnaJ03bwcta+ryedpegFqccDjjic5AOI G+PjJSl4wmp2mhAjJlXTyjMDI3G0EnvwOLj9UttHtBMJ1p5KQIAaXyrbWyBc4g4cokAZ KKghJxDuMs6NmX66caWoCRA1kKSPbDwutqYHPgwINGoPgaCVdYz+t9CAue64VMOQVkxR LiRJ+FLFwJx9+Mr6WGX8Phh2ukNE9SgE5TzILmaQzHh5GP3H1ynUgfYPzJh/TkqeQ+ao OWcVn/z2HNl5/u2alru3R7Ns66VLI3bfJTYwgRpJw+dod/nFx7u8AUCLk+Ve7b05l1IN 5BVw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q1si707856pge.144.2017.06.02.21.05.07; Fri, 02 Jun 2017 21:05:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751310AbdFCEEr (ORCPT + 25 others); Sat, 3 Jun 2017 00:04:47 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:7303 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751168AbdFCEEp (ORCPT ); Sat, 3 Jun 2017 00:04:45 -0400 Received: from 172.30.72.56 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.56]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APR03904; Sat, 03 Jun 2017 12:04:24 +0800 (CST) Received: from localhost (10.177.23.32) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Sat, 3 Jun 2017 12:04:12 +0800 From: Ding Tianhong To: , , , , , , , , , , , , , , , , , , , , , , , CC: Ding Tianhong Subject: [PATCH v2 1/3] PCI: Add new PCIe Fabric End Node flag, PCI_DEV_FLAGS_NO_RELAXED_ORDERING Date: Sat, 3 Jun 2017 12:04:05 +0800 Message-ID: <1496462647-7632-2-git-send-email-dingtianhong@huawei.com> X-Mailer: git-send-email 1.8.5.2.msysgit.0 In-Reply-To: <1496462647-7632-1-git-send-email-dingtianhong@huawei.com> References: <1496462647-7632-1-git-send-email-dingtianhong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090202.5932354A.003C, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: b6320d18526f6840b153b5ab787dbb7d Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Casey Leedom The new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING indicates that the Relaxed Ordering Attribute should not be used on Transaction Layer Packets destined for the PCIe End Node so flagged. Initially flagged this way are Intel E5-26xx Root Complex Ports which suffer from a Flow Control Credit Performance Problem and AMD A1100 ARM ("SEATTLE") Root Complex Ports which don't obey PCIe 3.0 ordering rules which can lead to Data Corruption. Signed-off-by: Casey Leedom Signed-off-by: Ding Tianhong --- drivers/pci/quirks.c | 38 ++++++++++++++++++++++++++++++++++++++ include/linux/pci.h | 2 ++ 2 files changed, 40 insertions(+) -- 1.9.0 diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 085fb78..58bdd23 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3999,6 +3999,44 @@ static void quirk_tw686x_class(struct pci_dev *pdev) quirk_tw686x_class); /* + * Some devices have problems with Transaction Layer Packets with the Relaxed + * Ordering Attribute set. Such devices should mark themselves and other + * Device Drivers should check before sending TLPs with RO set. + */ +static void quirk_relaxedordering_disable(struct pci_dev *dev) +{ + dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; +} + +/* + * Intel E5-26xx Root Complex has a Flow Control Credit issue which can + * cause performance problems with Upstream Transaction Layer Packets with + * Relaxed Ordering set. + */ +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); + +/* + * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex + * where Upstream Transaction Layer Packets with the Relaxed Ordering + * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering + * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules + * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 + * November 10, 2010). As a result, on this platform we can't use Relaxed + * Ordering for Upstream TLPs. + */ +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); + +/* * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same * values for the Attribute as were supplied in the header of the * corresponding Request, except as explicitly allowed when IDO is used." diff --git a/include/linux/pci.h b/include/linux/pci.h index 33c2b0b..e1e8428 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -183,6 +183,8 @@ enum pci_dev_flags { PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), /* Do not use FLR even if device advertises PCI_AF_CAP */ PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), + /* Don't use Relaxed Ordering for TLPs directed at this device */ + PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), }; enum pci_irq_reroute_variant { From patchwork Sat Jun 3 04:04:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ding Tianhong X-Patchwork-Id: 101299 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp41696qgd; Fri, 2 Jun 2017 21:05:47 -0700 (PDT) X-Received: by 10.98.224.194 with SMTP id d63mr3911377pfm.174.1496462747098; Fri, 02 Jun 2017 21:05:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496462747; cv=none; d=google.com; s=arc-20160816; b=0qIhiC5D2FFGS9driMsGN6haC8r/bMFZOt2wpD1ejb0+QyQT4E2LzBUrESbSoZg8dR 9j97Ghuq2ctqXibIZ4LEtYF9a2IO3tSufiGl4nbcQvcbEL9Gbg2AcdVfNn4Pe8XzoqFh 2go8sz8sSvClI8E/MBPXsBZ2bj2RD/LjUK7ePRCHP2PRYL69OcHHBkKdRC/F7+RWZI8M 9pY+jyRmaMGkUJ2wpFwD/FRqSGR2SbJ8yy2JO6Wix+r0AsxygTnwNToPD2+f165vbh/V 5KzEdMEEtQEYTOqEU+kwbFw6H9lnbMX6kQ+cPCdMDKIm8jriUy7VuTu7nBqXgYv2KWhe /QIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=55v2FwrKIWw69yGXYt0GiWLER3dhCKvhBWxjhILS5lA=; b=ItymKZcB6qSP9IBwHzUSqFjIBKGrmFFf0C+nWCO3HckZjbuOqevqPXl/Doa8i3jhsz mt/nhyPl6iIhZ36ZRHtml/P2AxQDbw3U012QnD3px411RLra3Tj3CIFrbPPjSdGwdOZG ddZRJRZLd+gAfruoo212OMMjJESLAy70gk9h+KGwR/SXnAuSvAT1DVOuXL88TZraGtmw Em8V/b2x7mtLWxBxSyKZKjd7GLcJTuJFZOPUG9cydWuHZXKrd3weuA+0Dxqzvns/CpjL do8k9GR4zaWBx1hgyQAxjF+oJQWyYWMbcxKzpCMwJtxidSHPVUo9yrxlZB3r9LHE0vXD GbGA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 33si1501794plc.304.2017.06.02.21.05.46; Fri, 02 Jun 2017 21:05:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751349AbdFCEFb (ORCPT + 25 others); Sat, 3 Jun 2017 00:05:31 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:7302 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751241AbdFCEEk (ORCPT ); Sat, 3 Jun 2017 00:04:40 -0400 Received: from 172.30.72.56 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.56]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APR03903; Sat, 03 Jun 2017 12:04:24 +0800 (CST) Received: from localhost (10.177.23.32) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Sat, 3 Jun 2017 12:04:14 +0800 From: Ding Tianhong To: , , , , , , , , , , , , , , , , , , , , , , , CC: Ding Tianhong Subject: [PATCH v2 2/3] PCI: Enable PCIe Relaxed Ordering if supported Date: Sat, 3 Jun 2017 12:04:06 +0800 Message-ID: <1496462647-7632-3-git-send-email-dingtianhong@huawei.com> X-Mailer: git-send-email 1.8.5.2.msysgit.0 In-Reply-To: <1496462647-7632-1-git-send-email-dingtianhong@huawei.com> References: <1496462647-7632-1-git-send-email-dingtianhong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090205.5932354B.0018, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 63dd14c2a9e0465dbc74dbd82be0d15c Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The PCIe Device Control Register use the bit 4 to indicate that whether the device is permitted to enable relaxed ordering or not. But relaxed ordering is not safe for some platform which could only use strong write ordering, so devices are allowed (but not required) to enable relaxed ordering bit by default. If a platform support relaxed ordering but does not enable it by default, enable it in the PCIe configuration. This allows some device to send TLPs with the relaxed ordering attributes set, which may improve the performance. Signed-off-by: Ding Tianhong --- drivers/pci/pci.c | 42 ++++++++++++++++++++++++++++++++++++++++++ drivers/pci/probe.c | 11 +++++++++++ include/linux/pci.h | 3 +++ 3 files changed, 56 insertions(+) -- 1.9.0 diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index b01bd5b..f57a374 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4878,6 +4878,48 @@ int pcie_set_mps(struct pci_dev *dev, int mps) EXPORT_SYMBOL(pcie_set_mps); /** + * pcie_set_relaxed_ordering - set PCI Express relexed ordering bit + * @dev: PCI device to query + * + * If possible sets relaxed ordering + */ +int pcie_set_relaxed_ordering(struct pci_dev *dev) +{ + return pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN); +} +EXPORT_SYMBOL(pcie_set_relaxed_ordering); + +/** + * pcie_clear_relaxed_ordering - clear PCI Express relexed ordering bit + * @dev: PCI device to query + * + * If possible clear relaxed ordering + */ +int pcie_clear_relaxed_ordering(struct pci_dev *dev) +{ + return pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN); +} +EXPORT_SYMBOL(pcie_clear_relaxed_ordering); + +/** + * pcie_get_relaxed_ordering - check PCI Express relexed ordering bit + * @dev: PCI device to query + * + * Returns true if relaxed ordering is been set + */ +int pcie_get_relaxed_ordering(struct pci_dev *dev) +{ + u16 v; + + pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); + + return (v & PCI_EXP_DEVCTL_RELAX_EN) >> 4; +} +EXPORT_SYMBOL(pcie_get_relaxed_ordering); + +/** + * pcie_set_mps - set PCI Express maximum payload size +/** * pcie_get_minimum_link - determine minimum link settings of a PCI device * @dev: PCI device to query * @speed: storage for minimum speed diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 19c8950..aeb22b5 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1701,6 +1701,16 @@ static void pci_configure_extended_tags(struct pci_dev *dev) PCI_EXP_DEVCTL_EXT_TAG); } +static void pci_configure_relaxed_ordering(struct pci_dev *dev) +{ + int ret; + + if (dev && (dev->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING)) + pcie_set_relaxed_ordering(dev); + else + pcie_clear_relaxed_ordering(dev); +} + static void pci_configure_device(struct pci_dev *dev) { struct hotplug_params hpp; @@ -1708,6 +1718,7 @@ static void pci_configure_device(struct pci_dev *dev) pci_configure_mps(dev); pci_configure_extended_tags(dev); + pci_configure_relaxed_ordering(dev); memset(&hpp, 0, sizeof(hpp)); ret = pci_get_hp_params(dev, &hpp); diff --git a/include/linux/pci.h b/include/linux/pci.h index e1e8428..84bd6af 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1105,6 +1105,9 @@ int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, void pci_pme_wakeup_bus(struct pci_bus *bus); void pci_d3cold_enable(struct pci_dev *dev); void pci_d3cold_disable(struct pci_dev *dev); +int pcie_set_relaxed_ordering(struct pci_dev *dev); +int pcie_clear_relaxed_ordering(struct pci_dev *dev); +int pcie_get_relaxed_ordering(struct pci_dev *dev); static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable) From patchwork Sat Jun 3 04:04:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ding Tianhong X-Patchwork-Id: 101297 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp41546qgd; Fri, 2 Jun 2017 21:05:08 -0700 (PDT) X-Received: by 10.99.121.13 with SMTP id u13mr10396272pgc.147.1496462708647; Fri, 02 Jun 2017 21:05:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496462708; cv=none; d=google.com; s=arc-20160816; b=oj+UNgo2YuR+a2v6+YeN3YP0j+qzZq8Or0Gr4OJXUXvGSWkukAdFdKvrStDxjJQ/pC Ql6+WEvj4S/xu/mrOT8cFXrq30OjcJMVlhl8czPiKtgU9/9E8gwXpCPMk0B12GrMLjoO W9sXx34VoK1E1uf1bx9URi7jlGIqxKb0HBX4wKiinSNHBzeiQQMa34Pay5lTAIxwQrlx 9tZ8/VQAdWY4iHDcnNwHB502bODcWqQc1F5L3N+cxlWkHHpUROKQ/zOt32HXaT5z/CBt q8y2b3So7TDZX8OIySG8mSuNiF/utcndAakRPvYwRLK86mNHiTOIZ5Fx1N7qClb5SDks oHwQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=PzmLuCjHegW1766GL6fHbRD5Iv6JZPpt4Hk/DR4LoT0=; b=qNV1qFFf82aQHqP8FIu9quBn2eG1n8c7pPinOMtAbWGCqE6TRm8kw8o6aUa4M66JRL 1p+2LEYo/7/mte6csluJb2IOepliMLPNsNfJlFzOownqv0t2Hw3SYoAS7q13F0/TGkp/ zhcmv8E604kEFThhA2ux27yQc8a/PJDgzVXtJKYtB7qWz3eeiBj+YdTK974eldBxAab7 yagcaPhSG9yAVVjaJ3hoQlIN1nx4nEAy4nombfukJlRKMuRLNv7f/fKWh/uRpaPVPsyX /fq+O8mEC9A5JLLhJM89daPF+NufSerBhEc1CAzgecV1IZtKhuTcK9rYgO/BtO4sseDU 8nJw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q1si707856pge.144.2017.06.02.21.05.08; Fri, 02 Jun 2017 21:05:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751284AbdFCEEm (ORCPT + 25 others); Sat, 3 Jun 2017 00:04:42 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:7301 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751168AbdFCEEi (ORCPT ); Sat, 3 Jun 2017 00:04:38 -0400 Received: from 172.30.72.56 (EHLO dggeml406-hub.china.huawei.com) ([172.30.72.56]) by dggrg01-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id APR03900; Sat, 03 Jun 2017 12:04:24 +0800 (CST) Received: from localhost (10.177.23.32) by dggeml406-hub.china.huawei.com (10.3.17.50) with Microsoft SMTP Server id 14.3.301.0; Sat, 3 Jun 2017 12:04:15 +0800 From: Ding Tianhong To: , , , , , , , , , , , , , , , , , , , , , , , CC: Ding Tianhong Subject: [PATCH v2 3/3] net/cxgb4: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag Date: Sat, 3 Jun 2017 12:04:07 +0800 Message-ID: <1496462647-7632-4-git-send-email-dingtianhong@huawei.com> X-Mailer: git-send-email 1.8.5.2.msysgit.0 In-Reply-To: <1496462647-7632-1-git-send-email-dingtianhong@huawei.com> References: <1496462647-7632-1-git-send-email-dingtianhong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090203.5932354B.0024, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: aa2448f62044ee080b96600cbccc6293 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Casey Leedom cxgb4 Ethernet driver now queries Root Complex Port to determine if it can send TLPs to it with the Relaxed Ordering Attribute set. Signed-off-by: Casey Leedom Signed-off-by: Ding Tianhong --- drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 1 + drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 17 +++++++++++++++++ drivers/net/ethernet/chelsio/cxgb4/sge.c | 5 +++-- 3 files changed, 21 insertions(+), 2 deletions(-) -- 1.9.0 diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h index e88c180..478f25a 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h +++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h @@ -521,6 +521,7 @@ enum { /* adapter flags */ USING_SOFT_PARAMS = (1 << 6), MASTER_PF = (1 << 7), FW_OFLD_CONN = (1 << 9), + ROOT_NO_RELAXED_ORDERING = (1 << 10), }; enum { diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c index 38a5c67..fbfe341 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c +++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c @@ -4628,6 +4628,7 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) #ifdef CONFIG_PCI_IOV u32 v, port_vec; #endif + struct pci_dev *root; printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION); @@ -4726,6 +4727,22 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) adapter->msg_enable = DFLT_MSG_ENABLE; memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map)); + /* If possible, we use PCIe Relaxed Ordering Attribute to deliver + * Ingress Packet Data to Free List Buffers in order to allow for + * chipset performance optimizations between the Root Complex and + * Memory Controllers. (Messages to the associated Ingress Queue + * notifying new Packet Placement in the Free Lists Buffers will be + * send without the Relaxed Ordering Attribute thus guaranteing that + * all preceding PCIe Transaction Layer Packets will be processed + * first.) But some Root Complexes have various issues with Upstream + * Transaction Layer Packets with the Relaxed Ordering Attribute set. + * So we check our Root Complex to see if it's flaged with advice + * against using Relaxed Ordering. + */ + root = pci_find_pcie_root_port(adapter->pdev); + if (pcie_get_relaxed_ordering(root)) + adapter->flags |= ROOT_NO_RELAXED_ORDERING; + spin_lock_init(&adapter->stats_lock); spin_lock_init(&adapter->tid_release_lock); spin_lock_init(&adapter->win0_lock); diff --git a/drivers/net/ethernet/chelsio/cxgb4/sge.c b/drivers/net/ethernet/chelsio/cxgb4/sge.c index f05f0d4..ac229a3 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/sge.c +++ b/drivers/net/ethernet/chelsio/cxgb4/sge.c @@ -2571,6 +2571,7 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, struct fw_iq_cmd c; struct sge *s = &adap->sge; struct port_info *pi = netdev_priv(dev); + int relaxed = !(adap->flags & ROOT_NO_RELAXED_ORDERING); /* Size needs to be multiple of 16, including status entry. */ iq->size = roundup(iq->size, 16); @@ -2624,8 +2625,8 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, flsz = fl->size / 8 + s->stat_len / sizeof(struct tx_desc); c.iqns_to_fl0congen |= htonl(FW_IQ_CMD_FL0PACKEN_F | - FW_IQ_CMD_FL0FETCHRO_F | - FW_IQ_CMD_FL0DATARO_F | + FW_IQ_CMD_FL0FETCHRO_V(relaxed) | + FW_IQ_CMD_FL0DATARO_V(relaxed) | FW_IQ_CMD_FL0PADEN_F); if (cong >= 0) c.iqns_to_fl0congen |=