From patchwork Wed Dec 19 12:41:58 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 154266 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4891312ljp; Wed, 19 Dec 2018 04:43:58 -0800 (PST) X-Google-Smtp-Source: AFSGD/WnW00rxGA68c6wKAixRXXW5E+YUnPBI9pGypem4Nb5zUOtonkhiF52TP8JUguCs1rfH6zl X-Received: by 2002:a17:902:227:: with SMTP id 36mr20363186plc.140.1545223438270; Wed, 19 Dec 2018 04:43:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545223438; cv=none; d=google.com; s=arc-20160816; b=WkyjLQm2zfK0eOqIG/5wNVGGdymLaqODbliQFnr3MBDK5Vgy0uedhOxLVMN2aLFZhD tX//9lw1P2OW5X14UH3dzqa8W/zyVJ1wBqONZGJ8XxRQS/iGiDzSgnrOnCMpHMVfRjO+ qAMF90+hS6adWZu5zjuGlAW0dw38w8ZFIgF5gU4tzfursQ9w1SLzyMxY5/R4SHW9uVgf 5xu2ePYuTgZ2yL0q6I8BsIKeOu+ZydfuDfSJooXiyWuimYysa10VWu0zNphpMKt5gcBQ PGI9Wu1tVYEaqJMmrHydrb9JSd3Fm8d/8+FMDpLuO7MMR5IRIbAGHzYJkOtVYOku3gY1 EBVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=GmaChAagvvR3BKGTtUPZxsSHjPP8U/j4RxXcXLkz7sg=; b=VXdfs8ZrtTcjnoiOZu2nTCBBliURsjfY1dt95TW9rgqZvbQjGfnse4ImqrVf9LZMFz sfKVnwoVtHXgSgNpCD1pJ2lrVaQ7zj43JLqP+2SV6KY8N+L31SmN5uDHwX/jYVVa8gOI Ddh3cUWioa1xpdY+Cawt2pbG0+rxMafBWEowhhmlkCQbYTNISet65S4p1VhbJnR9IoAS cjOxo979ko+fJvnzcCw6uAgipjF+ynYpHHF3yBqJVTlW8lXK3GOP+pgNSumRDV7P9ghQ 8+aZbgQL2+HW/DKKfdMg+7sDnj2W0c5ytluZRot0lPm8eZ4oN+m5ZwUx5h/0vXCbzSNF BOZw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="C2wDmQb/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id t12si15489558plq.190.2018.12.19.04.43.57; Wed, 19 Dec 2018 04:43:58 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="C2wDmQb/"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729800AbeLSMnI (ORCPT + 31 others); Wed, 19 Dec 2018 07:43:08 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:54698 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729723AbeLSMms (ORCPT ); Wed, 19 Dec 2018 07:42:48 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id wBJCgU2w098475; Wed, 19 Dec 2018 06:42:30 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1545223350; bh=GmaChAagvvR3BKGTtUPZxsSHjPP8U/j4RxXcXLkz7sg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=C2wDmQb/8TisaVIM7M1lDDwyAWjWX7oYY9rQcmg2zzCgRGEjJilx0yvXbZgSukipx ob/1DOMpGn8dqfJHiX6heKO4IOhVXghftn5AImh6ggQSdc0WRlu2yf7W+b1jMJs8A1 9A+XKBnTlKFUpRwwAllMOtDNSSnc8hhHZAIYryaM= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wBJCgUx1051539 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 19 Dec 2018 06:42:30 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Wed, 19 Dec 2018 06:42:30 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Wed, 19 Dec 2018 06:42:30 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wBJCgNZk003940; Wed, 19 Dec 2018 06:42:27 -0600 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi , Gustavo Pimentel , Marc Zyngier CC: Bjorn Helgaas , Jingoo Han , , , , Subject: [PATCH 01/10] PCI: keystone: Cleanup interrupt related macros Date: Wed, 19 Dec 2018 18:11:58 +0530 Message-ID: <20181219124207.13479-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181219124207.13479-1-kishon@ti.com> References: <20181219124207.13479-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org No functional change. Change both MSI interrupt and legacy interrupt related macros to take an additional argument in order to return the correct register offset. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 26 +++++++++++------------ 1 file changed, 13 insertions(+), 13 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 14f2b0b4ed5e..5286a480f76b 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -52,17 +52,17 @@ /* IRQ register defines */ #define IRQ_EOI 0x050 -#define IRQ_STATUS 0x184 -#define IRQ_ENABLE_SET 0x188 -#define IRQ_ENABLE_CLR 0x18c #define MSI_IRQ 0x054 -#define MSI0_IRQ_STATUS 0x104 -#define MSI0_IRQ_ENABLE_SET 0x108 -#define MSI0_IRQ_ENABLE_CLR 0x10c -#define IRQ_STATUS 0x184 +#define MSI_IRQ_STATUS(n) (0x104 + ((n) << 4)) +#define MSI_IRQ_ENABLE_SET(n) (0x108 + ((n) << 4)) +#define MSI_IRQ_ENABLE_CLR(n) (0x10c + ((n) << 4)) #define MSI_IRQ_OFFSET 4 +#define IRQ_STATUS(n) (0x184 + ((n) << 4)) +#define IRQ_ENABLE_SET(n) (0x188 + ((n) << 4)) +#define INTx_EN BIT(0) + #define ERR_IRQ_STATUS 0x1c4 #define ERR_IRQ_ENABLE_SET 0x1c8 #define ERR_AER BIT(5) /* ECRC error */ @@ -142,7 +142,7 @@ static void ks_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset) u32 pending, vector; int src, virq; - pending = ks_pcie_app_readl(ks_pcie, MSI0_IRQ_STATUS + (offset << 4)); + pending = ks_pcie_app_readl(ks_pcie, MSI_IRQ_STATUS(offset)); /* * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit @@ -169,7 +169,7 @@ static void ks_pcie_msi_irq_ack(int irq, struct pcie_port *pp) ks_pcie = to_keystone_pcie(pci); update_reg_offset_bit_pos(irq, ®_offset, &bit_pos); - ks_pcie_app_writel(ks_pcie, MSI0_IRQ_STATUS + (reg_offset << 4), + ks_pcie_app_writel(ks_pcie, MSI_IRQ_STATUS(reg_offset), BIT(bit_pos)); ks_pcie_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET); } @@ -181,7 +181,7 @@ static void ks_pcie_msi_set_irq(struct pcie_port *pp, int irq) struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); update_reg_offset_bit_pos(irq, ®_offset, &bit_pos); - ks_pcie_app_writel(ks_pcie, MSI0_IRQ_ENABLE_SET + (reg_offset << 4), + ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset), BIT(bit_pos)); } @@ -192,7 +192,7 @@ static void ks_pcie_msi_clear_irq(struct pcie_port *pp, int irq) struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); update_reg_offset_bit_pos(irq, ®_offset, &bit_pos); - ks_pcie_app_writel(ks_pcie, MSI0_IRQ_ENABLE_CLR + (reg_offset << 4), + ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset), BIT(bit_pos)); } @@ -206,7 +206,7 @@ static void ks_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie) int i; for (i = 0; i < PCI_NUM_INTX; i++) - ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET + (i << 4), 0x1); + ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET(i), 0x1); } static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, @@ -217,7 +217,7 @@ static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, u32 pending; int virq; - pending = ks_pcie_app_readl(ks_pcie, IRQ_STATUS + (offset << 4)); + pending = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(offset)); if (BIT(0) & pending) { virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset); From patchwork Wed Dec 19 12:41:59 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 154258 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4890404ljp; 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Since there is nothing to do in the irqchip callback functions, use handle_simple_irq instead of handle_level_irq. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 24 ++--------------------- 1 file changed, 2 insertions(+), 22 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 5286a480f76b..1ef443009da5 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -266,31 +266,12 @@ static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie) return IRQ_HANDLED; } -static void ks_pcie_ack_legacy_irq(struct irq_data *d) -{ -} - -static void ks_pcie_mask_legacy_irq(struct irq_data *d) -{ -} - -static void ks_pcie_unmask_legacy_irq(struct irq_data *d) -{ -} - -static struct irq_chip ks_pcie_legacy_irq_chip = { - .name = "Keystone-PCI-Legacy-IRQ", - .irq_ack = ks_pcie_ack_legacy_irq, - .irq_mask = ks_pcie_mask_legacy_irq, - .irq_unmask = ks_pcie_unmask_legacy_irq, -}; - static int ks_pcie_init_legacy_irq_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw_irq) { - irq_set_chip_and_handler(irq, &ks_pcie_legacy_irq_chip, - handle_level_irq); + irq_set_chip_and_handler(irq, &dummy_irq_chip, + handle_simple_irq); irq_set_chip_data(irq, d->host_data); return 0; @@ -298,7 +279,6 @@ static int ks_pcie_init_legacy_irq_map(struct irq_domain *d, static const struct irq_domain_ops ks_pcie_legacy_irq_domain_ops = { .map = ks_pcie_init_legacy_irq_map, - .xlate = irq_domain_xlate_onetwocell, }; /** From patchwork Wed Dec 19 12:42:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 154259 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4890494ljp; Wed, 19 Dec 2018 04:43:03 -0800 (PST) X-Google-Smtp-Source: AFSGD/UYKd8Y68KGbleFcJ8xnRBCz4/xBWHN+DoiXsLDkdm5z4QANoM3X0kOHce/jOT6v7m/NBNj X-Received: by 2002:a17:902:722:: with SMTP id 31mr20237612pli.271.1545223383235; Wed, 19 Dec 2018 04:43:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545223383; cv=none; d=google.com; s=arc-20160816; b=j3hL/IPz4O1eG22GPpCgsU7UZsZl9L/4fxX/R6+5/sES7F9jxSq+o3I6+5pE8ayTRP AEnblZB/QfnAxfebWuYO0NYe9NTPbi9P/4ZKIqH0BY27TpyPY0RYF7jP6VGtOXdvS7Ok OD9R04OtrMsL7d2Y2kJOwjCbzft/8ze3ns2aKVOKq8nKEAFLfCoIjFR+khS8Ufsq72k8 MS+lEHZhQ26b2ozGMY0r4hVS4TMzrhk2JBPVrqNF6ecXyh3FBf6RWzYlzyxCIsBqBan4 wiI7t4Swx/oRmAOl7/Xzec6YLSFacewtT640IRgpFRjF8XvlMcqcWKINnA9LlfJpz+6q U7iw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=/mryJEnDKpkn8c9z8vkT/gef1dG7mXbfXz/QOxGPW7c=; b=ZK9cGocmUY3YyF1uu/GNFp+bMhc53E32t7YXXSDmzpyVlSBZlxIzOdHQ2Bh8QqZRf7 gv9SVnq9nqcfs/D+yc6OR7CEVoxXU3Add+rYXJUIWlaTWMOeSvK0nGvJKkP7/Y+CDYNe KdAOgsDqWzzvRkNcn1te9gosavIHqehEYOrdqL1ivVeG2Sp8kYUuuh8K8+XNnrNcqCAh CLi+7UnEhFg7May0UI3ILsC/m5pXcuqy4pVHizbWepGg0kAXyjQX/6bKJGnfVI6fOepI 9eosYjuRHAWeFSDV3h1BZvvHAab1TJ0LzEQiXhCNsHl0kPqwKtqQUCyPmeAds3QLPAVj 5yHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="Xt0aO/qC"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c7si15250595plz.118.2018.12.19.04.43.02; Wed, 19 Dec 2018 04:43:03 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="Xt0aO/qC"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729753AbeLSMmu (ORCPT + 31 others); Wed, 19 Dec 2018 07:42:50 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:54700 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729726AbeLSMms (ORCPT ); Wed, 19 Dec 2018 07:42:48 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id wBJCgafD098484; Wed, 19 Dec 2018 06:42:36 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1545223356; bh=/mryJEnDKpkn8c9z8vkT/gef1dG7mXbfXz/QOxGPW7c=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Xt0aO/qCvm1jPcl/uy0Dw1olZC3RzKQaWI0I1dE50ZjJeAun+tzmrUSNI5WuNEhxR /PfqQTLIqUFTe+Wmz0pzgH+VDCuZKc7YKv1v+V9cWPsJAYCTbfxtZMlOlpKgprl01+ cOOjet7DzDeP5n/WuA0fTJ+LDu8ccN9xgp+bVhHg= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wBJCga72034588 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 19 Dec 2018 06:42:36 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Wed, 19 Dec 2018 06:42:36 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Wed, 19 Dec 2018 06:42:36 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wBJCgNZm003940; Wed, 19 Dec 2018 06:42:33 -0600 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi , Gustavo Pimentel , Marc Zyngier CC: Bjorn Helgaas , Jingoo Han , , , , Subject: [PATCH 03/10] PCI: keystone: Modify legacy_irq_handler to check the IRQ_STATUS of INTA/B/C/D Date: Wed, 19 Dec 2018 18:12:00 +0530 Message-ID: <20181219124207.13479-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181219124207.13479-1-kishon@ti.com> References: <20181219124207.13479-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The legacy interrupt handler directly checks the IRQ_STATUS register corresponding to a interrupt line inorder to invoke generic_handle_irq. While this is okay for K2G platform which has separate interrupt line for each of the 4 legacy interrupts, AM654 which uses the same PCIe wrapper has a single interrupt line for all the legacy interrupts. So for AM654 the interrupt handler won't be able to directly check the IRQ_STATUS register corresponding to the interrupt line. Also the legacy interrupt handler uses 'virq' obtained from irq_of_parse_and_map to find the correct interrupt line which raised the interrupt. There is no guarantee that virq assigned for contiguous hardware irq will be contiguous and the interrupt handler might end up checking the wrong IRQ_STATUS register. In order to overcome the above issues, read the IRQ_STATUS register of all the 4 legacy interrupts to determine which interrupt was raised. Link: https://lkml.kernel.org/r/bb081d21-7c03-0357-4294-7e92d95d838c@arm.com Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 1ef443009da5..e9f5387136f0 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -214,16 +214,11 @@ static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, { struct dw_pcie *pci = ks_pcie->pci; struct device *dev = pci->dev; - u32 pending; int virq; - pending = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(offset)); - - if (BIT(0) & pending) { - virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset); - dev_dbg(dev, ": irq: irq_offset %d, virq %d\n", offset, virq); - generic_handle_irq(virq); - } + virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset); + dev_dbg(dev, ": irq: irq_offset %d, virq %d\n", offset, virq); + generic_handle_irq(virq); /* EOI the INTx interrupt */ ks_pcie_app_writel(ks_pcie, IRQ_EOI, offset); @@ -587,8 +582,9 @@ static void ks_pcie_legacy_irq_handler(struct irq_desc *desc) struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); struct dw_pcie *pci = ks_pcie->pci; struct device *dev = pci->dev; - u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0]; struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned int irq_no; + u32 reg; dev_dbg(dev, ": Handling legacy irq %d\n", irq); @@ -598,7 +594,13 @@ static void ks_pcie_legacy_irq_handler(struct irq_desc *desc) * ack operation. */ chained_irq_enter(chip, desc); - ks_pcie_handle_legacy_irq(ks_pcie, irq_offset); + for (irq_no = 0; irq_no < PCI_NUM_INTX; irq_no++) { + reg = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(irq_no)); + if (!(reg & INTx_EN)) + continue; + ks_pcie_handle_legacy_irq(ks_pcie, irq_no); + } + chained_irq_exit(chip, desc); } From patchwork Wed Dec 19 12:42:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 154267 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4898102ljp; Wed, 19 Dec 2018 04:51:41 -0800 (PST) X-Google-Smtp-Source: AFSGD/UpeLTol70t5Rhi7nGLIxebkRt6g700rS+0dt2wCuFzjteuC4540EWYegC6ToeEQ0h4I7gw X-Received: by 2002:a63:8f45:: with SMTP id r5mr19163347pgn.222.1545223901425; Wed, 19 Dec 2018 04:51:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545223901; cv=none; d=google.com; s=arc-20160816; b=Q3W3uOJwEvK1tPVyvpOWHrk7wP1GQ26rgOica04qx3/x7n59GtzH0q7wf02VzaLLR0 tmIFkGOgndG/ZZ/w38tJAwmhB623D7MPeowwyLW7uim1baqffZSXJp3Gj5KAwhn3jmeQ qIhlo8fC5ErySlTYOiYenOmIjdqdGcoSjEBxmp4shDMBYmbhaMoGMl2szJyvXlrdnSpM NeneWpN6jS/Jl4aGcnywkR7/Rl/l9cGhJpVIClSAUeEE1OAKg0qh65hGqlgtvoMUmcbz 97nxR++smTvRyW9WQhej23uXW4Qp7s7wMJ7bb1zEU32h3vgwdibwcypwahHglKchbW09 bLTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=mbbb79Ac8cqndqKQy/QFEfwpSj42VwCaCqlC/i9Zp2c=; b=VRELOkyz0dlAo6oE60SNTqueYb98YMNow6D6m5yt4dWQVtBLqiqxBXUaxsxwGkw6sn 4hvnwsSeT9hZx0CLnFGynEXSJtBq1xjUnab6DyXn1Z88yz1QIhpw/JtzH83qwQuzWN5D ZJH0nURkITp1ZFqTzsOBS2FXLCGCxzqaSiVXi4ALo8GPBQVwqmUozLakfvoRJq3NZ4eq lzXMIHHmr4J2aen0Yd1urz9Vw6cAVNH0FxLwY54ML1OcCSNEErEV5PR+GZwDBurdQBQj fFdNx0Nwx8g2yBs/RZCq9lUd6PnkCkL2QIsIrhzFTHf+pIvwNa60FcujClRmQNyOyl7c A6Ig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=DHjXmfM1; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r25si16982356pfk.28.2018.12.19.04.51.40; Wed, 19 Dec 2018 04:51:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=DHjXmfM1; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728373AbeLSMvi (ORCPT + 31 others); Wed, 19 Dec 2018 07:51:38 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:56440 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726833AbeLSMvi (ORCPT ); Wed, 19 Dec 2018 07:51:38 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id wBJCgdeJ098490; Wed, 19 Dec 2018 06:42:39 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1545223359; bh=mbbb79Ac8cqndqKQy/QFEfwpSj42VwCaCqlC/i9Zp2c=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=DHjXmfM1Gctgvkg4S6lQC/uvJ9hHs2jAOBnAMEuyXSUHxQCEGztVY1WBSFqdeKXuj hbidjtzBuVSc6j8jfkRN9NdQcT7MxzFCALRBTk1F0cANRsl1BdHnf2zq0ZA7NYkfmA sRGwTftne+lzgFpJof4kNKakjfRBwNLgS2e/V5UI= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wBJCgd5u062324 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 19 Dec 2018 06:42:39 -0600 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Wed, 19 Dec 2018 06:42:39 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Wed, 19 Dec 2018 06:42:39 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wBJCgNZn003940; Wed, 19 Dec 2018 06:42:36 -0600 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi , Gustavo Pimentel , Marc Zyngier CC: Bjorn Helgaas , Jingoo Han , , , , Subject: [PATCH 04/10] PCI: keystone: Add separate functions for configuring MSI and legacy interrupt Date: Wed, 19 Dec 2018 18:12:01 +0530 Message-ID: <20181219124207.13479-5-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181219124207.13479-1-kishon@ti.com> References: <20181219124207.13479-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ks_pcie_get_irq_controller_info() was used to configure both MSI and legacy interrupt. This will prevent MSI or legacy interrupt specific intializations. Add separate functions to configure MSI and legacy interrupts. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 188 +++++++++++----------- 1 file changed, 96 insertions(+), 92 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index e9f5387136f0..a8712804c891 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -87,11 +87,8 @@ struct keystone_pcie { struct dw_pcie *pci; /* PCI Device ID */ u32 device_id; - int num_legacy_host_irqs; - int legacy_host_irqs[PCI_NUM_INTX]; struct device_node *legacy_intc_np; - int num_msi_host_irqs; int msi_host_irqs[MAX_MSI_HOST_IRQS]; int num_lanes; u32 num_viewport; @@ -201,14 +198,6 @@ static int ks_pcie_msi_host_init(struct pcie_port *pp) return dw_pcie_allocate_domains(pp); } -static void ks_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie) -{ - int i; - - for (i = 0; i < PCI_NUM_INTX; i++) - ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET(i), 0x1); -} - static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, int offset) { @@ -470,17 +459,6 @@ static int __init ks_pcie_dw_host_init(struct keystone_pcie *ks_pcie) ks_pcie->app = *res; - /* Create legacy IRQ domain */ - ks_pcie->legacy_irq_domain = - irq_domain_add_linear(ks_pcie->legacy_intc_np, - PCI_NUM_INTX, - &ks_pcie_legacy_irq_domain_ops, - NULL); - if (!ks_pcie->legacy_irq_domain) { - dev_err(dev, "Failed to add irq domain for legacy irqs\n"); - return -EINVAL; - } - return dw_pcie_host_init(pp); } @@ -604,85 +582,117 @@ static void ks_pcie_legacy_irq_handler(struct irq_desc *desc) chained_irq_exit(chip, desc); } -static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie, - char *controller, int *num_irqs) +static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie) { - int temp, max_host_irqs, legacy = 1, *host_irqs; struct device *dev = ks_pcie->pci->dev; - struct device_node *np_pcie = dev->of_node, **np_temp; - - if (!strcmp(controller, "msi-interrupt-controller")) - legacy = 0; - - if (legacy) { - np_temp = &ks_pcie->legacy_intc_np; - max_host_irqs = PCI_NUM_INTX; - host_irqs = &ks_pcie->legacy_host_irqs[0]; - } else { - np_temp = &ks_pcie->msi_intc_np; - max_host_irqs = MAX_MSI_HOST_IRQS; - host_irqs = &ks_pcie->msi_host_irqs[0]; - } + struct device_node *np = ks_pcie->np; + struct device_node *intc_np; + int irq_count; + int irq; + int ret; + int i; - /* interrupt controller is in a child node */ - *np_temp = of_get_child_by_name(np_pcie, controller); - if (!(*np_temp)) { - dev_err(dev, "Node for %s is absent\n", controller); - return -EINVAL; - } + if (!IS_ENABLED(CONFIG_PCI_MSI)) + return 0; - temp = of_irq_count(*np_temp); - if (!temp) { - dev_err(dev, "No IRQ entries in %s\n", controller); - of_node_put(*np_temp); + intc_np = of_get_child_by_name(np, "msi-interrupt-controller"); + if (!intc_np) { + dev_WARN(dev, "msi-interrupt-controller node is absent\n"); return -EINVAL; } - if (temp > max_host_irqs) - dev_warn(dev, "Too many %s interrupts defined %u\n", - (legacy ? "legacy" : "MSI"), temp); + irq_count = of_irq_count(intc_np); + if (!irq_count) { + dev_err(dev, "No IRQ entries in msi-interrupt-controller\n"); + ret = -EINVAL; + goto err; + } - /* - * support upto max_host_irqs. In dt from index 0 to 3 (legacy) or 0 to - * 7 (MSI) - */ - for (temp = 0; temp < max_host_irqs; temp++) { - host_irqs[temp] = irq_of_parse_and_map(*np_temp, temp); - if (!host_irqs[temp]) - break; + if (irq_count > MAX_MSI_HOST_IRQS) { + dev_warn(dev, "Too many MSI interrupt lines defined %u\n", + irq_count); + irq_count = MAX_MSI_HOST_IRQS; } - of_node_put(*np_temp); + for (i = 0; i < irq_count; i++) { + irq = irq_of_parse_and_map(intc_np, i); + if (!irq) { + ret = -EINVAL; + goto err; + } + ks_pcie->msi_host_irqs[i] = irq; - if (temp) { - *num_irqs = temp; - return 0; + irq_set_chained_handler_and_data(irq, ks_pcie_msi_irq_handler, + ks_pcie); } - return -EINVAL; + of_node_put(intc_np); + return 0; + +err: + of_node_put(intc_np); + return ret; } -static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie) +static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie) { + struct device *dev = ks_pcie->pci->dev; + struct irq_domain *legacy_irq_domain; + struct device_node *np = ks_pcie->np; + struct device_node *intc_np; + int irq_count; + int irq; + int ret; int i; - /* Legacy IRQ */ - for (i = 0; i < ks_pcie->num_legacy_host_irqs; i++) { - irq_set_chained_handler_and_data(ks_pcie->legacy_host_irqs[i], + intc_np = of_get_child_by_name(np, "legacy-interrupt-controller"); + if (!intc_np) { + dev_WARN(dev, "legacy-interrupt-controller node is absent\n"); + return -EINVAL; + } + + irq_count = of_irq_count(intc_np); + if (!irq_count) { + dev_err(dev, "No IRQ entries in legacy-interrupt-controller\n"); + ret = -EINVAL; + goto err; + } + + for (i = 0; i < irq_count; i++) { + irq = irq_of_parse_and_map(intc_np, i); + if (!irq) { + ret = -EINVAL; + goto err; + } + irq_set_chained_handler_and_data(irq, ks_pcie_legacy_irq_handler, ks_pcie); } - ks_pcie_enable_legacy_irqs(ks_pcie); - - /* MSI IRQ */ - if (IS_ENABLED(CONFIG_PCI_MSI)) { - for (i = 0; i < ks_pcie->num_msi_host_irqs; i++) { - irq_set_chained_handler_and_data(ks_pcie->msi_host_irqs[i], - ks_pcie_msi_irq_handler, - ks_pcie); - } + + legacy_irq_domain = + irq_domain_add_linear(intc_np, PCI_NUM_INTX, + &ks_pcie_legacy_irq_domain_ops, NULL); + if (!legacy_irq_domain) { + dev_err(dev, "Failed to add irq domain for legacy irqs\n"); + ret = -EINVAL; + goto err; } + ks_pcie->legacy_irq_domain = legacy_irq_domain; + + for (i = 0; i < PCI_NUM_INTX; i++) + ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET(i), INTx_EN); + + of_node_put(intc_np); + + return 0; + +err: + of_node_put(intc_np); + return ret; +} +static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie) +{ if (ks_pcie->error_irq > 0) ks_pcie_enable_error_irq(ks_pcie); } @@ -736,6 +746,14 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); int ret; + ret = ks_pcie_config_legacy_irq(ks_pcie); + if (ret) + return ret; + + ret = ks_pcie_config_msi_irq(ks_pcie); + if (ret) + return ret; + dw_pcie_setup_rc(pp); ks_pcie_establish_link(ks_pcie); @@ -785,20 +803,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, struct device *dev = &pdev->dev; int ret; - ret = ks_pcie_get_irq_controller_info(ks_pcie, - "legacy-interrupt-controller", - &ks_pcie->num_legacy_host_irqs); - if (ret) - return ret; - - if (IS_ENABLED(CONFIG_PCI_MSI)) { - ret = ks_pcie_get_irq_controller_info(ks_pcie, - "msi-interrupt-controller", - &ks_pcie->num_msi_host_irqs); - if (ret) - return ret; - } - /* * Index 0 is the platform interrupt for error interrupt * from RC. This is optional. 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[209.132.180.67]) by mx.google.com with ESMTP id v141si17544927pfc.260.2018.12.19.04.43.45; Wed, 19 Dec 2018 04:43:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=fgDBsGKL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729834AbeLSMnO (ORCPT + 31 others); Wed, 19 Dec 2018 07:43:14 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:54850 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729796AbeLSMnJ (ORCPT ); Wed, 19 Dec 2018 07:43:09 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id wBJCgg3d098497; Wed, 19 Dec 2018 06:42:42 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1545223362; bh=aGKggKrre68tpewZr9QnXh/i5cUBcmHQ2TJDpEiqdgk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fgDBsGKLiEWFeZ0Qd2X6bXgfIdVvHuUuf3tBXtKMxJ54ywWCtLvg6CIk0LtFTq6TM UbVFhXlfPVIrF/JhzrKhOF4N7uN2rwnKyLPED9I61jc5xNNd2aPkb0PoCVKMRAmWNg lAo8q8vkKyzEcTOLF4PXUwLhxkP0KoCd1UusXbA4= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wBJCggpA040985 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 19 Dec 2018 06:42:42 -0600 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Wed, 19 Dec 2018 06:42:42 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Wed, 19 Dec 2018 06:42:42 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wBJCgNZo003940; Wed, 19 Dec 2018 06:42:39 -0600 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi , Gustavo Pimentel , Marc Zyngier CC: Bjorn Helgaas , Jingoo Han , , , , Subject: [PATCH 05/10] PCI: keystone: Use hwirq to get the IRQ number offset Date: Wed, 19 Dec 2018 18:12:02 +0530 Message-ID: <20181219124207.13479-6-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181219124207.13479-1-kishon@ti.com> References: <20181219124207.13479-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ks_pcie_msi_irq_handler() uses 'virq' to get the IRQ number offset. This offset is used to get the correct MSI_IRQ_STATUS register corresponding to the IRQ line that raised the interrupt. There is no guarantee that 'virq' assigned for consecutive hardware IRQ will be contiguous. And this might get us an incorrect IRQ number offset. Fix it here by using 'hwirq' to get the IRQ number offset. Since we don't store the 'virq' numbers of all the IRQ numbers, stop checking if irq count is greater than MAX_MSI_HOST_IRQS and remove MAX_MSI_HOST_IRQS. Link: https://lkml.kernel.org/r/bb081d21-7c03-0357-4294-7e92d95d838c@arm.com Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 24 ++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index a8712804c891..8a78307dac99 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -74,7 +74,6 @@ #define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \ ERR_NONFATAL | ERR_FATAL | ERR_SYS) -#define MAX_MSI_HOST_IRQS 8 /* PCIE controller device IDs */ #define PCIE_RC_K2HK 0xb008 #define PCIE_RC_K2E 0xb009 @@ -89,7 +88,7 @@ struct keystone_pcie { u32 device_id; struct device_node *legacy_intc_np; - int msi_host_irqs[MAX_MSI_HOST_IRQS]; + int msi_host_irq; int num_lanes; u32 num_viewport; struct phy **phy; @@ -527,9 +526,9 @@ static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie) static void ks_pcie_msi_irq_handler(struct irq_desc *desc) { - unsigned int irq = irq_desc_get_irq(desc); + unsigned int irq = desc->irq_data.hwirq; struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); - u32 offset = irq - ks_pcie->msi_host_irqs[0]; + u32 offset = irq - ks_pcie->msi_host_irq; struct dw_pcie *pci = ks_pcie->pci; struct device *dev = pci->dev; struct irq_chip *chip = irq_desc_get_chip(desc); @@ -587,6 +586,7 @@ static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie) struct device *dev = ks_pcie->pci->dev; struct device_node *np = ks_pcie->np; struct device_node *intc_np; + struct irq_data *irq_data; int irq_count; int irq; int ret; @@ -608,19 +608,21 @@ static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie) goto err; } - if (irq_count > MAX_MSI_HOST_IRQS) { - dev_warn(dev, "Too many MSI interrupt lines defined %u\n", - irq_count); - irq_count = MAX_MSI_HOST_IRQS; - } - for (i = 0; i < irq_count; i++) { irq = irq_of_parse_and_map(intc_np, i); if (!irq) { ret = -EINVAL; goto err; } - ks_pcie->msi_host_irqs[i] = irq; + + if (!ks_pcie->msi_host_irq) { + irq_data = irq_get_irq_data(irq); + if (!irq_data) { + ret = -EINVAL; + goto err; + } + ks_pcie->msi_host_irq = irq_data->hwirq; + } irq_set_chained_handler_and_data(irq, ks_pcie_msi_irq_handler, ks_pcie); From patchwork Wed Dec 19 12:42:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 154261 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4890718ljp; Wed, 19 Dec 2018 04:43:18 -0800 (PST) X-Google-Smtp-Source: AFSGD/VbGp+R+6nFSXj35JdqOmnzgXH87BbUKqkZp94V1/gRp4lVbwJmeWblrZFoQk7zx9hOOCQK X-Received: by 2002:a17:902:145:: with SMTP id 63mr20106670plb.256.1545223397860; Wed, 19 Dec 2018 04:43:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545223397; cv=none; d=google.com; s=arc-20160816; b=IdMLB0m3Rx2Gh7dhV+0A1D7UcvQXy2YcODLu+kup7eHYzksvBXwRHsFJYTnLfij51K DQKgEHJdvvIz6srUUfpMSnSr4IOcsCpI9JmT+4Fj5RfRbayC/XwWQPB1q9sP/R4uVymh XrSycKzRrenTTHHUNhmcgSgPDgt9l2VHGzbTiAcWAL2DlSwPjrEHJeInjh/VhP6VYIqx +uJvrl9dGH8tOrCytwvRw/j51PiMK8rf5YlfIr2d6FGe25LX/rYlExEw4q+KDOkFs11c qwJRBpvkH+hMUZzUmX1fN1wn+ahggccpZJO9w98Nc2R7FRKZ2neRTZ9CEq/lG3q3iTFV XV+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=ztM8Irs9LmeJGtLm8EUU626+/KaAZ0J8xx9JifReD64=; b=L/DJ50IfU2ttdcwylSKnCF+9MFvKEO07XSrWMabpQs/W7rlxiiy/LJ3Og5Fc9oDVTZ 7BRNL/Wgbiv0BnvlN9dbqxR60Pec9P892/8qrBbJhtZpwwKXRYyyrn59wig04+zEo0Ra pFb5t+/oIuVsDMhBsY7lqQLwIRLNhhqJS8fnt4r/IohWTZHsSKfS6RbqnIXwAy4zyFc5 EM+8KyVV5aNEPQ+xFttEmqnaFQ0gKQmCcdo2ORkkQtHpRIL4i/5O4kSmown56SSkwX0s 9vvHgJAjiUl2eXZj1OJqeYekcFFPT8r4KRAQ/4Wmr33RTNyWIjZJdc+BQ5QwNhKT1Jzo 6Skg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=X2ZCWBtl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b7si15858984plk.206.2018.12.19.04.43.17; Wed, 19 Dec 2018 04:43:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=X2ZCWBtl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729848AbeLSMnQ (ORCPT + 31 others); Wed, 19 Dec 2018 07:43:16 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:59924 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729825AbeLSMnN (ORCPT ); Wed, 19 Dec 2018 07:43:13 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id wBJCgjoZ123351; Wed, 19 Dec 2018 06:42:45 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1545223365; bh=ztM8Irs9LmeJGtLm8EUU626+/KaAZ0J8xx9JifReD64=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=X2ZCWBtlbPZsOKOF8Whmbqwy4ejfsaQ6+amRnwugqHLntjdovE4TxCjNq7gt+HdJy kY+fDfIoImE6JFVuOq/4q++2AP6weGXHbxe6TCc1js8OX/HNyo4YzBCSZ4ZQJTw500 YJils+qZflqYlfs48MtdKPCSV4phIJMyoo5EnQR8= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wBJCgjmp041006 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 19 Dec 2018 06:42:45 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Wed, 19 Dec 2018 06:42:45 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Wed, 19 Dec 2018 06:42:45 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wBJCgNZp003940; Wed, 19 Dec 2018 06:42:42 -0600 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi , Gustavo Pimentel , Marc Zyngier CC: Bjorn Helgaas , Jingoo Han , , , , Subject: [PATCH 06/10] PCI: keystone: Cleanup ks_pcie_msi_irq_handler and ks_pcie_legacy_irq_handler Date: Wed, 19 Dec 2018 18:12:03 +0530 Message-ID: <20181219124207.13479-7-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181219124207.13479-1-kishon@ti.com> References: <20181219124207.13479-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Both ks_pcie_msi_irq_handler() and ks_pcie_legacy_irq_handler() invokes ks_pcie_handle_msi_irq() and ks_pcie_handle_legacy_irq() respectively for handling the interrupts. Having two functions for handling the interrupt was used when keystone PCIe driver was implemented using two files. But with commit b492aca35c982011500377797d2 ("PCI: keystone: Merge pci-keystone-dw.c and pci-keystone.c"), which merged the keystone PCIe driver to use a single file, two functions for handling the interrupt handler is not required. Handle both MSI interrupt and legacy interrupt in a single interrupt handler here. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 92 ++++++++++------------- 1 file changed, 39 insertions(+), 53 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 8a78307dac99..05b2bd613c68 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -104,13 +104,6 @@ struct keystone_pcie { struct resource app; }; -static inline void update_reg_offset_bit_pos(u32 offset, u32 *reg_offset, - u32 *bit_pos) -{ - *reg_offset = offset % 8; - *bit_pos = offset >> 3; -} - static phys_addr_t ks_pcie_get_msi_addr(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -130,31 +123,6 @@ static void ks_pcie_app_writel(struct keystone_pcie *ks_pcie, u32 offset, writel(val, ks_pcie->va_app_base + offset); } -static void ks_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset) -{ - struct dw_pcie *pci = ks_pcie->pci; - struct pcie_port *pp = &pci->pp; - struct device *dev = pci->dev; - u32 pending, vector; - int src, virq; - - pending = ks_pcie_app_readl(ks_pcie, MSI_IRQ_STATUS(offset)); - - /* - * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit - * shows 1, 9, 17, 25 and so forth - */ - for (src = 0; src < 4; src++) { - if (BIT(src) & pending) { - vector = offset + (src << 3); - virq = irq_linear_revmap(pp->irq_domain, vector); - dev_dbg(dev, "irq: bit %d, vector %d, virq %d\n", - src, vector, virq); - generic_handle_irq(virq); - } - } -} - static void ks_pcie_msi_irq_ack(int irq, struct pcie_port *pp) { u32 reg_offset, bit_pos; @@ -163,7 +131,9 @@ static void ks_pcie_msi_irq_ack(int irq, struct pcie_port *pp) pci = to_dw_pcie_from_pp(pp); ks_pcie = to_keystone_pcie(pci); - update_reg_offset_bit_pos(irq, ®_offset, &bit_pos); + + reg_offset = irq % 8; + bit_pos = irq >> 3; ks_pcie_app_writel(ks_pcie, MSI_IRQ_STATUS(reg_offset), BIT(bit_pos)); @@ -176,7 +146,9 @@ static void ks_pcie_msi_set_irq(struct pcie_port *pp, int irq) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); - update_reg_offset_bit_pos(irq, ®_offset, &bit_pos); + reg_offset = irq % 8; + bit_pos = irq >> 3; + ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset), BIT(bit_pos)); } @@ -187,7 +159,9 @@ static void ks_pcie_msi_clear_irq(struct pcie_port *pp, int irq) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); - update_reg_offset_bit_pos(irq, ®_offset, &bit_pos); + reg_offset = irq % 8; + bit_pos = irq >> 3; + ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset), BIT(bit_pos)); } @@ -197,21 +171,6 @@ static int ks_pcie_msi_host_init(struct pcie_port *pp) return dw_pcie_allocate_domains(pp); } -static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, - int offset) -{ - struct dw_pcie *pci = ks_pcie->pci; - struct device *dev = pci->dev; - int virq; - - virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset); - dev_dbg(dev, ": irq: irq_offset %d, virq %d\n", offset, virq); - generic_handle_irq(virq); - - /* EOI the INTx interrupt */ - ks_pcie_app_writel(ks_pcie, IRQ_EOI, offset); -} - static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) { ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); @@ -530,8 +489,13 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc) struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); u32 offset = irq - ks_pcie->msi_host_irq; struct dw_pcie *pci = ks_pcie->pci; + struct pcie_port *pp = &pci->pp; struct device *dev = pci->dev; struct irq_chip *chip = irq_desc_get_chip(desc); + u32 vector; + u32 virq; + u32 reg; + u32 pos; dev_dbg(dev, "%s, irq %d\n", __func__, irq); @@ -541,7 +505,23 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc) * ack operation. */ chained_irq_enter(chip, desc); - ks_pcie_handle_msi_irq(ks_pcie, offset); + + reg = ks_pcie_app_readl(ks_pcie, MSI_IRQ_STATUS(offset)); + /* + * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit + * shows 1, 9, 17, 25 and so forth + */ + for (pos = 0; pos < 4; pos++) { + if (!(reg & BIT(pos))) + continue; + + vector = offset + (pos << 3); + virq = irq_linear_revmap(pp->irq_domain, vector); + dev_dbg(dev, "irq: bit %d, vector %d, virq %d\n", pos, vector, + virq); + generic_handle_irq(virq); + } + chained_irq_exit(chip, desc); } @@ -561,6 +541,7 @@ static void ks_pcie_legacy_irq_handler(struct irq_desc *desc) struct device *dev = pci->dev; struct irq_chip *chip = irq_desc_get_chip(desc); unsigned int irq_no; + u32 virq; u32 reg; dev_dbg(dev, ": Handling legacy irq %d\n", irq); @@ -575,9 +556,14 @@ static void ks_pcie_legacy_irq_handler(struct irq_desc *desc) reg = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(irq_no)); if (!(reg & INTx_EN)) continue; - ks_pcie_handle_legacy_irq(ks_pcie, irq_no); - } + virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, irq_no); + dev_dbg(dev, ": irq: irq_offset %d, virq %d\n", irq_no, virq); + generic_handle_irq(virq); + + /* EOI the INTx interrupt */ + ks_pcie_app_writel(ks_pcie, IRQ_EOI, irq_no); + } chained_irq_exit(chip, desc); } From patchwork Wed Dec 19 12:42:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 154260 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4890652ljp; Wed, 19 Dec 2018 04:43:13 -0800 (PST) X-Google-Smtp-Source: AFSGD/VC7I2h9rNPzLY228lMmEq08ZktTkeTLbGzsDDSq2AFsp0yJAxkteQ6be+g/yuWeDr9Tr6C X-Received: by 2002:a17:902:887:: with SMTP id 7mr19987140pll.164.1545223393140; Wed, 19 Dec 2018 04:43:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545223393; cv=none; d=google.com; s=arc-20160816; b=bLNwRjWMu5cNw8GmPJHar9hHjkjLv8q9n6iOpStOcue79yBfArVs6pl61tIXoyP8t6 hvW4d/vxRQGAQ717Rpixxnfj21hQy7yJ+TQbUMw6acpeV9JKiKPmyw6V1WAae9u8Yn97 tw7ggZuuyjCWTdTX+h6LDUwd7gzA3+zeMPzIWpWumdT+BcdZ7190EsmR+CLnTLD6yRtp NFFQLqPHkH//V1qR7shnWjN0Y7ZZB+opzeNFV5nihRSZ7Np+Nj4gATa/jDRxF12sXuhx ogcv2kvQyEyzHbQQBqZoh4UHYUZD8+hGwkkbF5pp58Mx+iIGfKVu6NXKet5Uovjs26sm ytlA== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id b7si15858984plk.206.2018.12.19.04.43.12; Wed, 19 Dec 2018 04:43:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=cN0HBEVN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729818AbeLSMnL (ORCPT + 31 others); Wed, 19 Dec 2018 07:43:11 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:54848 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729795AbeLSMnI (ORCPT ); Wed, 19 Dec 2018 07:43:08 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id wBJCgmIb098512; Wed, 19 Dec 2018 06:42:48 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1545223369; bh=2Znl2d3jLCrX2Ss1Y7tIZm8c5dh8/ypWE14F2Dg39vw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=cN0HBEVN3hmW5fAJ4//i8TIpO2Uq1VPFjduNZEFAw4DShguZl/Ma0+ybS518Kn9KI 3sW9mLXBKH1Jf+dEPs7LFIc1YVnKouteFJdURXnCFDxNfdw/WHqe8X8Thys2ugbFSd 9FblDf/u0bscEcpZ1VtkrrXrl+Q2eTqGTn2RGtLA= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wBJCgmI6034691 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 19 Dec 2018 06:42:48 -0600 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Wed, 19 Dec 2018 06:42:48 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Wed, 19 Dec 2018 06:42:48 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wBJCgNZq003940; Wed, 19 Dec 2018 06:42:45 -0600 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi , Gustavo Pimentel , Marc Zyngier CC: Bjorn Helgaas , Jingoo Han , , , , Subject: [PATCH 07/10] PCI: dwc: Add support to use non default msi_irq_chip Date: Wed, 19 Dec 2018 18:12:04 +0530 Message-ID: <20181219124207.13479-8-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181219124207.13479-1-kishon@ti.com> References: <20181219124207.13479-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Platforms using Designware IP uses dw_pci_msi_bottom_irq_chip for configuring the MSI controller logic within the Designware IP. However certain platforms like Keystone (K2G) which uses Desingware IP has it's own MSI controller logic. For handling such platforms, the irqchip ops uses msi_irq_ack, msi_set_irq, msi_clear_irq callback functions. Add support to use different msi_irq_chip with default as dw_pci_msi_bottom_irq_chip. This is in preparation to get rid off msi_irq_ack, msi_set_irq, msi_clear_irq and other Keystone specific dw_pcie_host_ops. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware-host.c | 5 ++++- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) -- 2.17.1 Acked-by: Gustavo Pimentel diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 0fa9e8fdce66..db21bd11f153 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -245,7 +245,7 @@ static int dw_pcie_irq_domain_alloc(struct irq_domain *domain, for (i = 0; i < nr_irqs; i++) irq_domain_set_info(domain, virq + i, bit + i, - &dw_pci_msi_bottom_irq_chip, + pp->msi_irq_chip, pp, handle_edge_irq, NULL, NULL); @@ -277,6 +277,9 @@ int dw_pcie_allocate_domains(struct pcie_port *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node); + if (!pp->msi_irq_chip) + pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip; + pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors, &dw_pcie_msi_domain_ops, pp); if (!pp->irq_domain) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 0989d880ac46..0873ee4084aa 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -168,6 +168,7 @@ struct pcie_port { struct irq_domain *irq_domain; struct irq_domain *msi_domain; dma_addr_t msi_data; + struct irq_chip *msi_irq_chip; u32 num_vectors; u32 irq_status[MAX_MSI_CTRLS]; raw_spinlock_t lock; From patchwork Wed Dec 19 12:42:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 154263 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4890856ljp; Wed, 19 Dec 2018 04:43:26 -0800 (PST) X-Google-Smtp-Source: AFSGD/XCujvzNaM2fq/IUubonpeJTWNqJGu88sSYwKASLzO8WEgW8XfjV6LYD9++5T09h+0B8l6A X-Received: by 2002:a17:902:9f93:: with SMTP id g19mr19818841plq.195.1545223406692; Wed, 19 Dec 2018 04:43:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545223406; cv=none; d=google.com; s=arc-20160816; b=aVTHmNFQ8PLdvXHjiDfBY7kvrUEmesCWhoh8OhT7/IVVAayFTtJGZyrZfeUDLhMOaP +fZd/Ayp8vinFgWpUM25qY3YTeUwS6ePDgg3cujve6XKFZC75fLcVHq428bN1UOEyS5c 9c1yOEBDtRRP05UWQG14J8rTWwpLQJowmIPS74Y+XmdFNbebCuZk8g0aYjcAJKV8TQX0 Ard8B1dlqELH3mH4BT1O4DnSacdSgzN4Jzs950lntvcQO9VJftU89k0Akp67KcV4V2nW guGhu4AM3FAN1KmrtncNf1Q1etG6W9nsV2Xh88dzp7yeoZeSC3GzG5+hDAsdhjhe4yjv epqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=s8YQTAlDMbSOqhf4u+bKfrqy75XWX+0He0qtHas8k58=; b=DmVO1d/R1zK4w92WcyNWcMta22SnkCNhZBmB0j3ShNEftevPw3rjkLZHdoHxX5Eegn MPX4GbQmQZtDrku2jsEJATHSrhnnE3Dai/XjDKSVflwkeYCIhzekVVEjoyHwPtSQH9Gj 8QMts2qCTkZQLSDF+NPad1Qnymv89PgDxsGuMQonGFZvVNFMO4AZ13MYF/mM8d898ZEe DpAb8mdoNQkTp2Vu5R6fh+zuMHiabcNgMhKKADZoz7KtEzWo2UnZtEVZKPinWs+/Mauj +iGlO3TaxnsisVvmHAK80d7wtoWla58uuF5wntFZJqkoLIRgtt1IDACohHrTOA+rJs5g 8G7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=B4XRHDBL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This will help to remove Keystone specific callback functions added in dw_pcie_host_ops. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 96 +++++++++++++++++------ 1 file changed, 72 insertions(+), 24 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 05b2bd613c68..420d30ce11f4 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -104,14 +104,6 @@ struct keystone_pcie { struct resource app; }; -static phys_addr_t ks_pcie_get_msi_addr(struct pcie_port *pp) -{ - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); - - return ks_pcie->app.start + MSI_IRQ; -} - static u32 ks_pcie_app_readl(struct keystone_pcie *ks_pcie, u32 offset) { return readl(ks_pcie->va_app_base + offset); @@ -123,11 +115,14 @@ static void ks_pcie_app_writel(struct keystone_pcie *ks_pcie, u32 offset, writel(val, ks_pcie->va_app_base + offset); } -static void ks_pcie_msi_irq_ack(int irq, struct pcie_port *pp) +static void ks_pcie_msi_irq_ack(struct irq_data *data) { - u32 reg_offset, bit_pos; + struct pcie_port *pp = irq_data_get_irq_chip_data(data); struct keystone_pcie *ks_pcie; + u32 irq = data->hwirq; struct dw_pcie *pci; + u32 reg_offset; + u32 bit_pos; pci = to_dw_pcie_from_pp(pp); ks_pcie = to_keystone_pcie(pci); @@ -140,34 +135,91 @@ static void ks_pcie_msi_irq_ack(int irq, struct pcie_port *pp) ks_pcie_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET); } -static void ks_pcie_msi_set_irq(struct pcie_port *pp, int irq) +static void ks_pcie_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) { - u32 reg_offset, bit_pos; - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + struct pcie_port *pp = irq_data_get_irq_chip_data(data); + struct keystone_pcie *ks_pcie; + struct dw_pcie *pci; + u64 msi_target; + + pci = to_dw_pcie_from_pp(pp); + ks_pcie = to_keystone_pcie(pci); + + msi_target = ks_pcie->app.start + MSI_IRQ; + msg->address_lo = lower_32_bits(msi_target); + msg->address_hi = upper_32_bits(msi_target); + msg->data = data->hwirq; + + dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", + (int)data->hwirq, msg->address_hi, msg->address_lo); +} + +static int ks_pcie_msi_set_affinity(struct irq_data *irq_data, + const struct cpumask *mask, bool force) +{ + return -EINVAL; +} + +static void ks_pcie_msi_mask(struct irq_data *data) +{ + struct pcie_port *pp = irq_data_get_irq_chip_data(data); + struct keystone_pcie *ks_pcie; + u32 irq = data->hwirq; + struct dw_pcie *pci; + unsigned long flags; + u32 reg_offset; + u32 bit_pos; + + raw_spin_lock_irqsave(&pp->lock, flags); + + pci = to_dw_pcie_from_pp(pp); + ks_pcie = to_keystone_pcie(pci); reg_offset = irq % 8; bit_pos = irq >> 3; - ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset), + ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset), BIT(bit_pos)); + + raw_spin_unlock_irqrestore(&pp->lock, flags); } -static void ks_pcie_msi_clear_irq(struct pcie_port *pp, int irq) +static void ks_pcie_msi_unmask(struct irq_data *data) { - u32 reg_offset, bit_pos; - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + struct pcie_port *pp = irq_data_get_irq_chip_data(data); + struct keystone_pcie *ks_pcie; + u32 irq = data->hwirq; + struct dw_pcie *pci; + unsigned long flags; + u32 reg_offset; + u32 bit_pos; + + raw_spin_lock_irqsave(&pp->lock, flags); + + pci = to_dw_pcie_from_pp(pp); + ks_pcie = to_keystone_pcie(pci); reg_offset = irq % 8; bit_pos = irq >> 3; - ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset), + ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset), BIT(bit_pos)); + + raw_spin_unlock_irqrestore(&pp->lock, flags); } +static struct irq_chip ks_pcie_msi_irq_chip = { + .name = "KEYSTONE-PCI-MSI", + .irq_ack = ks_pcie_msi_irq_ack, + .irq_compose_msi_msg = ks_pcie_compose_msi_msg, + .irq_set_affinity = ks_pcie_msi_set_affinity, + .irq_mask = ks_pcie_msi_mask, + .irq_unmask = ks_pcie_msi_unmask, +}; + static int ks_pcie_msi_host_init(struct pcie_port *pp) { + pp->msi_irq_chip = &ks_pcie_msi_irq_chip; return dw_pcie_allocate_domains(pp); } @@ -768,11 +820,7 @@ static const struct dw_pcie_host_ops ks_pcie_host_ops = { .rd_other_conf = ks_pcie_rd_other_conf, .wr_other_conf = ks_pcie_wr_other_conf, .host_init = ks_pcie_host_init, - .msi_set_irq = ks_pcie_msi_set_irq, - .msi_clear_irq = ks_pcie_msi_clear_irq, - .get_msi_addr = ks_pcie_get_msi_addr, .msi_host_init = ks_pcie_msi_host_init, - .msi_irq_ack = ks_pcie_msi_irq_ack, .scan_bus = ks_pcie_v3_65_scan_bus, }; From patchwork Wed Dec 19 12:42:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 154264 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4891024ljp; Wed, 19 Dec 2018 04:43:37 -0800 (PST) X-Google-Smtp-Source: AFSGD/VPJarcIM6yjI67/c5oyA4ipNEANHBFoc0vpX6zgD2E3//u02wg+a2Pzoj8aWdPd+rEEu5t X-Received: by 2002:a62:8985:: with SMTP id n5mr20626310pfk.255.1545223417457; Wed, 19 Dec 2018 04:43:37 -0800 (PST) ARC-Seal: i=1; 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Signed-off-by: Kishon Vijay Abraham I --- .../pci/controller/dwc/pcie-designware-host.c | 45 ++++++------------- drivers/pci/controller/dwc/pcie-designware.h | 5 --- 2 files changed, 14 insertions(+), 36 deletions(-) -- 2.17.1 Acked-by: Gustavo Pimentel diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index db21bd11f153..dbc94f3be3d5 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -126,18 +126,12 @@ static void dw_pci_setup_msi_msg(struct irq_data *data, struct msi_msg *msg) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); u64 msi_target; - if (pp->ops->get_msi_addr) - msi_target = pp->ops->get_msi_addr(pp); - else - msi_target = (u64)pp->msi_data; + msi_target = (u64)pp->msi_data; msg->address_lo = lower_32_bits(msi_target); msg->address_hi = upper_32_bits(msi_target); - if (pp->ops->get_msi_data) - msg->data = pp->ops->get_msi_data(pp, data->hwirq); - else - msg->data = data->hwirq; + msg->data = data->hwirq; dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", (int)data->hwirq, msg->address_hi, msg->address_lo); @@ -157,17 +151,13 @@ static void dw_pci_bottom_mask(struct irq_data *data) raw_spin_lock_irqsave(&pp->lock, flags); - if (pp->ops->msi_clear_irq) { - pp->ops->msi_clear_irq(pp, data->hwirq); - } else { - ctrl = data->hwirq / MAX_MSI_IRQS_PER_CTRL; - res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; - bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL; + ctrl = data->hwirq / MAX_MSI_IRQS_PER_CTRL; + res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; + bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL; - pp->irq_status[ctrl] &= ~(1 << bit); - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, - ~pp->irq_status[ctrl]); - } + pp->irq_status[ctrl] &= ~(1 << bit); + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, + ~pp->irq_status[ctrl]); raw_spin_unlock_irqrestore(&pp->lock, flags); } @@ -180,17 +170,13 @@ static void dw_pci_bottom_unmask(struct irq_data *data) raw_spin_lock_irqsave(&pp->lock, flags); - if (pp->ops->msi_set_irq) { - pp->ops->msi_set_irq(pp, data->hwirq); - } else { - ctrl = data->hwirq / MAX_MSI_IRQS_PER_CTRL; - res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; - bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL; + ctrl = data->hwirq / MAX_MSI_IRQS_PER_CTRL; + res = ctrl * MSI_REG_CTRL_BLOCK_SIZE; + bit = data->hwirq % MAX_MSI_IRQS_PER_CTRL; - pp->irq_status[ctrl] |= 1 << bit; - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, - ~pp->irq_status[ctrl]); - } + pp->irq_status[ctrl] |= 1 << bit; + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, + ~pp->irq_status[ctrl]); raw_spin_unlock_irqrestore(&pp->lock, flags); } @@ -209,9 +195,6 @@ static void dw_pci_bottom_ack(struct irq_data *d) dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + res, 4, 1 << bit); - if (pp->ops->msi_irq_ack) - pp->ops->msi_irq_ack(d->hwirq, pp); - raw_spin_unlock_irqrestore(&pp->lock, flags); } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 0873ee4084aa..53cb6ab405b5 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -134,14 +134,9 @@ struct dw_pcie_host_ops { int (*wr_other_conf)(struct pcie_port *pp, struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); int (*host_init)(struct pcie_port *pp); - void (*msi_set_irq)(struct pcie_port *pp, int irq); - void (*msi_clear_irq)(struct pcie_port *pp, int irq); - phys_addr_t (*get_msi_addr)(struct pcie_port *pp); - u32 (*get_msi_data)(struct pcie_port *pp, int pos); void (*scan_bus)(struct pcie_port *pp); void (*set_num_vectors)(struct pcie_port *pp); int (*msi_host_init)(struct pcie_port *pp); - void (*msi_irq_ack)(int irq, struct pcie_port *pp); }; struct pcie_port { From patchwork Wed Dec 19 12:42:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 154262 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4890778ljp; Wed, 19 Dec 2018 04:43:21 -0800 (PST) X-Google-Smtp-Source: AFSGD/XrEodkr6GN0+uXnY+ST3+neU8TV7egE7OKAhGJDu+7heJ3jm7EX7pO8aK8Fu2wMQvlZut0 X-Received: by 2002:a17:902:365:: with SMTP id 92mr19166991pld.327.1545223401785; Wed, 19 Dec 2018 04:43:21 -0800 (PST) ARC-Seal: i=1; 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Writing to MSI control registers on platforms which doesn't use Designware's MSI controller logic might have side effects. To be safe, do not write to MSI control registers if the platform uses it's own MSI controller logic instead of Designware's MSI controller logic. Signed-off-by: Kishon Vijay Abraham I --- .../pci/controller/dwc/pcie-designware-host.c | 24 ++++++++++--------- 1 file changed, 13 insertions(+), 11 deletions(-) -- 2.17.1 Acked-by: Gustavo Pimentel diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index dbc94f3be3d5..6644a5683b2b 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -647,17 +647,19 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_setup(pci); - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; - - /* Initialize IRQ Status array */ - for (ctrl = 0; ctrl < num_ctrls; ctrl++) { - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - 4, ~0); - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - 4, ~0); - pp->irq_status[ctrl] = 0; + if (!pp->ops->msi_host_init) { + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + + /* Initialize IRQ Status array */ + for (ctrl = 0; ctrl < num_ctrls; ctrl++) { + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), + 4, ~0); + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), + 4, ~0); + pp->irq_status[ctrl] = 0; + } } /* Setup RC BARs */