From patchwork Tue Apr 26 16:04:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 566014 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp3742743map; Tue, 26 Apr 2022 09:22:34 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyJ8NZdXVGnXlqYlXrcgrXrgKYCuYuYp+exjlu2jalGKm0V9IEy6z1YVlTB+of4kQJj1VOc X-Received: by 2002:a25:2f03:0:b0:648:3d2f:6e66 with SMTP id v3-20020a252f03000000b006483d2f6e66mr14226519ybv.9.1650990154071; Tue, 26 Apr 2022 09:22:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650990154; cv=none; d=google.com; s=arc-20160816; b=ueMZ8KVL2+eShg1h6Tz2oEn/AK4hit3icynW+VQypYIq/dbakBiYD5H9lxBo7El/pt tmzoYFCbA6C6JfK/6mXawgpyBD7BJXdXE2RSubCniiVAZ53Xs6okeSuWD1/L87m5SCO2 LHeQai999vB4/O6pPCUwAexW8qPch0Gz0nBGYaAkGZfjOA8KIj38r88nEER4KmEMEHZm 5mFZBA2IPjsMx4Ly+zj/jKOND40itNWAbzJ/Fnuppvb3F9vYf/2C7lmYMUFaxwzJEfRP HJXtpRqrEeCJMN3DtqYMeYlHf1xBMRPTlCr3Mnm60TuXe1hHGAvXtp8L7lmYu1TinIuQ gYaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kUC9tG6igzVEJirEgnCTOHV137FjKUwSoYb77+c6ZRw=; b=It/Ot1nKBjv5ps/AF7LDXN/A6WJVxL3PkPBQGXPatmMZ4u0ppmkptsAvgs44D6a8f7 7Fe0rOO7JTHKlITxYqIr8e8OFHI5x6hE4kY7h4lP40odHBU9z+rdIgjVUyOXb5osVL/d zo66JK6JWFy862K75mpsCxgYs52vGrzt4QBCOMBxrHaXN1eRIKMtlhkmEcjjP5cBvEC4 CGbti1bQtTwosnSn/sqAMiI0oF2YLFShZ9uOJmE3SECd27NtO2QbixGM98G7Kvf4S9Kj n+wcgks4upiNpllcs2cNIuWVC8GFpPFc21gpLUPZcIJ+k5HpMCC0DXCEkeGpsVtUOta/ /csA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lNyrgsYt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x2-20020a814a02000000b002ec35658153si13928947ywa.490.2022.04.26.09.22.34 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Apr 2022 09:22:34 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lNyrgsYt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40566 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1njNxR-0001lc-Bv for patch@linaro.org; Tue, 26 Apr 2022 12:22:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38766) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1njNfw-0006QZ-OQ for qemu-devel@nongnu.org; Tue, 26 Apr 2022 12:04:28 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:41539) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1njNfu-0007np-JT for qemu-devel@nongnu.org; Tue, 26 Apr 2022 12:04:28 -0400 Received: by mail-wr1-x432.google.com with SMTP id s21so11437551wrb.8 for ; Tue, 26 Apr 2022 09:04:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kUC9tG6igzVEJirEgnCTOHV137FjKUwSoYb77+c6ZRw=; b=lNyrgsYtPfOsC/NPE8Tl6zMXHkfjDIf2zluXg+X/aFcl88cWjCcZq+Y4hSDMi5aIYB L7EdlCgNVN9/EJPLkwLQ7jZePx8sD8aprb45HLgGt3h4AeMe2j22N2O01KL+yR3Szpiu XmvsXW8fI4Ul7zJ07Gu75byBBfeuzx5faytLqOHZ5BYsgDRWb1pY74i9T0Xf294KN0/u 2KpyMSGGiO6UBEl6TiPJU3iZqDArgDS3nrdZY796CXYIAHf7k/A52gljDFs2pckIyZGG 25BH2I5ia1VBEsEeW44UC6MAR2gJNXvEmJeib1fFYOB6nGFYbXYq+NEZTuOdlju/HuTw FJxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kUC9tG6igzVEJirEgnCTOHV137FjKUwSoYb77+c6ZRw=; b=euhOIRM17Kmu0w3he6COFScWKxL3q0tVNNLc/d+hWN/kYs+14qyknm+W4wRk0dQwzp wKx28wtR2TLKxMh8wUEp69677+Zp4wobOvuAG46cpKR9/Mnx+NagJDhAyxcTVLBVLY8L J6fabwLVopyfxqx7SDfRdh42gT4mRam3uhKG1NV2SBPFYs8jjp7nToMz3D5y3OYRIPFL ADY76oDukP3m8qvPIb6ccln5KE/ePUvM/hZi88CvxBv5+zXlvI/l6vQgJ+2t5bpjGNpo byO9CQyerpBcnOvG3zAu/XHbHpCN3TSGOTl/2nHJ2CHwP5CdW80DOe18eBx4bPLePxNj AM/A== X-Gm-Message-State: AOAM530PurWu0ylRz6WGv5YO+gi8N1vBlCKJFCtbGajnvG/kxy883Z3W NmUUlEsPDZm6XmJmB1vr4jVgADV6yJ7cgg== X-Received: by 2002:a5d:4303:0:b0:207:a7d8:4ce6 with SMTP id h3-20020a5d4303000000b00207a7d84ce6mr19164757wrq.101.1650989065217; Tue, 26 Apr 2022 09:04:25 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p26-20020adf959a000000b0020aca418f14sm13584777wrp.54.2022.04.26.09.04.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Apr 2022 09:04:24 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/3] target/arm: Advertise support for FEAT_TTL Date: Tue, 26 Apr 2022 17:04:20 +0100 Message-Id: <20220426160422.2353158-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220426160422.2353158-1-peter.maydell@linaro.org> References: <20220426160422.2353158-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The Arm FEAT_TTL architectural feature allows the guest to provide an optional hint in an AArch64 TLB invalidate operation about which translation table level holds the leaf entry for the address being invalidated. QEMU's TLB implementation doesn't need that hint, and we correctly ignore the (previously RES0) bits in TLB invalidate operation values that are now used for the TTL field. So we can simply advertise support for it in our 'max' CPU. Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + 2 files changed, 2 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 520fd39071e..6ed2417f6fc 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -54,6 +54,7 @@ the following architecture extensions: - FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain) - FEAT_TLBIRANGE (TLB invalidate range instructions) - FEAT_TTCNP (Translation table Common not private translations) +- FEAT_TTL (Translation Table Level) - FEAT_TTST (Small translation tables) - FEAT_UAO (Unprivileged Access Override control) - FEAT_VHE (Virtualization Host Extensions) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index eb44c05822c..ec2d159163f 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -839,6 +839,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ + t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ cpu->isar.id_aa64mmfr2 = t; t = cpu->isar.id_aa64zfr0; From patchwork Tue Apr 26 16:04:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 566011 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp3734575map; Tue, 26 Apr 2022 09:13:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw/oIWPGKZWpjhKW05jtgHSoysfbCU0iSwG/vzA9pH/Onen/hUWssmra56qgdGeYbDAVnEJ X-Received: by 2002:a05:6902:104:b0:628:bc80:748f with SMTP id o4-20020a056902010400b00628bc80748fmr22503191ybh.575.1650989585388; Tue, 26 Apr 2022 09:13:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650989585; cv=none; d=google.com; s=arc-20160816; b=nlbJEe9S4pr2TiqRokhgMS4usMt/f++TD7rnJw6P/8R0uVIgGhoHreTtrusVZc6HTw 0XnNS5h1oxCrcNFVXUw89gSprjRf4kTlt9aFEIQdwRinKmdyVAqW9yl/vRxtPJJf5ze+ A3LaH9C9JWCr0YHFe6LP5Bc5BGz2eMRY3Oq1Eisb9rIEclavPngsf7Mn1Th5YFD2WuTl DvHN3fg5dLWPimcGdmsMha6LYSXq7w4x+rKjJftK72DRsk/pqOi8c42q/zokrXgiS5F9 WYXubvMPuN1L0jg+oQ+pQBK++uAAhXVBXxyzRopNFLKNjw/D+OR8/lDSnBfRXeg8uLoK jgZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=Z32BMyn+yGJAtZTpHVnzzj+i0p3WqVl/zaCG0tsjJlk=; b=Lk9aRfTdpDaiogrxH00+OW9S8BLuqahEv9C62Zrmn4TUqGVd95k9yP7t5DF5tpax5V hzaigcfV/aU07BSJxCvH4tzCaiL7s/tfb04BpZPUeJh7bBItfFoumQoUO7mY6MRwj87Y KKL780PUrqEpnt9WDx+aTT3lObDWa3G9jr4zRc+7GBJZV1BC6gd5moJXh83coFpYnhR4 pOvlHRkye2jT+1Lt+Ry73NrOuN7bq1HT8be5IscptDtHfkwneX/aZoSpQBFTg6Ht+y7h CnW5Ook5zfst5J81pFEBGEeL/2Qp97cwqufpDT5KcHKtFCapUvWr+dqh1QvHZfkB+iOn weAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=toIno8Pm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a3-20020a251a03000000b0064540d1f187si15805059yba.681.2022.04.26.09.13.05 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Apr 2022 09:13:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=toIno8Pm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42050 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1njNoG-0008Nb-OD for patch@linaro.org; Tue, 26 Apr 2022 12:13:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38786) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1njNfx-0006T0-Fz for qemu-devel@nongnu.org; Tue, 26 Apr 2022 12:04:29 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:46000) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1njNfv-0007o5-FP for qemu-devel@nongnu.org; Tue, 26 Apr 2022 12:04:29 -0400 Received: by mail-wr1-x432.google.com with SMTP id w4so26081363wrg.12 for ; Tue, 26 Apr 2022 09:04:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z32BMyn+yGJAtZTpHVnzzj+i0p3WqVl/zaCG0tsjJlk=; b=toIno8PmSDyTi/EcApXnqZMSlP6jK9sHOQ7YdSZ5iigqGKsY5Cd0O24s7oRK4bfNtI kjycVSoQVpHQSLgl9+O4bEEfZrZk9UsMeKPoHXFvHfASgPdNPVbox5kv8wtDE6DOsj/y R85hQM/iIeevBY4YjSfbnkyzVnAgoBQWdOJu3Y5O5N/s12VcwMsoqgKrJ44XPh54awB2 8ucYTWTiz+TM0da/HIhR0ayEWetrd+3SNg6O+99rYI1/mXKgfkdzUzmnBFihCCTsuL0y qm7L/s6Or35p+8fgid6BjET+lcodaPs5Ddy+VsmNB33MlBth1mV/mWfe/aguUMaYnI0X f63A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z32BMyn+yGJAtZTpHVnzzj+i0p3WqVl/zaCG0tsjJlk=; b=nQ+E7vY+0rICr4h7pdZXLSix6JkCtlB1pH2H8TrPbSn0emflSY7Wl4Hfgho6RBqdGx QtkY4rsW1LBvXrpG9R2cvhO2YZWFLZdewV85T1dp5SRkFfFD/9xewMa405stqv6l3beH C7Bjc7BasHa2qJJOD0mv7tWUQzO4ooplSLn7YbiXH9SacepzfB6siUL8z7Lgn+c8xIip vK3tu/voWDJBUfu0OrAH7mHA/6PE9ctaIr9yzd2hWARfyo6ngwvFh0Uc44JK//idlnR/ nTzj86IgMqunfrjzAvvnj4xxO6ycu5TpyFT29UYXwAb+XabG70x4tdI5zsEFX3E3V7bx dRSw== X-Gm-Message-State: AOAM530REh4g0sFkkzyLFjAwUrHKNALkKpjLtDkdNlGd4XdJjoK5E5/W TwnzFrlnAvrZnOVxdHayLa0JsA== X-Received: by 2002:a5d:6e89:0:b0:20a:de31:18d1 with SMTP id k9-20020a5d6e89000000b0020ade3118d1mr7625812wrz.449.1650989066088; Tue, 26 Apr 2022 09:04:26 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p26-20020adf959a000000b0020aca418f14sm13584777wrp.54.2022.04.26.09.04.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Apr 2022 09:04:25 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/3] target/arm: Advertise support for FEAT_BBM level 2 Date: Tue, 26 Apr 2022 17:04:21 +0100 Message-Id: <20220426160422.2353158-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220426160422.2353158-1-peter.maydell@linaro.org> References: <20220426160422.2353158-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The description in the Arm ARM of the requirements of FEAT_BBM is admirably clear on the guarantees it provides software, but slightly more obscure on what that means for implementations. The description of the equivalent SMMU feature in the SMMU specification (IHI0070D.b section 3.21.1) is perhaps a bit more detailed and includes some example valid implementation choices. (The SMMU version of this feature is slightly tighter than the CPU version: the CPU is permitted to raise TLB Conflict aborts in some situations that the SMMU may not. This doesn't matter for QEMU because we don't want to do TLB Conflict aborts anyway.) The informal summary of FEAT_BBM is that it is about permitting an OS to switch a range of memory between "covered by a huge page" and "covered by a sequence of normal pages" without having to engage in the 'break-before-make' dance that has traditionally been necessary. The 'break-before-make' sequence is: * replace the old translation table entry with an invalid entry * execute a DSB insn * execute a broadcast TLB invalidate insn * execute a DSB insn * write the new translation table entry * execute a DSB insn The point of this is to ensure that no TLB can simultaneously contain TLB entries for the old and the new entry, which would traditionally be UNPREDICTABLE (allowing the CPU to generate a TLB Conflict fault or to use a random mishmash of values from the old and the new entry). FEAT_BBM level 2 says "for the specific case where the only thing that changed is the size of the block, the TLB is guaranteed not to do weird things even if there are multiple entries for an address", which means that software can now do: * replace old translation table entry with new entry * DSB * broadcast TLB invalidate * DSB As the SMMU spec notes, valid ways to do this include: * if there are multiple entries in the TLB for an address, choose one of them and use it, ignoring the others * if there are multiple entries in the TLB for an address, throw them all out and do a page table walk to get a new one QEMU's page table walk implementation for Arm CPUs already meets the requirements for FEAT_BBM level 2. When we cache an entry in our TCG TLB, we do so only for the specific (non-huge) page that the address is in, and there is no way for the TLB data structure to ever have more than one TLB entry for that page. (We handle huge pages only in that we track what part of the address space is covered by huge pages so that a TLB invalidate operation for an address in a huge page results in an invalidation of the whole TLB.) We ignore the Contiguous bit in page table entries, so we don't have to do anything for the parts of FEAT_BBM that deal with changis to the Contiguous bit. FEAT_BBM level 2 also requires that the nT bit in block descriptors must be ignored; since commit 39a1fd25287f5dece5 we do this. It's therefore safe for QEMU to advertise FEAT_BBM level 2 by setting ID_AA64MMFR2_EL1.BBM to 2. Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + 2 files changed, 2 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 6ed2417f6fc..c3bd0676a87 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -9,6 +9,7 @@ the following architecture extensions: - FEAT_AA32HPD (AArch32 hierarchical permission disables) - FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions) - FEAT_AES (AESD and AESE instructions) +- FEAT_BBM at level 2 (Translation table break-before-make levels) - FEAT_BF16 (AArch64 BFloat16 instructions) - FEAT_BTI (Branch Target Identification) - FEAT_DIT (Data Independent Timing instructions) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index ec2d159163f..2974cbc0d35 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -840,6 +840,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ + t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ cpu->isar.id_aa64mmfr2 = t; t = cpu->isar.id_aa64zfr0; From patchwork Tue Apr 26 16:04:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 566013 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp3737725map; Tue, 26 Apr 2022 09:16:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJy7Gz0OyIt7Do6P4J83V/9uBiO0GR7YtCG4kvopGZT1kiMHPFa3c7VCuobAotbw1CTYy8Ux X-Received: by 2002:a05:6902:103:b0:628:3eb4:a6cc with SMTP id o3-20020a056902010300b006283eb4a6ccmr21467132ybh.4.1650989805546; Tue, 26 Apr 2022 09:16:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650989805; cv=none; d=google.com; s=arc-20160816; b=OvEuKqbCeaMJhrQCmyoktMZQksSEOTH6yfIgre0aOZyvfVCsb1g/w7WyfelEWUUTur krlB7iEy1jyTk2EN5iVzQ/Ar+Cjfg64Fr1vhkpbMXYIB2yQJB3gjotftR32OYhBpxg0b cqzFoGCzKnBNLFIGxhX2cE6/SBFZ/Cgb+SEW9NOEZYFHxkUj/zmNoZnPtZh36SGqN8HX Jgf0RdNnDQbKQNYIsoaS5STlSesl7VIze33lGuKoj9DY0vD4wG+nDmHHSWG/0nJV77d+ wplCn4rBl1xC4yLVmKUOguIIdDsE+3oI5ZuUM6Wa6ClsQ1fG7CwLFYt5N0qeXgvNc+cq vFGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=OsQV7ZmcQTGgPLMSTvn131giURirHLy7ThlcG0+Jl1Q=; b=sf389ZxtIRiQCOvwTTHTmkGVFG2G7fK+MwSY20urSqyXdUEpxI8AJl/3UkVKkj/gUD 3WsYXPL5fd2w7QJkHPxTtWYhYRg2oDrc/x6WVN5DqHP2AJUF+jDF2nKzs/bkuVb8msgz 5BlESrqiO5+2rAdIa3tgUeZPlCA/mocMf6wU44N5NPSeDYM8w7laBEn4oHZFLdD/WcBt 2ubumoEBJDgfvvegojAyJ6zwh09bOHIrTfX0nWbJRp0trPlXG1Deno/6amGWiUJ29Dbi URo2vFOfT9NwDjAU+uAcUakD29PzJFMlbaSvIe1IK8xc0oXyRghi/D+Imzs9MFOnxfTi ijiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UcxDkNq6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z196-20020a814ccd000000b002eaabee6ec6si13795621ywa.334.2022.04.26.09.16.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Apr 2022 09:16:45 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UcxDkNq6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:50858 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1njNrp-0006Es-2C for patch@linaro.org; Tue, 26 Apr 2022 12:16:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38798) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1njNfy-0006U5-9Z for qemu-devel@nongnu.org; Tue, 26 Apr 2022 12:04:30 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:41832) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1njNfw-0007oS-J1 for qemu-devel@nongnu.org; Tue, 26 Apr 2022 12:04:30 -0400 Received: by mail-wm1-x32b.google.com with SMTP id u9-20020a05600c00c900b00393e729e655so1894061wmm.0 for ; Tue, 26 Apr 2022 09:04:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OsQV7ZmcQTGgPLMSTvn131giURirHLy7ThlcG0+Jl1Q=; b=UcxDkNq6HwUVjI7SrSKIKyl7zkUmsYOum2JX9evLnWcVIAuuoKk3bvJdVwp/qBl6yW VzfjkWA3QHRXRiVS8I0GOL8l/uXW7yPDIyuAt3Pn/pofYHCfrtPuLjWxVAZHb2uMOwbh cwOLyu+pUycF72ELo2/5nkj1eyjpZ7OrxBkldNRalZl6CpE/oR9/F9eSz2opfWYTr5T0 igkb6n0k437jI6JhTGEAFri4t830yt1xdSPTKZzGIlfwIK3Og+7gCAmqhw1unTPcX7jQ jkqUQByGFgSfEh/mIWlUbngWk56k5Tp8b4eAcx6coC5qSStXIy48dox6mNqKUNcSI20u CBjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OsQV7ZmcQTGgPLMSTvn131giURirHLy7ThlcG0+Jl1Q=; b=VtEV5t5Tww1xKfgGq7+rkKM4sqr1z2WnBKaRRS+9dBjYoGA+QXwdtZ6Ah18jbaQg8c t6iNDDPlB7YPwUgZ1gx63Gy4GzY5oV7eYLHfuYucIiz+bgzRgmPCeBg4usWeTzgvO8v7 PldyIlqhGQ6edCoMyr9udsq9GuNDWmxCYIstsqoAKG4bhCkhqY+Tas5bMR2iljWBI7ne jsP50bn3yQoj6icn0urlEyPE2jJYhFohwOOl1CpLgYg+lUmAtwHUc9GUEO7fVnC6rOJG OGU+dPa8RATaP3RZRnlsn46CU17MYF1j6drvw7APrBdaP+TapF6QrWMuN/Hg40c+DqC9 CTeA== X-Gm-Message-State: AOAM532AS5EZtIIXfpdys7J4LYSFSOPxQqAdo4hWZOhCCiNEGcuplKw2 sQR2cCjnZ403C2Zh+CZ9Eho0Tw== X-Received: by 2002:a1c:f30b:0:b0:380:e444:86b9 with SMTP id q11-20020a1cf30b000000b00380e44486b9mr21957069wmq.81.1650989067083; Tue, 26 Apr 2022 09:04:27 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id p26-20020adf959a000000b0020aca418f14sm13584777wrp.54.2022.04.26.09.04.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Apr 2022 09:04:26 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 3/3] hw/arm/smmuv3: Advertise support for SMMUv3.2-BBML2 Date: Tue, 26 Apr 2022 17:04:22 +0100 Message-Id: <20220426160422.2353158-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220426160422.2353158-1-peter.maydell@linaro.org> References: <20220426160422.2353158-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eric Auger , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The Arm SMMUv3 includes an optional feature equivalent to the CPU FEAT_BBM, which permits an OS to switch a range of memory between "covered by a huge page" and "covered by a sequence of normal pages" without having to engage in the traditional 'break-before-make' dance. (This is particularly important for the SMMU, because devices performing I/O through an SMMU are less likely to be able to cope with the window in the sequence where an access results in a translation fault.) The SMMU spec explicitly notes that one of the valid ways to be a BBM level 2 compliant implementation is: * if there are multiple entries in the TLB for an address, choose one of them and use it, ignoring the others Our SMMU TLB implementation (unlike our CPU TLB) does allow multiple TLB entries for an address, because the translation table level is part of the SMMUIOTLBKey, and so our IOTLB hashtable can include entries for the same address where the leaf was at different levels (i.e. both hugepage and normal page). Our TLB lookup implementation in smmu_iotlb_lookup() will always find the entry with the lowest level (i.e. it prefers the hugepage over the normal page) and ignore any others. TLB invalidation correctly removes all TLB entries matching the specified address or address range (unless the guest specifies the leaf level explicitly, in which case it gets what it asked for). So we can validly advertise support for BBML level 2. Note that we still can't yet advertise ourselves as an SMMU v3.2, because v3.2 requires support for the S2FWB feature, which we don't yet implement. Signed-off-by: Peter Maydell Reviewed-by: Eric Auger --- hw/arm/smmuv3-internal.h | 1 + hw/arm/smmuv3.c | 1 + 2 files changed, 2 insertions(+) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index d1885ae3f25..e9150a6ff33 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -56,6 +56,7 @@ REG32(IDR2, 0x8) REG32(IDR3, 0xc) FIELD(IDR3, HAD, 2, 1); FIELD(IDR3, RIL, 10, 1); + FIELD(IDR3, BBML, 11, 2); REG32(IDR4, 0x10) REG32(IDR5, 0x14) FIELD(IDR5, OAS, 0, 3); diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 707eb430c23..74bc2e85ee4 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -259,6 +259,7 @@ static void smmuv3_init_regs(SMMUv3State *s) s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1); s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1); + s->idr[3] = FIELD_DP32(s->idr[3], IDR3, BBML, 2); /* 4K, 16K and 64K granule support */ s->idr[5] = FIELD_DP32(s->idr[5], IDR5, GRAN4K, 1);