From patchwork Sun Apr 24 23:17:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 565665 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6AB5AC433EF for ; Sun, 24 Apr 2022 23:17:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239882AbiDXXU6 (ORCPT ); Sun, 24 Apr 2022 19:20:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36784 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233081AbiDXXU5 (ORCPT ); Sun, 24 Apr 2022 19:20:57 -0400 Received: from out3-smtp.messagingengine.com (out3-smtp.messagingengine.com [66.111.4.27]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68CB55DA14; Sun, 24 Apr 2022 16:17:54 -0700 (PDT) Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id BC0865C010E; Sun, 24 Apr 2022 19:17:53 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Sun, 24 Apr 2022 19:17:53 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :message-id:mime-version:reply-to:sender:subject:subject:to:to; s=fm2; t=1650842273; x=1650928673; bh=ukhK/3p5rv4p+ixQouMflt4+T +mWNkdHDOYzih3p7Uc=; b=ZgtYGMJLu+mac01+DAYTZ0b8xT+Og/Lx7gii1iuci G33s0ZfpaZXpNjjAfsh1j2zUBsTpsq2QYROM8IWxtePYhZYmwyNzBemRGpZhVQNf u4PdbRnehe99W8WnDhtOqwWmk0e8QJB88z5Xh9riqiU8cD4kc3Z5wQUHvoc0t2ZX k/+U3J6316QBjh3LJKti3VFS5YZQsD8QLTmlLkIsmtIBjXkW3/XmeYOIClNBJgrn sbixv5kLO08IuRgMoJbkZYmJ/WZ5nukR07Ps01LJX4+ScCvL4fw8n5jC5dwu5jz8 UV+wA7pVeYUAA3ajkKm1rlfQmSZqe4GU7VqppPExZH71A== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :from:from:in-reply-to:message-id:mime-version:reply-to:sender :subject:subject:to:to:x-me-proxy:x-me-proxy:x-me-sender :x-me-sender:x-sasl-enc; s=fm1; t=1650842273; x=1650928673; bh=u khK/3p5rv4p+ixQouMflt4+T+mWNkdHDOYzih3p7Uc=; b=mbIQwFTIE94auivFE sTfdUfxiDwtXw4VsO9TSzerZLQr5ueV758NYVCYWyiw8j7UTrlGGnKdQWECilEhH LIxwJf+6bx8E+BhqUS7e1b8BfelX/mKC3BU3D8imbHzw5Lsf8CPRSTS4NzO2wBiL FW+ry/lwD1sVthP/YBMUHeCZ3kqOiIEPfBx/epGKIWF7XdKzqWtqQ0bwQBWvenjR 8gd9XMmTRXSKXorpDNj/IYol5x6pLkCJrdb76GCfGrqX85nmthySApPrOZS0QXZZ W3mmupJapOLKUXhrMGBtPcdCvL+gu9vY44tcOrHmu4eR00lj1oIE4VYsjBRh8gHL JN5ZQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedruddtgddvudcutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvfevufffkffoggfgsedtkeertdertddtnecuhfhrohhmpefurghmuhgvlhcu jfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenucggtffrrg htthgvrhhnpeekveelhfejueelleetvdejvdeffeetgeelheeujeffhefgffefkeehhffh keekgeenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpe hsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sun, 24 Apr 2022 19:17:52 -0400 (EDT) From: Samuel Holland To: Ulf Hansson , linux-mmc@vger.kernel.org Cc: Samuel Holland , Andre Przywara , Chen-Yu Tsai , Jernej Skrabec , Maxime Ripard , Yangtao Li , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH] mmc: sunxi-mmc: Fix DMA descriptors allocated above 32 bits Date: Sun, 24 Apr 2022 18:17:50 -0500 Message-Id: <20220424231751.32053-1-samuel@sholland.org> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Newer variants of the MMC controller support a 34-bit physical address space by using word addresses instead of byte addresses. However, the code truncates the DMA descriptor address to 32 bits before applying the shift. This breaks DMA for descriptors allocated above the 32-bit limit. Fixes: 3536b82e5853 ("mmc: sunxi: add support for A100 mmc controller") Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Reviewed-by: Jernej Skrabec --- drivers/mmc/host/sunxi-mmc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c index c62afd212692..46f9e2923d86 100644 --- a/drivers/mmc/host/sunxi-mmc.c +++ b/drivers/mmc/host/sunxi-mmc.c @@ -377,8 +377,9 @@ static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host, pdes[i].buf_addr_ptr1 = cpu_to_le32(sg_dma_address(&data->sg[i]) >> host->cfg->idma_des_shift); - pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc >> - host->cfg->idma_des_shift); + pdes[i].buf_addr_ptr2 = + cpu_to_le32(next_desc >> + host->cfg->idma_des_shift); } pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD);