From patchwork Sun Apr 24 13:20:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 565646 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7BD70C433F5 for ; Sun, 24 Apr 2022 13:20:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229577AbiDXNXm (ORCPT ); Sun, 24 Apr 2022 09:23:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54574 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234000AbiDXNXl (ORCPT ); Sun, 24 Apr 2022 09:23:41 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4FEACAE64 for ; Sun, 24 Apr 2022 06:20:39 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id g19so21944272lfv.2 for ; Sun, 24 Apr 2022 06:20:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=13bAhAMjv2je6RMOj1RTuCmatzo9I4F5Zv7WwkP8+gk=; b=u8Fh+X/orbfnwbnBJeGYv39MuQFzNu5KAHWMwplOnLS5OegN1HK15Tn+HV3iUo8hzm 0HUpMnDgdSFyA6FliVEH2sUSdI1rYfwRzEmYF7X3drv4wto/dZ2sdyGKqT020K77fUe0 brR4YoLvVs0ovkuBcw/R4K0ZbxszzwpNxvBaU0LGyzC/OtIG3G9lDDlSmWmV+MPh5Sf+ 6qV6z/Q4V8JrKUSjQ+sRegQZF80azSHOEB72tzpKQ5Fjxpn6EU12dmIOJIlo7A1bMA+p yQyN25HZjkwnZwgeB0x6+ljlLlSBt9YXFbLqrgRcHxGtXi3Sq/xN8CAQFK/EHb34ZQwl h51Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=13bAhAMjv2je6RMOj1RTuCmatzo9I4F5Zv7WwkP8+gk=; b=SF0j8JJCb+we5NF9/zTetD2hxdFqVSeu4yhgXl9sawQIODUvE7LpMBZERxzqAGxLWZ UUYseLaFYb12HERuntYqvD3igbfKeiGof6+gAUzSrqotjxGtAIfvV3VpF3pQLzQqnUiI 4yri958BCAGhs7NuZzrGIfnXx/R2tQ86MmI08KxLVhQDC2MKPTAcGQ8phJM5jiTTAM5y mcW4B5wAJIArth5R/TCmh4UxpeC4M8r3nXXMB+PbbXhEm8woINx5Nj8PdE1C9ZPqwisH px5f+dwkEozIP/JpYXAQ7pYOz2vFdmFAtPOMmQfRSOHZekMsWM5rR0unPxBcr0XcQGfZ H7Kw== X-Gm-Message-State: AOAM533wN0uU62Q5LoUoc2jAjh1fslTvT+TwPkBNSwSjkrFi5a9GT7r4 pOD4iGNJT+gmFXqFC9rCEkgRUg== X-Google-Smtp-Source: ABdhPJw3kncz5bBeFvGNHHjQHWuKAmMjfyyD4wJtaWuf72K9qaqlzxZROoUJU/oZxzv4EwKivcuIhg== X-Received: by 2002:ac2:48ad:0:b0:472:4ef:d347 with SMTP id u13-20020ac248ad000000b0047204efd347mr892271lfg.422.1650806437307; Sun, 24 Apr 2022 06:20:37 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id l12-20020a056512332c00b0046d0e0e5b44sm1015877lfe.20.2022.04.24.06.20.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Apr 2022 06:20:36 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Stanimir Varbanov , Manivannan Sadhasivam Cc: Bjorn Helgaas , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v3 2/8] dt-bindings: pci/qcom, pcie: resets are not defined for msm8996 Date: Sun, 24 Apr 2022 16:20:28 +0300 Message-Id: <20220424132034.2235768-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220424132034.2235768-1-dmitry.baryshkov@linaro.org> References: <20220424132034.2235768-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On MSM8996/APQ8096 platforms the PCIe controller doesn't have any resets. So move the requirement stance under the corresponding if condition. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/pci/qcom,pcie.yaml | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 496ba3baf6d2..3a1d0c751217 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -113,8 +113,6 @@ required: - interrupt-map - clocks - clock-names - - resets - - reset-names allOf: - $ref: /schemas/pci/pci-bus.yaml# @@ -502,6 +500,18 @@ allOf: required: - power-domains + - if: + not: + properties: + compatibles: + contains: + enum: + - qcom,pcie-msm8996 + then: + required: + - resets + - reset-names + unevaluatedProperties: false examples: From patchwork Sun Apr 24 13:20:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 565643 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4599C4332F for ; Sun, 24 Apr 2022 13:20:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234968AbiDXNXy (ORCPT ); Sun, 24 Apr 2022 09:23:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234357AbiDXNXn (ORCPT ); Sun, 24 Apr 2022 09:23:43 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E0EAA1BF for ; Sun, 24 Apr 2022 06:20:40 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id w19so21898844lfu.11 for ; Sun, 24 Apr 2022 06:20:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=r63/wTPr4/PHvX+hVpl1ZWtMnqt2kinAFP5uZt5KkRE=; b=ALmRy/bFlY69tvB5T3mBwXhmSpEaxXkLGQShEotFEuSD4RWbrgMXqsnfjOdQADWurQ MSNPGTbc98Wdm+3Miz853Lmib3OnmUKCP42RpXC1Aq77m7qhjXIH3Cic4TBs6Udyoyar pTAfJiz3GA2lJeHChB3xgj9r7E1IhLzCFppv+3y56mPC1bv2mtaNOpqruPyNQkcRZ3Rv zcpaDntmzcVzBUuJT+UuY8ZU6WtjtY+uaVpue4cCjE+5ZMm46iA1uOHJsqVRx/CXVC71 3N+qdTsxglieVRY9mNJAXy5U9gZ0xpdn/txsIzP8I/6qlxORFuNpT4nTNcUoL1xUi0uP Kjuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=r63/wTPr4/PHvX+hVpl1ZWtMnqt2kinAFP5uZt5KkRE=; b=CJPRVGkmxMrFdhgytR1iK6Y9oh+TNv9FQA3OOqNJY1ayR+VCGessQWkWqFdWH9YK1V IPlk37g877YQ10gQQmNC8PjDnc83zPGksEg/KLdVb+S/MrghZRtJEB7zqoPha+LVsfXn cCPDmBjOrbz8o5fu0J2kR94OInrJLX5cG1+GqlLS9nJe/xfXic58DMfwk9EdkOIU35ls TU1duJnx3DbvaUU9//A/jo2ABFq03ZGBYCCFAzMCRgR+CQXtdi2daRPjMhuDQLQTC/gj OVmP4sA5QiKBCAezusySnPIphkGdkihMbch5LTbsE38+vzBPk+3Ijzw5ASz2w1z04cl3 vk0w== X-Gm-Message-State: AOAM530j54bG/uPnfaWLBd0ia/lDUyKpAQ4NKyqej8Q2RGCydpp+seoA C4RXv8F2z4lUC4gVo3OlNdY4WQ== X-Google-Smtp-Source: ABdhPJz62gajffXDWjGnPCI0nRAXA8BAM9TDCLtTQ1iSpcdCOb5MmZTMh76RuYP2hIZ3E7ueCPFOhg== X-Received: by 2002:a19:ca50:0:b0:471:f556:92b with SMTP id h16-20020a19ca50000000b00471f556092bmr5626331lfj.587.1650806438850; Sun, 24 Apr 2022 06:20:38 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id l12-20020a056512332c00b0046d0e0e5b44sm1015877lfe.20.2022.04.24.06.20.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Apr 2022 06:20:38 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Stanimir Varbanov , Manivannan Sadhasivam Cc: Bjorn Helgaas , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v3 4/8] dt-bindings: pci/qcom,pcie: add schema for sc7280 chipset Date: Sun, 24 Apr 2022 16:20:30 +0300 Message-Id: <20220424132034.2235768-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220424132034.2235768-1-dmitry.baryshkov@linaro.org> References: <20220424132034.2235768-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for sc7280-specific clock and reset definitions. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/pci/qcom,pcie.yaml | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index c79b12a0d315..48d56b073564 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -25,6 +25,7 @@ properties: - qcom,pcie-ipq4019 - qcom,pcie-ipq8074 - qcom,pcie-qcs404 + - qcom,pcie-sc7280 - qcom,pcie-sc8180x - qcom,pcie-sdm845 - qcom,pcie-sm8250 @@ -176,6 +177,7 @@ allOf: compatible: contains: enum: + - qcom,pcie-sc7280 - qcom,pcie-sc8180x - qcom,pcie-sm8250 - qcom,pcie-sm8450-pcie0 @@ -411,6 +413,36 @@ allOf: - const: pwr # PWR reset - const: ahb # AHB reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-sc7280 + then: + properties: + clocks: + minItems: 11 + maxItems: 11 + clock-names: + items: + - const: pipe # PIPE clock + - const: pipe_mux # PIPE MUX + - const: phy_pipe # PIPE output clock + - const: ref # REFERENCE clock + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: tbu # PCIe TBU clock + - const: ddrss_sf_tbu # PCIe SF TBU clock + resets: + maxItems: 1 + reset-names: + items: + - const: pci # PCIe core reset + - if: properties: compatible: From patchwork Sun Apr 24 13:20:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 565645 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62E61C43219 for ; Sun, 24 Apr 2022 13:20:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234577AbiDXNXq (ORCPT ); Sun, 24 Apr 2022 09:23:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234229AbiDXNXn (ORCPT ); Sun, 24 Apr 2022 09:23:43 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 660CEBCBE for ; Sun, 24 Apr 2022 06:20:42 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id t25so21918179lfg.7 for ; Sun, 24 Apr 2022 06:20:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ugzBs2Kot7nDRgqzctSCPbKbp3TBExEgizD4VqmQZYs=; b=wxjNhxSu1cOAeXUz1NDfA6RurOfh3RxSmKgHuAxyituc/XC7pxYJOSMpPVLl4S39+e Z4pgoOIEuis+tSWF4sFFBR/NBtB1oedJHlc6hclUk1xMsD4eSbaTkF61KW1HrTcsSULs jKZXQFkQQuedgYxyM4VFH50I6s2CimKXRRo4wM++eez+o4otZdlqEb+ms7ehQXmmdwS/ fO/VfYRu+V71TWGq28Ijl+0Uubu4pPCm/SOFK+GnzaSUNTtRmM4O1j5HHpmX3/IiiO0D 2dx/roxjE3GHKWgbnE0d7qqcjhjoiCztfzRp3QXwWi91rStmmfh1HTAIhF6n/9mFyt9a EtQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ugzBs2Kot7nDRgqzctSCPbKbp3TBExEgizD4VqmQZYs=; b=Wdrxc2B4gN0RKqhFbuyfh+Ol7R2v0e6vUqyryNEMpG0k5vR4Fg6xvka6mSH9qU5+6W 9N2VjdfJpCxdSzrR2puxqv3ycXbsdrDGnTZVsp2xyFPJStxsyVwZ1OJNn3LDpTAu1CRm rl6B3H4SrIBabzWmBsxfFBIkPKsU8R/ul4+j+oLX2iZ2DMUJgp+TQkow6M+fwPtcv6hI mZK+91V7VINUnwPdPTMsWTWSuuMunXU4nFvAANy2avlf6R9FuwFq3aOEgiHA7cX7hCRB 9vjG70DBBqcn4IGw4nm62SYtH+9Qp492bkDwoxDul+beW+DHGLUjZ4rlUpSgsw68XOcb EUmw== X-Gm-Message-State: AOAM5331UPuj04GEz8q/x4pjRsxN2k4Ej6vb+9CB5V0br2pYsflMXiDt cy5+uZ2stoPMGud62b37M4+uOg== X-Google-Smtp-Source: ABdhPJxAdluRACkgPt3HsP0Oqh6qv7tt5KORnXoVGmItASHTXT2Jr0bM3gIzmZIeVGs7b9k+Wb8djQ== X-Received: by 2002:a05:6512:238c:b0:471:8af8:7d67 with SMTP id c12-20020a056512238c00b004718af87d67mr9898721lfv.97.1650806440523; Sun, 24 Apr 2022 06:20:40 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id l12-20020a056512332c00b0046d0e0e5b44sm1015877lfe.20.2022.04.24.06.20.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Apr 2022 06:20:40 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Stanimir Varbanov , Manivannan Sadhasivam Cc: Bjorn Helgaas , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v3 6/8] arm: dts: qcom: stop using snps,dw-pcie falback Date: Sun, 24 Apr 2022 16:20:32 +0300 Message-Id: <20220424132034.2235768-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220424132034.2235768-1-dmitry.baryshkov@linaro.org> References: <20220424132034.2235768-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Qualcomm PCIe devices are not really compatible with the snps,dw-pcie. Unlike the generic IP core, they have special requirements regarding enabling clocks, toggling resets, using the PHY, etc. This is not to mention that platform snps-dw-pcie driver expects to find two IRQs declared, while Qualcomm platforms use just one. Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-apq8064.dtsi | 2 +- arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index a1c8ae516d21..ec2f98671a8c 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1370,7 +1370,7 @@ gfx3d1: iommu@7d00000 { }; pcie: pci@1b500000 { - compatible = "qcom,pcie-apq8064", "snps,dw-pcie"; + compatible = "qcom,pcie-apq8064"; reg = <0x1b500000 0x1000>, <0x1b502000 0x80>, <0x1b600000 0x100>, diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index a9d0566a3190..1e814dbe135e 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -412,7 +412,7 @@ restart@4ab000 { }; pcie0: pci@40000000 { - compatible = "qcom,pcie-ipq4019", "snps,dw-pcie"; + compatible = "qcom,pcie-ipq4019"; reg = <0x40000000 0xf1d 0x40000f20 0xa8 0x80000 0x2000 From patchwork Sun Apr 24 13:20:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 565644 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D20E0C433FE for ; Sun, 24 Apr 2022 13:20:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234055AbiDXNXt (ORCPT ); Sun, 24 Apr 2022 09:23:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234968AbiDXNXo (ORCPT ); Sun, 24 Apr 2022 09:23:44 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA307AE65 for ; Sun, 24 Apr 2022 06:20:43 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id v1so11456074ljv.3 for ; Sun, 24 Apr 2022 06:20:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eDT9kSu3JZdpsuMm2x+UDGGY32H0TbkhH7Wl08ke45c=; b=xxGoQVS+wblsqp24izvk1A+1/OOXXDUJfajlBvrKO43Rx0E1qXSdl300dbBIj3RabE tpjv8iUV+psStrwKnu7O3ykEcZkiEDnlC1Sqxkrc0YqEdadB7VGQVa5WltfnUcAcAaK0 AMCEV0iNlBPyKfWFmb7ESLzPk5GpGWXnb5hw9SsNPMZWc9iUMfcTTfTq/fi1YPE4Havr QuNqpjE+IeLUc1fnQx93oY3FLAjCcDLc4IUxe22c8M108cGXFcJS32Y/epxJctJujFO5 MjBbk6GeAFQBL4qN2/NtqTUz9FsGIsUmcKLvQG/93Ol7yFz6/f7qSGL0bHBiPvVUpNBM 94cQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eDT9kSu3JZdpsuMm2x+UDGGY32H0TbkhH7Wl08ke45c=; b=hS8JVRDfEMvnWVtEsmERIlmCTcOFrUdok3d9+zHBEUIacaC8DU7gb5NAdwI9FZnWwA A90l4IEcZhPX39xPo+CkQjHRcNHh/7wQWGDPF01s8Y+0XTC43Q/rrdZqhvboxW86hif0 V3WqRECENt98xsknsXmmfRDARDfyBzZoZITGLD6CB85wt28lxs+ADxijzLuODmaalY/7 NU3IiYax4u1vGF6K0vnNdIPT7tIPhn59mld/4WcBCmStvmy00zvHVKsCJvvISji/UsT2 HKiFPPsvvIg4tokUQ6C7epf8YWQfxULNhzESw034sDf0pRbach+/KLVNFYe7ob6Cw9DH eGuA== X-Gm-Message-State: AOAM532SxvQdAddMpepMlRG1eNUX7HX7vkj+zh49YAs2PhVFJb0I6F4V dO0K2QrYUYI8CSofj9xXhaMW9Q== X-Google-Smtp-Source: ABdhPJxG8F9B0tyGs0mXKGj6RIIbQmjUMliuhjL1N7cv/oCvQV1PRxZcx6ZS7ehipFFOkXaLR+rXhw== X-Received: by 2002:a2e:300a:0:b0:24d:b373:2d41 with SMTP id w10-20020a2e300a000000b0024db3732d41mr8076142ljw.486.1650806441330; Sun, 24 Apr 2022 06:20:41 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id l12-20020a056512332c00b0046d0e0e5b44sm1015877lfe.20.2022.04.24.06.20.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Apr 2022 06:20:40 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Stanimir Varbanov , Manivannan Sadhasivam Cc: Bjorn Helgaas , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v3 7/8] arm: dts: qcom-*: replace deprecated perst-gpio with perst-gpios Date: Sun, 24 Apr 2022 16:20:33 +0300 Message-Id: <20220424132034.2235768-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220424132034.2235768-1-dmitry.baryshkov@linaro.org> References: <20220424132034.2235768-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Replace deprecated perst-gpio properties with up-to-date perst-gpios in the arm32 Qualcomm Snapdragon device trees. Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 2 +- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 2 +- arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 2 +- arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 2 +- arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 +++--- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts index e068a8d0adf0..160291c5ebeb 100644 --- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts +++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts @@ -215,7 +215,7 @@ pci@1b500000 { vdda_refclk-supply = <&v3p3_fixed>; pinctrl-0 = <&pcie_pins>; pinctrl-names = "default"; - perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; + perst-gpios = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; }; amba { diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index 2638b380be20..8b1d540a5f65 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -285,7 +285,7 @@ pci@1b500000 { vdda_refclk-supply = <&ext_3p3v>; pinctrl-0 = <&pcie_pins>; pinctrl-names = "default"; - perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; + perst-gpios = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; }; qcom,ssbi@500000 { diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi index 7a337dc08741..872f64a12047 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi @@ -100,7 +100,7 @@ m25p80@0 { pci@40000000 { status = "okay"; - perst-gpio = <&tlmm 38 0x1>; + perst-gpios = <&tlmm 38 0x1>; }; qpic-nand@79b0000 { diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts index 06f9f2cb2fe9..ab1835b0fe40 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts @@ -10,7 +10,7 @@ / { soc { pci@40000000 { status = "okay"; - perst-gpio = <&tlmm 38 0x1>; + perst-gpios = <&tlmm 38 0x1>; }; spi@78b6000 { diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 996f4458d9fc..fa67cb6adcb8 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -842,7 +842,7 @@ pcie0: pci@1b500000 { pinctrl-names = "default"; status = "disabled"; - perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; + perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; }; pcie1: pci@1b700000 { @@ -893,7 +893,7 @@ pcie1: pci@1b700000 { pinctrl-names = "default"; status = "disabled"; - perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; + perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; }; pcie2: pci@1b900000 { @@ -944,7 +944,7 @@ pcie2: pci@1b900000 { pinctrl-names = "default"; status = "disabled"; - perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; + perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; }; nss_common: syscon@03000000 {