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([2607:fb90:80c1:f8a5:3d1f:84a9:7713:bf09]) by smtp.gmail.com with ESMTPSA id 204-20020a6302d5000000b00385f29b02b2sm23557644pgc.50.2022.04.21.10.31.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 10:31:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 1/7] target/rx: Put tb_flags into DisasContext Date: Thu, 21 Apr 2022 10:31:08 -0700 Message-Id: <20220421173114.48357-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220421173114.48357-1-richard.henderson@linaro.org> References: <20220421173114.48357-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Copy tb->flags into ctx->tb_flags; we'll want to modify this value throughout the tb in future. Signed-off-by: Richard Henderson Reviewed-by: Yoshinori Sato Message-Id: <20220417165130.695085-2-richard.henderson@linaro.org> --- target/rx/translate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/rx/translate.c b/target/rx/translate.c index c8a8991a63..c9db16553b 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -32,6 +32,7 @@ typedef struct DisasContext { DisasContextBase base; CPURXState *env; uint32_t pc; + uint32_t tb_flags; } DisasContext; typedef struct DisasCompare { @@ -231,7 +232,7 @@ static inline TCGv rx_load_source(DisasContext *ctx, TCGv mem, /* Processor mode check */ static int is_privileged(DisasContext *ctx, int is_exception) { - if (FIELD_EX32(ctx->base.tb->flags, PSW, PM)) { + if (FIELD_EX32(ctx->tb_flags, PSW, PM)) { if (is_exception) { gen_helper_raise_privilege_violation(cpu_env); } @@ -2292,6 +2293,7 @@ static void rx_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) CPURXState *env = cs->env_ptr; DisasContext *ctx = container_of(dcbase, DisasContext, base); ctx->env = env; + ctx->tb_flags = ctx->base.tb->flags; } static void rx_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) From patchwork Thu Apr 21 17:31:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564416 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp651812map; Thu, 21 Apr 2022 10:53:17 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz6mcIzY82ugnhyICDNn+R+Rg7SJkZ7Nvz2BZ/m8BOPkAT/8FIX/q4FftL/oIA1PKcx3teD X-Received: by 2002:a5b:cc:0:b0:63d:897a:ddab with SMTP id d12-20020a5b00cc000000b0063d897addabmr906048ybp.110.1650563597775; Thu, 21 Apr 2022 10:53:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650563597; cv=none; d=google.com; s=arc-20160816; b=mgpchCRkhREaikbM/3PYJ2oBzzXUbKrwOrYb6K+W/on2cBOmhb3NM3wCKCQkUbo75n j/kPg34H2640VUnE1aXXkg71DQ4f+pKUABU7xPibKBYIOh5lwIgZgJZ0uSUXMkYTnATW GlCuiV/R6IinDIrrp+SjzfWwXHUzOSOrMlupkMjiSJEjTyIzBWMxYSEpsPt6i4pKzU84 mWbtRQ8e+Op294vuOjct75hqxhzD479f/WJIYZNMbR13GGH3El+eQKHqMIqfqcH02A3a +1lMJUufvIeMl6UvvtPWtqo7vaUiYNLWDG64BXuGH6Q5bPjl2YL9X618DVg5VdXCqjZV w3fw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=iZwRb4fahw0JrRJgExptSGtesafOl/Y4v5cGBspLojo=; b=tkJZaJ/Cqq7YCLrpB22vY3YRhCl8RTf2s4YPy5gfZwjMT1uFd5Up5PFuGuh0HqQzxQ lzlbPReljPXjl5u3kfufH2Eh1kcDtGLhVWoi2imY/kV3pkK9R+jRgoeOUcN2dhhkzm3/ 2ikEVkmt1zTggctcjT1HBBcbu/JylWZw38sXi6nEfSHb1NQyuO2ropLcDtb4qgTS3Y5W 2xlpfsIZc5Gl+CpvnZKkUbkpFwvYi3TeE/kV4Sr8hOiyUz4pqLW+F3ziGO5fqgBITHxw QFJCutGjpXkTRJhpciqStt0vempOLzFpaoNVnuJtZrQJCFsam7YocCIivCzlGEpN1fjW jJSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZukOyKXk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:80c1:f8a5:3d1f:84a9:7713:bf09]) by smtp.gmail.com with ESMTPSA id 204-20020a6302d5000000b00385f29b02b2sm23557644pgc.50.2022.04.21.10.31.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 10:31:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 2/7] target/rx: Store PSW.U in tb->flags Date: Thu, 21 Apr 2022 10:31:09 -0700 Message-Id: <20220421173114.48357-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220421173114.48357-1-richard.henderson@linaro.org> References: <20220421173114.48357-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" With this, we don't need movcond to determine which stack pointer is current. Signed-off-by: Richard Henderson Reviewed-by: Yoshinori Sato Message-Id: <20220417165130.695085-3-richard.henderson@linaro.org> --- target/rx/cpu.h | 1 + target/rx/translate.c | 42 +++++++++++++++++++++++------------------- 2 files changed, 24 insertions(+), 19 deletions(-) diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 1c267f83bf..5655dffeff 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -149,6 +149,7 @@ static inline void cpu_get_tb_cpu_state(CPURXState *env, target_ulong *pc, *pc = env->pc; *cs_base = 0; *flags = FIELD_DP32(0, PSW, PM, env->psw_pm); + *flags = FIELD_DP32(*flags, PSW, U, env->psw_u); } static inline int cpu_mmu_index(CPURXState *env, bool ifetch) diff --git a/target/rx/translate.c b/target/rx/translate.c index c9db16553b..df7a8e5153 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -311,9 +311,8 @@ static void psw_cond(DisasCompare *dc, uint32_t cond) } } -static void move_from_cr(TCGv ret, int cr, uint32_t pc) +static void move_from_cr(DisasContext *ctx, TCGv ret, int cr, uint32_t pc) { - TCGv z = tcg_const_i32(0); switch (cr) { case 0: /* PSW */ gen_helper_pack_psw(ret, cpu_env); @@ -322,8 +321,11 @@ static void move_from_cr(TCGv ret, int cr, uint32_t pc) tcg_gen_movi_i32(ret, pc); break; case 2: /* USP */ - tcg_gen_movcond_i32(TCG_COND_NE, ret, - cpu_psw_u, z, cpu_sp, cpu_usp); + if (FIELD_EX32(ctx->tb_flags, PSW, U)) { + tcg_gen_mov_i32(ret, cpu_sp); + } else { + tcg_gen_mov_i32(ret, cpu_usp); + } break; case 3: /* FPSW */ tcg_gen_mov_i32(ret, cpu_fpsw); @@ -335,8 +337,11 @@ static void move_from_cr(TCGv ret, int cr, uint32_t pc) tcg_gen_mov_i32(ret, cpu_bpc); break; case 10: /* ISP */ - tcg_gen_movcond_i32(TCG_COND_EQ, ret, - cpu_psw_u, z, cpu_sp, cpu_isp); + if (FIELD_EX32(ctx->tb_flags, PSW, U)) { + tcg_gen_mov_i32(ret, cpu_isp); + } else { + tcg_gen_mov_i32(ret, cpu_sp); + } break; case 11: /* FINTV */ tcg_gen_mov_i32(ret, cpu_fintv); @@ -350,28 +355,27 @@ static void move_from_cr(TCGv ret, int cr, uint32_t pc) tcg_gen_movi_i32(ret, 0); break; } - tcg_temp_free(z); } static void move_to_cr(DisasContext *ctx, TCGv val, int cr) { - TCGv z; if (cr >= 8 && !is_privileged(ctx, 0)) { /* Some control registers can only be written in privileged mode. */ qemu_log_mask(LOG_GUEST_ERROR, "disallow control register write %s", rx_crname(cr)); return; } - z = tcg_const_i32(0); switch (cr) { case 0: /* PSW */ gen_helper_set_psw(cpu_env, val); break; /* case 1: to PC not supported */ case 2: /* USP */ - tcg_gen_mov_i32(cpu_usp, val); - tcg_gen_movcond_i32(TCG_COND_NE, cpu_sp, - cpu_psw_u, z, cpu_usp, cpu_sp); + if (FIELD_EX32(ctx->tb_flags, PSW, U)) { + tcg_gen_mov_i32(cpu_sp, val); + } else { + tcg_gen_mov_i32(cpu_usp, val); + } break; case 3: /* FPSW */ gen_helper_set_fpsw(cpu_env, val); @@ -383,10 +387,11 @@ static void move_to_cr(DisasContext *ctx, TCGv val, int cr) tcg_gen_mov_i32(cpu_bpc, val); break; case 10: /* ISP */ - tcg_gen_mov_i32(cpu_isp, val); - /* if PSW.U is 0, copy isp to r0 */ - tcg_gen_movcond_i32(TCG_COND_EQ, cpu_sp, - cpu_psw_u, z, cpu_isp, cpu_sp); + if (FIELD_EX32(ctx->tb_flags, PSW, U)) { + tcg_gen_mov_i32(cpu_isp, val); + } else { + tcg_gen_mov_i32(cpu_sp, val); + } break; case 11: /* FINTV */ tcg_gen_mov_i32(cpu_fintv, val); @@ -399,7 +404,6 @@ static void move_to_cr(DisasContext *ctx, TCGv val, int cr) "Unimplement control register %d", cr); break; } - tcg_temp_free(z); } static void push(TCGv val) @@ -683,7 +687,7 @@ static bool trans_PUSHC(DisasContext *ctx, arg_PUSHC *a) { TCGv val; val = tcg_temp_new(); - move_from_cr(val, a->cr, ctx->pc); + move_from_cr(ctx, val, a->cr, ctx->pc); push(val); tcg_temp_free(val); return true; @@ -2221,7 +2225,7 @@ static bool trans_MVTC_r(DisasContext *ctx, arg_MVTC_r *a) /* mvfc rs, rd */ static bool trans_MVFC(DisasContext *ctx, arg_MVFC *a) { - move_from_cr(cpu_regs[a->rd], a->cr, ctx->pc); + move_from_cr(ctx, cpu_regs[a->rd], a->cr, ctx->pc); return true; } From patchwork Thu Apr 21 17:31:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564413 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp638164map; 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([2607:fb90:80c1:f8a5:3d1f:84a9:7713:bf09]) by smtp.gmail.com with ESMTPSA id 204-20020a6302d5000000b00385f29b02b2sm23557644pgc.50.2022.04.21.10.31.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 10:31:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 3/7] target/rx: Move DISAS_UPDATE check for write to PSW Date: Thu, 21 Apr 2022 10:31:10 -0700 Message-Id: <20220421173114.48357-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220421173114.48357-1-richard.henderson@linaro.org> References: <20220421173114.48357-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Have one check in move_to_cr instead of one in each function that calls move_to_cr. Signed-off-by: Richard Henderson Reviewed-by: Yoshinori Sato Message-Id: <20220417165130.695085-4-richard.henderson@linaro.org> --- target/rx/translate.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/target/rx/translate.c b/target/rx/translate.c index df7a8e5153..bd4d110e8b 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -368,6 +368,10 @@ static void move_to_cr(DisasContext *ctx, TCGv val, int cr) switch (cr) { case 0: /* PSW */ gen_helper_set_psw(cpu_env, val); + if (is_privileged(ctx, 0)) { + /* PSW.{I,U} may be updated here. exit TB. */ + ctx->base.is_jmp = DISAS_UPDATE; + } break; /* case 1: to PC not supported */ case 2: /* USP */ @@ -631,10 +635,6 @@ static bool trans_POPC(DisasContext *ctx, arg_POPC *a) val = tcg_temp_new(); pop(val); move_to_cr(ctx, val, a->cr); - if (a->cr == 0 && is_privileged(ctx, 0)) { - /* PSW.I may be updated here. exit TB. */ - ctx->base.is_jmp = DISAS_UPDATE; - } tcg_temp_free(val); return true; } @@ -2205,9 +2205,6 @@ static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_i *a) imm = tcg_const_i32(a->imm); move_to_cr(ctx, imm, a->cr); - if (a->cr == 0 && is_privileged(ctx, 0)) { - ctx->base.is_jmp = DISAS_UPDATE; - } tcg_temp_free(imm); return true; } @@ -2216,9 +2213,6 @@ static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_i *a) static bool trans_MVTC_r(DisasContext *ctx, arg_MVTC_r *a) { move_to_cr(ctx, cpu_regs[a->rs], a->cr); - if (a->cr == 0 && is_privileged(ctx, 0)) { - ctx->base.is_jmp = DISAS_UPDATE; - } return true; } From patchwork Thu Apr 21 17:31:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564418 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp653467map; Thu, 21 Apr 2022 10:55:50 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx9r/ntHzPQS2ZxTQVfXPO5g2zbz2PQcWTgAw8pL0srHGsANJ3XSoedSQ4HOPv7jlZH6SZz X-Received: by 2002:a81:7455:0:b0:2ec:84:2c83 with SMTP id p82-20020a817455000000b002ec00842c83mr911234ywc.323.1650563750737; Thu, 21 Apr 2022 10:55:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650563750; cv=none; d=google.com; s=arc-20160816; b=RyGOEA4HyYKPOugz7hdTcq4fez0yhLXQYzYQyQPn7Mv5odyVU8mWg/4amYE1ZkMPoI hAWl6KGnfTZP3QUbSa0K2jinjkTS2bAwpUiizL/Ii7ydguuQgQmrm4wYDPIbTnJ0PNRt 6BrQ6q3dAJ8UL24G85kE6C3jn8lw53uPvllDeuiA/iCiA0reKovKflZgRuF56xAySWkZ 3ytms3AZ6iMwOKM5BpVGfPMTi0Nex1lHFbZZ11Pby06ZIrDuupgByTXhpSchYYFYi/aW LFvQMnvcd0fnfa645EKobB77/i8NQb8S1wfhJZnLK4gl+wyMRCwbRA1iOo4Zkgiej7Cb gOoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=uMjdlRZKRqMc37bzmt8n/trfJ/doq01lE7A/5TWhGjQ=; b=ZDQh/evcVPXVuwdMJOLgicVjsUo5Csbzjnt7ekmWukaY/xSqbHatjMQYq22WPyc1xc xn1Gw0XJJDCb0L9SjpWWE+yU7y6VT4ACDn5Clf0l08UCYFaK1AIb3Us6iqxL4+p85kGL U5ACNn+RrP/ew5YjeBd0QuSiftftjgO8z0UTjkBG+jjVVPuDRyP18uwuV6R6bMMF1ECd kDe1IVXPrTnnrU04kWAaDcRIYW+2f9jueYckzWWcaoBjk+lmbxLBhLrUcqIs0y4xHMjt chplgpGO91G68jMK0Y6SNg8bQtxpRpSVj/Ji7/0BarsJLT46kj8jV/7lvcItv929yv8Z 9Tcg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SnsXwAjR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:80c1:f8a5:3d1f:84a9:7713:bf09]) by smtp.gmail.com with ESMTPSA id 204-20020a6302d5000000b00385f29b02b2sm23557644pgc.50.2022.04.21.10.31.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 10:31:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 4/7] target/rx: Swap stack pointers on clrpsw/setpsw instruction Date: Thu, 21 Apr 2022 10:31:11 -0700 Message-Id: <20220421173114.48357-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220421173114.48357-1-richard.henderson@linaro.org> References: <20220421173114.48357-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tomoaki Kawada , Yoshinori Sato Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We properly perform this swap in helper_set_psw for MVTC, but we missed doing so for the CLRPSW/SETPSW of the U bit. Reported-by: Tomoaki Kawada Signed-off-by: Richard Henderson Reviewed-by: Yoshinori Sato Message-Id: <20220417165130.695085-5-richard.henderson@linaro.org> --- target/rx/translate.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/rx/translate.c b/target/rx/translate.c index bd4d110e8b..63c062993e 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -2165,7 +2165,12 @@ static inline void clrsetpsw(DisasContext *ctx, int cb, int val) ctx->base.is_jmp = DISAS_UPDATE; break; case PSW_U: - tcg_gen_movi_i32(cpu_psw_u, val); + if (FIELD_EX32(ctx->tb_flags, PSW, U) != val) { + ctx->tb_flags = FIELD_DP32(ctx->tb_flags, PSW, U, val); + tcg_gen_movi_i32(cpu_psw_u, val); + tcg_gen_mov_i32(val ? cpu_isp : cpu_usp, cpu_sp); + tcg_gen_mov_i32(cpu_sp, val ? cpu_usp : cpu_isp); + } break; default: qemu_log_mask(LOG_GUEST_ERROR, "Invalid distination %d", cb); From patchwork Thu Apr 21 17:31:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564419 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp654418map; Thu, 21 Apr 2022 10:57:26 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxjfBmJn0FSiM2+R1u8NBAM/GTSwR+MW088WFxy9o/iGNmU3aqCWuxvcCY7C1GVACMGmZYT X-Received: by 2002:a0d:e384:0:b0:2eb:2bc7:a80d with SMTP id m126-20020a0de384000000b002eb2bc7a80dmr924933ywe.41.1650563846194; Thu, 21 Apr 2022 10:57:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650563846; cv=none; d=google.com; s=arc-20160816; b=WxqwILQI2CRvW9zFqjtsl4L74XYpf7UiMHok0vV4kqRmjT4u4mg6azfvvAGEpszr5E 95LFh1PB4Ww6OolH0rtnGeZa3LapdSg06Phqzf4HOpydjnizbWEamEkHnJaQ6X4ygi3P Vv1IDcy1CfW8uKhkc2+Cl2fqso2L58VU/5YaJc70ZW3D3jnTfoVyfcbg3kbSEwyfwZ/V XoLxSO5CwEq/m8yRZXt+lMiLRT3uMGwDDSJcrK2xfh/CFUG34xWv71oA1UzClKg3Wwij BFZ08U6mnOgy4Q1HunCI54dwsfVwfXOBXoOpOE/Rlz7rjE+3nu1gMnmcFJJDWV9bZfKt q6bQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=YihlbUdW9nVb05t909DK2GaeZ9Rq4UBEpzdddYMos/s=; b=ZI6xnDrdBZB8XkFWAS7VVsRUV2LWMauY7pWU+liOyzKX9Xn2H7Gllc+TQuteA7IhCl r4x/HoJNaQ0ec9+haMzk4yZnWbcPKyjVIBRmLQak6n5lniBmdcR9zin1msp7ldBr0ZTl tS3l/k3R1LjCFmy3vi8DiKTiw6vuKtZ4lOkyhguhNvKKJULsg9UIURz8R5zZ3bdnrKyk 0e9QxeF32ICLdOFJyosWBHmjJlVojeB0ORfZZzjMfHx7aTwQfKi+oRXCdDADrpD+WQXY 3P+pp9wyWOwW5RDwfnbCYWbvaNm0BP7455jYL+KtzMLWik4WGrcaRPI9gfeoqdE7EJLL rIwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KvCMqeSG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:80c1:f8a5:3d1f:84a9:7713:bf09]) by smtp.gmail.com with ESMTPSA id 204-20020a6302d5000000b00385f29b02b2sm23557644pgc.50.2022.04.21.10.31.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 10:31:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 5/7] hw/rx: rx-gdbsim DTB load address aligned of 16byte. Date: Thu, 21 Apr 2022 10:31:12 -0700 Message-Id: <20220421173114.48357-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220421173114.48357-1-richard.henderson@linaro.org> References: <20220421173114.48357-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Yoshinori Sato Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Yoshinori Sato Linux kernel required alined address of DTB. But missing align in dtb load function. Fixed to load to the correct address. Signed-off-by: Yoshinori Sato Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20220207132758.84403-1-ysato@users.sourceforge.jp> Signed-off-by: Richard Henderson --- hw/rx/rx-gdbsim.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/rx/rx-gdbsim.c b/hw/rx/rx-gdbsim.c index 64f897e5b1..be147b4bd9 100644 --- a/hw/rx/rx-gdbsim.c +++ b/hw/rx/rx-gdbsim.c @@ -141,7 +141,7 @@ static void rx_gdbsim_init(MachineState *machine) exit(1); } /* DTB is located at the end of SDRAM space. */ - dtb_offset = machine->ram_size - dtb_size; + dtb_offset = ROUND_DOWN(machine->ram_size - dtb_size, 16); rom_add_blob_fixed("dtb", dtb, dtb_size, SDRAM_BASE + dtb_offset); /* Set dtb address to R1 */ From patchwork Thu Apr 21 17:31:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564420 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp655711map; Thu, 21 Apr 2022 10:59:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxyLIk46+yVOKy4k6Bd9fbJH7vuSRKdtQfr1TTBNE6lHxeo6ITZ/GxLqOeAyBH7k2A5X2Yx X-Received: by 2002:a25:1583:0:b0:641:183a:3c30 with SMTP id 125-20020a251583000000b00641183a3c30mr888133ybv.471.1650563983919; Thu, 21 Apr 2022 10:59:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650563983; cv=none; d=google.com; s=arc-20160816; b=1LDw3Pzr20+CfENXkNSFgrSi/nExrP0u5iXyx9VcLQG1lMphkhhhwW66LxnitwqGmF Q6yd/qwZ/6QJX/pyMry3N4dC6OkDO7URtuoaL/FXkhv/9Y3pbnJT0hM+v8EHw2F1WWcJ oOVPy1abk2Wo21LvGe4iXYheY+Ufvs3x5KDzJzUmvsU8REyKo5y6zMjMmlBrufC53Wgt FnyFBSgC9Rt3/88oSfjT10jhtE7/kUY612Jaobzh6WgxfyrQlHovhSvebOP3vw1qcuPS LBjfAq2ARsdHq3SmqGsF3WGZG9n+1K4qmWsrNs97SAq5/zM9Az533vsErYCi26+cWv0l +8eA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=vnUo923wbj7XIwCBnfHZzIv0sYzZ9mMty9XfzDgDwDE=; b=hZlyDK2T2pUGLb6SbrU4YQGILrUIO0BFKAHuXkSM7tIXyG1uwrPf0my0bVEwg+z1BU zunp0Pf/U5wnCpSL4ybGl28pQurI9AWRxKHhAMGlJSOvB/aMs7wvFSjcZOvNFZ6imHxc bI5cVZnIFVQDoiB3YAfDcDWXRpO+LLkLrj7IT7PvOicJObLZRE8EBmWj+Ld14TjsiDqb qzPq15r8/2VqraIxpxGK8ynNQjLawqBHZqYJIjmfm4YIK/iXCKAAW64eDvX0lg0BVUwT fu1zMc3yMFbD6h0U3OwkVeKeM1PqI1ASJrc3kfeODUgfwyuzR5TUq1p9V6R2GlqeVf8A A1/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SM0tk9g1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:80c1:f8a5:3d1f:84a9:7713:bf09]) by smtp.gmail.com with ESMTPSA id 204-20020a6302d5000000b00385f29b02b2sm23557644pgc.50.2022.04.21.10.31.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 10:31:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 6/7] target/rx: set PSW.I when executing wait instruction Date: Thu, 21 Apr 2022 10:31:13 -0700 Message-Id: <20220421173114.48357-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220421173114.48357-1-richard.henderson@linaro.org> References: <20220421173114.48357-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tomoaki Kawada , Yoshinori Sato Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Tomoaki Kawada This patch fixes the implementation of the wait instruction to implicitly update PSW.I as required by the ISA specification. Signed-off-by: Tomoaki Kawada Reviewed-by: Yoshinori Sato Reviewed-by: Richard Henderson Message-Id: <20220417045937.2128699-1-i@yvt.jp> Signed-off-by: Richard Henderson --- target/rx/op_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c index 11f952d340..81645adde3 100644 --- a/target/rx/op_helper.c +++ b/target/rx/op_helper.c @@ -448,6 +448,7 @@ void QEMU_NORETURN helper_wait(CPURXState *env) cs->halted = 1; env->in_sleep = 1; + env->psw_i = 1; raise_exception(env, EXCP_HLT, 0); } From patchwork Thu Apr 21 17:31:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 564421 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp659056map; Thu, 21 Apr 2022 11:03:27 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwRnL7KoZCQxnHqGYTD9+tfJY9Jj3lRcybqOPsNr19xSOb2K3t5HifToEKy11CfUjKY6Mck X-Received: by 2002:a25:ab33:0:b0:645:7995:86b6 with SMTP id u48-20020a25ab33000000b00645799586b6mr1002584ybi.60.1650564207303; Thu, 21 Apr 2022 11:03:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1650564207; cv=none; d=google.com; s=arc-20160816; b=VKSFxwxPaSrhPklVyWzYEgJum1Xi0gkO5MO/gobS3EJbn3nTN88eYNyjfgP9w8PlG9 0sc9sWSEhmfAur3408GLcYxb/8aLI6/OLW3NLD6wD5xb4Tpsf1FxkL7YLyxlzLRdWyu9 4Bd+ft9lWEddwvEQtGi3emagMRZxqEHGCWLFhjRI1bdiOjRmPl6hTP6+TuSgLiWxH6qg VOZihq/8Etrs1KUCd5BdQMG78y8LY1lxcRJR+EJ1gMsO/7S6RMTwvEf8fofYWtvLiFXU 5FmjXJRM59ztvLtc1tCvsHNxnPk0YnItbdSVkwlK5PYEPpdfgCvaAq10Q3TdyhmUVpTh zn2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ezPeHZwRhMK3J/mr8sMEjy7zxNhMKWlBGFUNACOiAjs=; b=0TzI/o9ohXATzCgmK+fmrIfufWLOv5trTF3em2L+MrxwYKgvVK3cJdMNX8JieLrMHC dgs/yUFgRLapZDd2MEtInsRhhmntwvc9ItS4RZLTelhC5rfS+JARC2W9+UgFrjhQAWL4 ymogzJ6R1Di2f5+flhOpeElBEMyj2+6mHPg8AJEI5bEm62EldZRe79Nvq1p93m1ZAjTT BniAb6Flm/M36wq6hHrtm6SsV3/gtdwyGkloWjm/UIwBf03n9Z27rNVwQAu7yHTVwBwk UfJhnqJQ8hAbMf5yMFDKO394Uh+lxjWvNT9a0PkHgNmkGs7AX9zy++qbkA+a+DSltUzk zv1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XJsmN6C7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2607:fb90:80c1:f8a5:3d1f:84a9:7713:bf09]) by smtp.gmail.com with ESMTPSA id 204-20020a6302d5000000b00385f29b02b2sm23557644pgc.50.2022.04.21.10.31.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 10:31:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 7/7] target/rx: update PC correctly in wait instruction Date: Thu, 21 Apr 2022 10:31:14 -0700 Message-Id: <20220421173114.48357-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220421173114.48357-1-richard.henderson@linaro.org> References: <20220421173114.48357-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tomoaki Kawada , Yoshinori Sato Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Tomoaki Kawada `cpu_pc` at this point does not necessary point to the current instruction (i.e., the wait instruction being translated), so it's incorrect to calculate the new value of `cpu_pc` based on this. It must be updated with `ctx->base.pc_next`, which contains the correct address of the next instruction. This change fixes the wait instruction skipping the subsequent branch when used in an idle loop like this: 0: wait bra.b 0b brk // should be unreachable Signed-off-by: Tomoaki Kawada Reviewed-by: Yoshinori Sato Reviewed-by: Richard Henderson Message-Id: <20220417060224.2131788-1-i@yvt.jp> Signed-off-by: Richard Henderson --- target/rx/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/rx/translate.c b/target/rx/translate.c index 63c062993e..62aee66937 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -2285,7 +2285,7 @@ static bool trans_INT(DisasContext *ctx, arg_INT *a) static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a) { if (is_privileged(ctx, 1)) { - tcg_gen_addi_i32(cpu_pc, cpu_pc, 2); + tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); gen_helper_wait(cpu_env); } return true;