From patchwork Wed Apr 20 15:56:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Schiffer X-Patchwork-Id: 564284 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F7AAC433F5 for ; Wed, 20 Apr 2022 15:57:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238253AbiDTQAD (ORCPT ); Wed, 20 Apr 2022 12:00:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37756 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242908AbiDTQAC (ORCPT ); Wed, 20 Apr 2022 12:00:02 -0400 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4833E2A24C; Wed, 20 Apr 2022 08:57:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1650470235; x=1682006235; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=b5buSbS/Y6YBWpO3y41GUfU3t//7M1BjS48dP9Par3w=; b=QH3YmD+Ir6Xr0a32moDtpzICUFCA9LpT6TJWnu/9tzvQMsDBWAvvW8Ah KQuGonp0ie2WFvpQ6SFAYe9QdMRPGPew4oRuSGklEuBMzWfu5V3aI71FM hDIOGrBLke4KcXDr1I7XkdUDk60jwAImD54yh8fY0X3JKfsYbVfnxbTA5 W3sb3j9nPoMpCH8plrSQ8uVd1kmNWWGpdgplEiukuQ52+SazRnUwEqXg/ bmOrWMRj8ucQKSti8BVArLhpI9gISvC1OEVx5z3gJbOIml6Q+p4S/n74s q9qSnVJ/Tvtba2WjzxvkN4tgKFAtflMVlZdMVewfx7A58FOhXWR7LQe4M g==; X-IronPort-AV: E=Sophos;i="5.90,276,1643670000"; d="scan'208";a="23392890" Received: from unknown (HELO tq-pgp-pr1.tq-net.de) ([192.168.6.15]) by mx1-pgp.tq-group.com with ESMTP; 20 Apr 2022 17:57:13 +0200 Received: from mx1.tq-group.com ([192.168.6.7]) by tq-pgp-pr1.tq-net.de (PGP Universal service); Wed, 20 Apr 2022 17:57:13 +0200 X-PGP-Universal: processed; by tq-pgp-pr1.tq-net.de on Wed, 20 Apr 2022 17:57:13 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1650470233; x=1682006233; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=b5buSbS/Y6YBWpO3y41GUfU3t//7M1BjS48dP9Par3w=; b=KAz8L97BaMoM7aKwZN655b9AdwPXyIn9pG5nRQyjwzRlVezjZeK4BcOz pUTteTko2Ai1JjDJeYNnOdJoKmu04Cl21bBzhish+tzD/25B+Zr8QzP51 9JFuxhbc9JHjCKY5YIX2t8tDZvo+XBNZ+1gAXreqvqhSqMyH9pCgfIJnG k9W0JCvflZBp1bRFhm8chJ9/EO4HNfsvgfnCKSWxELEsj3PKICKXxmBLO lDI2fP06jxlDigi9AXJoulOzGzj1r7FuVj2zvpw816r2Q5mrj562Lgkz9 6YaWDjkJaiWpOgGi6M2pFanKL1M7oTcZDcLQ0WOOeQmi/s0enEUjKM2fe g==; X-IronPort-AV: E=Sophos;i="5.90,276,1643670000"; d="scan'208";a="23392889" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 20 Apr 2022 17:57:13 +0200 Received: from localhost.localdomain (SCHIFFERM-M2.tq-net.de [10.121.49.14]) by vtuxmail01.tq-net.de (Postfix) with ESMTPA id 08F26280070; Wed, 20 Apr 2022 17:57:13 +0200 (CEST) From: Matthias Schiffer To: Mark Brown Cc: Pratyush Yadav , Tudor Ambarus , Vignesh Raghavendra , Ramuthevar Vadivel Murugan , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Schiffer Subject: [PATCH v2 1/2] spi: cadence-quadspi: drop cqspi_set_protocol() Date: Wed, 20 Apr 2022 17:56:15 +0200 Message-Id: <20220420155616.281730-1-matthias.schiffer@ew.tq-group.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org As suggested, this removes the whole cqspi_set_protocol() function, as it is not actually needed: - Checks for unsupported operations are already handled by supports_op(), removing the need to distinguish DTR and non-DTR modes in the buswidth setup - supports_op() ensures that the DTR flags match for all relevant parts of an operation, so op->cmd.dtr can be used instead of copying the flag to the cqspi_flash_pdata - The logic in cqspi_set_protocol() is moved to cqspi_calc_rdreg() and cqspi_write_setup() (with a helper macro CQSPI_OP_WIDTH()) The helper macro checks nbytes instead of buswidth for 0, for consistency with supports_op() etc. Suggested-by: Pratyush Yadav Signed-off-by: Matthias Schiffer Reviewed-by: Pratyush Yadav --- v2: remove cqspi_set_protocol() instead of simplifying it drivers/spi/spi-cadence-quadspi.c | 130 +++++++----------------------- 1 file changed, 27 insertions(+), 103 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 19686fb47bb3..8c12c6dd58ae 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -43,6 +43,8 @@ /* Capabilities */ #define CQSPI_SUPPORTS_OCTAL BIT(0) +#define CQSPI_OP_WIDTH(part) ((part).nbytes ? ilog2((part).buswidth) : 0) + struct cqspi_st; struct cqspi_flash_pdata { @@ -53,10 +55,6 @@ struct cqspi_flash_pdata { u32 tsd2d_ns; u32 tchsh_ns; u32 tslch_ns; - u8 inst_width; - u8 addr_width; - u8 data_width; - bool dtr; u8 cs; }; @@ -343,18 +341,18 @@ static irqreturn_t cqspi_irq_handler(int this_irq, void *dev) return IRQ_HANDLED; } -static unsigned int cqspi_calc_rdreg(struct cqspi_flash_pdata *f_pdata) +static unsigned int cqspi_calc_rdreg(const struct spi_mem_op *op) { u32 rdreg = 0; - rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; - rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; - rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; + rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; + rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; + rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; return rdreg; } -static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op, bool dtr) +static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op) { unsigned int dummy_clk; @@ -362,66 +360,12 @@ static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op, bool dtr) return 0; dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); - if (dtr) + if (op->cmd.dtr) dummy_clk /= 2; return dummy_clk; } -static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata, - const struct spi_mem_op *op) -{ - /* - * For an op to be DTR, cmd phase along with every other non-empty - * phase should have dtr field set to 1. If an op phase has zero - * nbytes, ignore its dtr field; otherwise, check its dtr field. - */ - f_pdata->dtr = op->cmd.dtr && - (!op->addr.nbytes || op->addr.dtr) && - (!op->data.nbytes || op->data.dtr); - - f_pdata->inst_width = 0; - if (op->cmd.buswidth) - f_pdata->inst_width = ilog2(op->cmd.buswidth); - - f_pdata->addr_width = 0; - if (op->addr.buswidth) - f_pdata->addr_width = ilog2(op->addr.buswidth); - - f_pdata->data_width = 0; - if (op->data.buswidth) - f_pdata->data_width = ilog2(op->data.buswidth); - - /* Right now we only support 8-8-8 DTR mode. */ - if (f_pdata->dtr) { - switch (op->cmd.buswidth) { - case 0: - case 8: - break; - default: - return -EINVAL; - } - - switch (op->addr.buswidth) { - case 0: - case 8: - break; - default: - return -EINVAL; - } - - switch (op->data.buswidth) { - case 0: - case 8: - break; - default: - return -EINVAL; - } - } - - return 0; -} - static int cqspi_wait_idle(struct cqspi_st *cqspi) { const unsigned int poll_idle_retry = 3; @@ -503,8 +447,7 @@ static int cqspi_setup_opcode_ext(struct cqspi_flash_pdata *f_pdata, } static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata, - const struct spi_mem_op *op, unsigned int shift, - bool enable) + const struct spi_mem_op *op, unsigned int shift) { struct cqspi_st *cqspi = f_pdata->cqspi; void __iomem *reg_base = cqspi->iobase; @@ -517,7 +460,7 @@ static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata, * We enable dual byte opcode here. The callers have to set up the * extension opcode based on which type of operation it is. */ - if (enable) { + if (op->cmd.dtr) { reg |= CQSPI_REG_CONFIG_DTR_PROTO; reg |= CQSPI_REG_CONFIG_DUAL_OPCODE; @@ -549,12 +492,7 @@ static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, size_t read_len; int status; - status = cqspi_set_protocol(f_pdata, op); - if (status) - return status; - - status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB, - f_pdata->dtr); + status = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); if (status) return status; @@ -565,17 +503,17 @@ static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, return -EINVAL; } - if (f_pdata->dtr) + if (op->cmd.dtr) opcode = op->cmd.opcode >> 8; else opcode = op->cmd.opcode; reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB; - rdreg = cqspi_calc_rdreg(f_pdata); + rdreg = cqspi_calc_rdreg(op); writel(rdreg, reg_base + CQSPI_REG_RD_INSTR); - dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr); + dummy_clk = cqspi_calc_dummy(op); if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) return -EOPNOTSUPP; @@ -622,12 +560,7 @@ static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, size_t write_len; int ret; - ret = cqspi_set_protocol(f_pdata, op); - if (ret) - return ret; - - ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB, - f_pdata->dtr); + ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_STIG_LSB); if (ret) return ret; @@ -638,10 +571,10 @@ static int cqspi_command_write(struct cqspi_flash_pdata *f_pdata, return -EINVAL; } - reg = cqspi_calc_rdreg(f_pdata); + reg = cqspi_calc_rdreg(op); writel(reg, reg_base + CQSPI_REG_RD_INSTR); - if (f_pdata->dtr) + if (op->cmd.dtr) opcode = op->cmd.opcode >> 8; else opcode = op->cmd.opcode; @@ -688,21 +621,20 @@ static int cqspi_read_setup(struct cqspi_flash_pdata *f_pdata, int ret; u8 opcode; - ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB, - f_pdata->dtr); + ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_READ_LSB); if (ret) return ret; - if (f_pdata->dtr) + if (op->cmd.dtr) opcode = op->cmd.opcode >> 8; else opcode = op->cmd.opcode; reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; - reg |= cqspi_calc_rdreg(f_pdata); + reg |= cqspi_calc_rdreg(op); /* Setup dummy clock cycles */ - dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr); + dummy_clk = cqspi_calc_dummy(op); if (dummy_clk > CQSPI_DUMMY_CLKS_MAX) return -EOPNOTSUPP; @@ -947,22 +879,21 @@ static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata, void __iomem *reg_base = cqspi->iobase; u8 opcode; - ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB, - f_pdata->dtr); + ret = cqspi_enable_dtr(f_pdata, op, CQSPI_REG_OP_EXT_WRITE_LSB); if (ret) return ret; - if (f_pdata->dtr) + if (op->cmd.dtr) opcode = op->cmd.opcode >> 8; else opcode = op->cmd.opcode; /* Set opcode. */ reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; - reg |= f_pdata->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; - reg |= f_pdata->addr_width << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; + reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; + reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; writel(reg, reg_base + CQSPI_REG_WR_INSTR); - reg = cqspi_calc_rdreg(f_pdata); + reg = cqspi_calc_rdreg(op); writel(reg, reg_base + CQSPI_REG_RD_INSTR); /* @@ -1244,10 +1175,6 @@ static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, const u_char *buf = op->data.buf.out; int ret; - ret = cqspi_set_protocol(f_pdata, op); - if (ret) - return ret; - ret = cqspi_write_setup(f_pdata, op); if (ret) return ret; @@ -1260,7 +1187,7 @@ static ssize_t cqspi_write(struct cqspi_flash_pdata *f_pdata, * mode. So, we can not use direct mode when in DTR mode for writing * data. */ - if (!f_pdata->dtr && cqspi->use_direct_mode && + if (!op->cmd.dtr && cqspi->use_direct_mode && ((to + len) <= cqspi->ahb_size)) { memcpy_toio(cqspi->ahb_base + to, buf, len); return cqspi_wait_idle(cqspi); @@ -1348,9 +1275,6 @@ static ssize_t cqspi_read(struct cqspi_flash_pdata *f_pdata, int ret; ddata = of_device_get_match_data(dev); - ret = cqspi_set_protocol(f_pdata, op); - if (ret) - return ret; ret = cqspi_read_setup(f_pdata, op); if (ret) From patchwork Wed Apr 20 15:56:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Schiffer X-Patchwork-Id: 567040 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 421DBC433FE for ; Wed, 20 Apr 2022 15:57:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353247AbiDTQAE (ORCPT ); Wed, 20 Apr 2022 12:00:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350019AbiDTQAD (ORCPT ); Wed, 20 Apr 2022 12:00:03 -0400 Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C37FC2ED5D; Wed, 20 Apr 2022 08:57:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1650470237; x=1682006237; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=S98vaXkbz8UZkBJ9FEMnbk+W6levwYfoDCblKiAVM20=; b=hzq1b4jquH4wQ+Xty9pUdCKh3UDj8yEJacSstOc6ziy6sY0BE6709pqj qCcIU9fbDsDUxUYvcdbGgPEiqco6FTt/rkXOXRB+d4nrlM3y4H93khAtL 0HSfdsjXOoGw7nOu0h6BRz2nOGP4v6w0Ab0K2uVx4LjI3EdsyizQnq5JS JwQx0euU3bvwPezxOCEhJNBeHMllpQD0r8cDNOTSiV1MrGg8rb+1PELbu DKHxvv0tQz6ZTDobvXmU23lqXnkcJyBniIkMIw8gcVsW29JNUOwC7b74/ HvPjO8Si7pxzM1bh5XEM8DvfS7qQ+ab2O02TpEv9hiqApEJN/d1ovaUVy Q==; X-IronPort-AV: E=Sophos;i="5.90,276,1643670000"; d="scan'208";a="23392892" Received: from unknown (HELO tq-pgp-pr1.tq-net.de) ([192.168.6.15]) by mx1-pgp.tq-group.com with ESMTP; 20 Apr 2022 17:57:15 +0200 Received: from mx1.tq-group.com ([192.168.6.7]) by tq-pgp-pr1.tq-net.de (PGP Universal service); Wed, 20 Apr 2022 17:57:15 +0200 X-PGP-Universal: processed; by tq-pgp-pr1.tq-net.de on Wed, 20 Apr 2022 17:57:15 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1650470235; x=1682006235; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=S98vaXkbz8UZkBJ9FEMnbk+W6levwYfoDCblKiAVM20=; b=DQrL6l2SiOoxKg5q/nTMqixNBoEGggjvvt3eeraTH0YM4f88s/hWl42V s8KOGt0hY8gtoI+guXiD8Ttbv7HY4kc8vyoO5o0VNdQwc8t0PmOSg1rHM FUKBla+K3XIAw0n+PgqoYG3IpaUnWPAtCRkW9RRnUKr2us9z+9XKJ4May NBmt31bik37WYIrwBh9skiYTUwtMeeVxdjPltagNSJQ2ePyFWLJu9W2D1 el08blOadz7KXnFwOBEWODXnUoLBvUnZaGASNH4piSOLpbvo8SJWlSl1Y zBmyGUjISB/kvMoPMXlHHWZuLoY5qImMpBlWCRXH8yyr6pMdzCr7KNc/K g==; X-IronPort-AV: E=Sophos;i="5.90,276,1643670000"; d="scan'208";a="23392891" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 20 Apr 2022 17:57:15 +0200 Received: from localhost.localdomain (SCHIFFERM-M2.tq-net.de [10.121.49.14]) by vtuxmail01.tq-net.de (Postfix) with ESMTPA id C2A19280070; Wed, 20 Apr 2022 17:57:14 +0200 (CEST) From: Matthias Schiffer To: Mark Brown Cc: Pratyush Yadav , Tudor Ambarus , Vignesh Raghavendra , Ramuthevar Vadivel Murugan , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Matthias Schiffer Subject: [PATCH v2 2/2] spi: cadence-quadspi: allow operations with cmd/addr buswidth >1 Date: Wed, 20 Apr 2022 17:56:16 +0200 Message-Id: <20220420155616.281730-2-matthias.schiffer@ew.tq-group.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220420155616.281730-1-matthias.schiffer@ew.tq-group.com> References: <20220420155616.281730-1-matthias.schiffer@ew.tq-group.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org With the removal of the incorrect logic of cqspi_set_protocol(), ops with cmd/addr buswidth >1 are now working correctly. Tested on a TI AM64x with a Macronix MX25U51245G QSPI flash using 1-4-4 operations. DTR operations are currently untested, so we leave them disabled for now (except for the previously allowed 8-8-8 ops). Signed-off-by: Matthias Schiffer --- v2: update commit message; no code changes drivers/spi/spi-cadence-quadspi.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 8c12c6dd58ae..0f7e28ef5209 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1347,13 +1347,7 @@ static bool cqspi_supports_mem_op(struct spi_mem *mem, return false; if (op->data.nbytes && op->data.buswidth != 8) return false; - } else if (all_false) { - /* Only 1-1-X ops are supported without DTR */ - if (op->cmd.nbytes && op->cmd.buswidth > 1) - return false; - if (op->addr.nbytes && op->addr.buswidth > 1) - return false; - } else { + } else if (!all_false) { /* Mixed DTR modes are not supported. */ return false; }