From patchwork Mon Apr 18 20:55:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 563151 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6099C433EF for ; Mon, 18 Apr 2022 20:55:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347845AbiDRU6G (ORCPT ); Mon, 18 Apr 2022 16:58:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38304 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237237AbiDRU6E (ORCPT ); Mon, 18 Apr 2022 16:58:04 -0400 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C4F315706 for ; Mon, 18 Apr 2022 13:55:24 -0700 (PDT) Received: by mail-pj1-x1034.google.com with SMTP id n11-20020a17090a73cb00b001d1d3a7116bso664719pjk.0 for ; Mon, 18 Apr 2022 13:55:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JoIn1027OXzmCOA2cCIKja8ksqjeKwGtO2KGzYKS9Ks=; b=sFoUtadypX7gqBjas8UAvAivDUUHJ3TkJ/7D7V3FS7IidpuxNkl4+GnnY+T3HKSvCp 9IBVuxpeTza06vtoznlZWV7zu5d+yj7uueGiZdOoFqdSlDxPYA/bFH9Pw8h7KUuDPeHa BYnA+pPQbi7Xqwa1r/WvifijgtO7RkTqck03FcrEdONmeCkB4AIB/QKT16U2v9BdumXa +XhSrs7Q5rQRNldzVYtpTeGhW+VZrnXhk/QgYIq2g29edpPA+xS68aULSj8Htqlfrdkh i6azEtVU1NyL6F9XcKbHAMoqhKZqHQCTwAVVDg7tPY9pTq3J71uhUkfIPRJpaY14Jc0O o6cQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JoIn1027OXzmCOA2cCIKja8ksqjeKwGtO2KGzYKS9Ks=; b=5QTEnaIgHExMEDygKR83bGEWBJt48MioR2whg0YOOakTG7u4JscSkdhBrYeFsmq32e CiMAB6aXTcSr/g+B2rcQSklIcHb7NJ7h1nN9T3ZlV1Fzlz4rdj8VhJJrkKvZ+LelyipK znc7rJs8BT6tvTRvsntR5DYEEZuOpyaQWjWRu5pBVyAPMbzfTJvkasGSkuSTZP9FMeLW YXE4rZAfFOs/6ePgLF0taBR5iqlIfi2jh4aUH5mewz9errj0KRXxNfCfXOKf8+Y1Jff0 HOF85uqD8tfxpqDj3u5GbhthtSxcjwbQVFRDR3XATq9uuVR2/scm2RjnlzwDsg4a57Ml 2xNA== X-Gm-Message-State: AOAM532CInC9BfJVigE9a0Sb/Wn0T1rDqeXfGUfBhYs+9k8NdJ68HtDS gp1MjSYV3Zo17j+7zAR0Uj9D0w== X-Google-Smtp-Source: ABdhPJya8fFGhzAYTYuKY4DalPfaHk5aNAbffZoalJqGmb12zkn+RpS27NCCDphkFcei7WJjWEBecw== X-Received: by 2002:a17:90b:1b52:b0:1d2:8d55:ad6d with SMTP id nv18-20020a17090b1b5200b001d28d55ad6dmr8382779pjb.223.1650315323758; Mon, 18 Apr 2022 13:55:23 -0700 (PDT) Received: from localhost.localdomain ([223.233.64.97]) by smtp.gmail.com with ESMTPSA id q60-20020a17090a17c200b001cd567fecaesm13498859pja.26.2022.04.18.13.55.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Apr 2022 13:55:23 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, agross@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, vkoul@kernel.org, bjorn.andersson@linaro.org Subject: [PATCH v3 1/4] dt-bindings: phy: qcom,qmp: Mark '#clock-cells' as a 'optional' property Date: Tue, 19 Apr 2022 02:25:06 +0530 Message-Id: <20220418205509.1102109-2-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220418205509.1102109-1-bhupesh.sharma@linaro.org> References: <20220418205509.1102109-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org '#clock-cells' is not a required property for qmp-phy(s) in the '/' node, but it should be is used in 'phy@' subnode (where it is actually a 'required' property). Fix the same. This also fixes the following 'make dtbs_check' warning(s): sm8350-microsoft-surface-duo2.dt.yaml: phy@1d87000: '#clock-cells' is a required property Cc: Bjorn Andersson Cc: Vinod Koul Cc: Rob Herring Signed-off-by: Bhupesh Sharma --- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index 8b850c5ab116..c39ead81ecd7 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -66,9 +66,6 @@ properties: - description: Address and length of PHY's common serdes block. - description: Address and length of PHY's DP_COM control block. - "#clock-cells": - enum: [ 1, 2 ] - "#address-cells": enum: [ 1, 2 ] @@ -112,11 +109,13 @@ patternProperties: description: Each device node of QMP phy is required to have as many child nodes as the number of lanes the PHY has. + properties: + "#clock-cells": + enum: [ 0, 1, 2 ] required: - compatible - reg - - "#clock-cells" - "#address-cells" - "#size-cells" - ranges @@ -468,7 +467,6 @@ examples: usb_2_qmpphy: phy-wrapper@88eb000 { compatible = "qcom,sdm845-qmp-usb3-uni-phy"; reg = <0x088eb000 0x18c>; - #clock-cells = <1>; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x088eb000 0x2000>; From patchwork Mon Apr 18 20:55:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 563150 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01E13C433EF for ; Mon, 18 Apr 2022 20:55:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347871AbiDRU6T (ORCPT ); Mon, 18 Apr 2022 16:58:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38874 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347864AbiDRU6P (ORCPT ); Mon, 18 Apr 2022 16:58:15 -0400 Received: from mail-pg1-x530.google.com (mail-pg1-x530.google.com [IPv6:2607:f8b0:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD644237C3 for ; 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Mon, 18 Apr 2022 13:55:33 -0700 (PDT) Received: from localhost.localdomain ([223.233.64.97]) by smtp.gmail.com with ESMTPSA id q60-20020a17090a17c200b001cd567fecaesm13498859pja.26.2022.04.18.13.55.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Apr 2022 13:55:32 -0700 (PDT) From: Bhupesh Sharma To: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, agross@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, vkoul@kernel.org, bjorn.andersson@linaro.org, Rob Herring Subject: [PATCH v3 3/4] dt-bindings: phy: qcom,qmp: Describe phy@ subnode properly Date: Tue, 19 Apr 2022 02:25:08 +0530 Message-Id: <20220418205509.1102109-4-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220418205509.1102109-1-bhupesh.sharma@linaro.org> References: <20220418205509.1102109-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Currently the qcom,qmp-phy dt-binding doesn't describe the 'reg' and '#phy-cells' properties for the phy@ subnode. Fix the same. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma --- .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index 411c79dbfa15..c553c8ad0d1a 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -118,6 +118,19 @@ patternProperties: Each device node of QMP phy is required to have as many child nodes as the number of lanes the PHY has. properties: + reg: + minItems: 1 + maxItems: 6 + items: + description: | + List of offset and length pairs of register sets for PHY blocks. + common block control registers, such as - SW_RESET, START_CTRL. + pcs registers, such as - PCS_STATUS, POWER_DOWN_CONTROL, + pcs misc registers, such as - PCS_MISC_TYPEC_CTRL. + + "#phy-cells": + const: 0 + "#clock-cells": enum: [ 0, 1, 2 ]