From patchwork Mon Apr 11 09:50:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 559759 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5AB61C4321E for ; Mon, 11 Apr 2022 09:52:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344821AbiDKJyd (ORCPT ); Mon, 11 Apr 2022 05:54:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345009AbiDKJxM (ORCPT ); Mon, 11 Apr 2022 05:53:12 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3406B41639; Mon, 11 Apr 2022 02:50:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649670649; x=1681206649; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=+xbfqnRznVX2Jfz5mYMD6PsZmXfJrHkCWmv6tLKMjMg=; b=TnoCjulOL4A/06iw1LWqy6JgFJQQwopxJ0wvmP0mWhWMPlpjCdARqZ7k hclVvl/DgBlGjodIZav893/77Znwq8DrBtH/H6kEEVE+9d2YynnzmrE0y 61w/JuP6kONeLEcsCA1SVE+iRoJHwwL4NJTdsTBA41nK9QEntG9vuPZwR s=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 11 Apr 2022 02:50:49 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/AES256-SHA; 11 Apr 2022 02:50:47 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 11 Apr 2022 15:20:24 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id C4C0D3AA3; Mon, 11 Apr 2022 15:20:23 +0530 (+0530) From: Rohit Agarwal To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, robh+dt@kernel.org, krzk+dt@kernel.org, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: manivannan.sadhasivam@linaro.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, Rohit Agarwal Subject: [PATCH v2 1/7] ARM: dts: qcom: sdx65: Add reserved memory nodes Date: Mon, 11 Apr 2022 15:20:09 +0530 Message-Id: <1649670615-21268-2-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649670615-21268-1-git-send-email-quic_rohiagar@quicinc.com> References: <1649670615-21268-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add reserved memory nodes to the SDX65 dtsi as defined by the memory map. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 21 +++++++++++++++++ arch/arm/boot/dts/qcom-sdx65.dtsi | 45 ++++++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index ad99f56..79dc31a 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -23,6 +23,27 @@ stdout-path = "serial0:115200n8"; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mpss_dsm: memory@8c400000 { + no-map; + reg = <0x8c400000 0x3200000>; + }; + + ipa_fw_mem: memory@8fced000 { + no-map; + reg = <0x8fced000 0x10000>; + }; + + mpss_adsp_mem: memory@90800000 { + no-map; + reg = <0x90800000 0x10000000>; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 7e2697f..dcc94c2 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -61,11 +61,56 @@ #size-cells = <1>; ranges; + tz_heap_mem: memory@8fcad000 { + no-map; + reg = <0x8fcad000 0x40000>; + }; + + secdata_mem: memory@8fcfd000 { + no-map; + reg = <0x8fcfd000 0x1000>; + }; + + hyp_mem: memory@8fd00000 { + no-map; + reg = <0x8fd00000 0x80000>; + }; + + access_control_mem: memory@8fd80000 { + no-map; + reg = <0x8fd80000 0x80000>; + }; + + aop_mem: memory@8fe00000 { + no-map; + reg = <0x8fe00000 0x20000>; + }; + + smem_mem: memory@8fe20000 { + no-map; + reg = <0x8fe20000 0xc0000>; + }; + cmd_db: reserved-memory@8fee0000 { compatible = "qcom,cmd-db"; reg = <0x8fee0000 0x20000>; no-map; }; + + tz_mem: memory@8ff00000 { + no-map; + reg = <0x8ff00000 0x100000>; + }; + + tz_apps_mem: memory@90000000 { + no-map; + reg = <0x90000000 0x500000>; + }; + + llcc_tcm_mem: memory@15800000 { + no-map; + reg = <0x15800000 0x800000>; + }; }; soc: soc { From patchwork Mon Apr 11 09:50:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 559761 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8914FC4321E for ; Mon, 11 Apr 2022 09:51:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344662AbiDKJyD (ORCPT ); Mon, 11 Apr 2022 05:54:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38578 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345020AbiDKJxM (ORCPT ); Mon, 11 Apr 2022 05:53:12 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6195541992; Mon, 11 Apr 2022 02:50:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649670653; x=1681206653; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=4sArmmPqK1fpsAra+ctcw1Mg8/kPFO/JwQ40cELNy00=; b=jNY70JwcHlYuriIrgeCYlJM8++mvOKSW1mAOUzMOcGSlWpNG1KMo07ph xP+0IJmnZrHWnlGbAPC4SaBJaAsqS2f7Ttex2OMCjy9N+MDZd71iLw/hz TGZUPlbZhONPQi+GQYCCybXPAYxK7jc4m2eZKNhZOVDp0U1783nOOjW5t E=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 11 Apr 2022 02:50:53 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 11 Apr 2022 02:50:51 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 11 Apr 2022 15:20:25 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id CAC7D3AB8; Mon, 11 Apr 2022 15:20:24 +0530 (+0530) From: Rohit Agarwal To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, robh+dt@kernel.org, krzk+dt@kernel.org, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: manivannan.sadhasivam@linaro.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, Rohit Agarwal Subject: [PATCH v2 4/7] dt-bindings: arm-smmu: Add binding for SDX65 SMMU Date: Mon, 11 Apr 2022 15:20:12 +0530 Message-Id: <1649670615-21268-5-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649670615-21268-1-git-send-email-quic_rohiagar@quicinc.com> References: <1649670615-21268-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add devicetree binding for Qualcomm SDX65 SMMU. Signed-off-by: Rohit Agarwal --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index da5381c..1f99bff 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -39,6 +39,7 @@ properties: - qcom,sc8180x-smmu-500 - qcom,sdm845-smmu-500 - qcom,sdx55-smmu-500 + - qcom,sdx65-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 From patchwork Mon Apr 11 09:50:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 559760 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10D30C433FE for ; Mon, 11 Apr 2022 09:51:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344757AbiDKJyH (ORCPT ); Mon, 11 Apr 2022 05:54:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345016AbiDKJxM (ORCPT ); Mon, 11 Apr 2022 05:53:12 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD4C94198E; Mon, 11 Apr 2022 02:50:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649670652; x=1681206652; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=i/ljBsm2MD9nNiXlMhM5SAGKdRLtBR+dGXw5lsuABgE=; b=w3U0bygSIeN40QIFOXYESB0GQx5A6VhfrdFu+0bLD0oAKgULgH0XnyKR ysH6avxAbjaBZ9L/bcOtub1Sbqc8ZWuwhpKtSnVstvcWKewyfeZOD8HJV /4MpLq2VGU6izE2W7JnMmwm+Kzy6j73WILD01seUMbvJh+X9Y6i8Jw2Xh g=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 11 Apr 2022 02:50:51 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 11 Apr 2022 02:50:49 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg02-blr.qualcomm.com with ESMTP; 11 Apr 2022 15:20:27 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 82DCC3A9B; Mon, 11 Apr 2022 15:20:26 +0530 (+0530) From: Rohit Agarwal To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, robh+dt@kernel.org, krzk+dt@kernel.org, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: manivannan.sadhasivam@linaro.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, Rohit Agarwal Subject: [PATCH v2 6/7] ARM: dts: qcom: sdx65: Add support for TCSR Mutex Date: Mon, 11 Apr 2022 15:20:14 +0530 Message-Id: <1649670615-21268-7-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649670615-21268-1-git-send-email-quic_rohiagar@quicinc.com> References: <1649670615-21268-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add TCSR Mutex node to support Qualcomm Hardware Mutex block on SDX65 platform. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index f50a8a4..210e55c 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -137,6 +137,12 @@ status = "disabled"; }; + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01f40000 0x40000>; + #hwlock-cells = <1>; + }; + sdhc_1: sdhci@8804000 { compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; reg = <0x08804000 0x1000>;