From patchwork Mon Apr 11 06:55:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 559657 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F80AC4332F for ; Mon, 11 Apr 2022 06:56:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245156AbiDKG6f (ORCPT ); Mon, 11 Apr 2022 02:58:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245130AbiDKG6b (ORCPT ); Mon, 11 Apr 2022 02:58:31 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 841172AE10; Sun, 10 Apr 2022 23:56:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649660177; x=1681196177; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=mjQU6c8wuWG8/rxJT2YYtKSSiAfz4IOR5/Ce9q0IxPc=; b=KgZ2utrO6Nx2Sls8ZZdCkVAgqVM3FpYC/i/Oqq+++n3yoxhB/jConIbs Mn+6KoWrxPGD+cVp2jP+tbIHwbltXUSAa1EteIDUbK9oRDU9ZAGTta0i0 3zNDKClibYnACDe1M9DtrxkbV3ZVdQlnoujIuhuOAxUHz/068bNcGfHzH A=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 10 Apr 2022 23:56:17 -0700 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 10 Apr 2022 23:56:15 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg01-blr.qualcomm.com with ESMTP; 11 Apr 2022 12:25:52 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id B12483AA0; Mon, 11 Apr 2022 12:25:51 +0530 (+0530) From: Rohit Agarwal To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, robh+dt@kernel.org, krzk+dt@kernel.org, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, Rohit Agarwal Subject: [PATCH 2/7] dt-bindings: mmc: sdhci-msm: Document the SDX65 compatible Date: Mon, 11 Apr 2022 12:25:38 +0530 Message-Id: <1649660143-22400-3-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com> References: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The SDHCI controller on SDX65 is based on MSM SDHCI v5 IP. Hence, document the compatible with "qcom,sdhci-msm-v5" as the fallback. Signed-off-by: Rohit Agarwal --- Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt index 6a8cc26..e1023e8 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt @@ -24,6 +24,7 @@ Required properties: "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5" "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; + "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5" NOTE that some old device tree files may be floating around that only have the string "qcom,sdhci-msm-v4" without the SoC compatible string From patchwork Mon Apr 11 06:55:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 559659 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3EF7C433FE for ; Mon, 11 Apr 2022 06:56:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241169AbiDKG6Z (ORCPT ); Mon, 11 Apr 2022 02:58:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236475AbiDKG6Z (ORCPT ); Mon, 11 Apr 2022 02:58:25 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 929CA2A25E; Sun, 10 Apr 2022 23:56:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649660171; x=1681196171; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=SPn7rGfpCdKX5BixSOyXy7nTS1C2Ef91VXqrhvWkrS4=; b=bifZ/ONFdc8+Kw/P+M4RC3weZByYW/1FoZLoLTgYYM3wHcwkh1GifZ9f K2j3H7MpXuj4Nbdod6LoU6WXyVyz2TxCZ+ytkbmY5igwM/8eqpMBaGJr0 N2r2ZumcnvznHOzPalae9XhQeB/KEoHJ7incWdSVWNiBRDZaBzNKmGI29 o=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 10 Apr 2022 23:56:11 -0700 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 10 Apr 2022 23:56:09 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg01-blr.qualcomm.com with ESMTP; 11 Apr 2022 12:25:54 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 4B7773A9B; Mon, 11 Apr 2022 12:25:53 +0530 (+0530) From: Rohit Agarwal To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, robh+dt@kernel.org, krzk+dt@kernel.org, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, Rohit Agarwal Subject: [PATCH 5/7] ARM: dts: qcom: sdx65: Enable ARM SMMU Date: Mon, 11 Apr 2022 12:25:41 +0530 Message-Id: <1649660143-22400-6-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com> References: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a node for the ARM SMMU found in the SDX65. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65.dtsi | 40 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 632ac78..2481769 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -181,6 +181,46 @@ status = "disabled"; }; + apps_smmu: iommu@15000000 { + compatible = "qcom,sdx65-smmu-500", "arm,mmu-500"; + reg = <0x15000000 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + pdc: interrupt-controller@b210000 { compatible = "qcom,sdx65-pdc", "qcom,pdc"; reg = <0xb210000 0x10000>; From patchwork Mon Apr 11 06:55:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 559658 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D81AEC433EF for ; Mon, 11 Apr 2022 06:56:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245136AbiDKG6b (ORCPT ); Mon, 11 Apr 2022 02:58:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37442 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245122AbiDKG62 (ORCPT ); Mon, 11 Apr 2022 02:58:28 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 571E02AC5E; Sun, 10 Apr 2022 23:56:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649660175; x=1681196175; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=aN1KTb9hnCejWsZRGrTW4ZKJH2xj1O2qH1Fk8k6TrPM=; b=tsDaj+T5zwaIP7y7YGtIja/Ph339sB1jWuYRLwMKCgvFpcbVcOZGr+Lp L39BJhBRCL/3Z3xMq47GcuYX/45ytEsAUZklVWapO1kPy/dPWxgbqRLkB NGt5lJnZWSfKXbdRj/QEJ/PkGEgMcufwxqDk3hiiXNsdNXi7mG5uA7Jtt s=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 10 Apr 2022 23:56:15 -0700 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 10 Apr 2022 23:56:13 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg01-blr.qualcomm.com with ESMTP; 11 Apr 2022 12:25:55 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 3E1BF37D9; Mon, 11 Apr 2022 12:25:54 +0530 (+0530) From: Rohit Agarwal To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, robh+dt@kernel.org, krzk+dt@kernel.org, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, Rohit Agarwal Subject: [PATCH 6/7] ARM: dts: qcom: sdx65: Add support for TCSR Mutex Date: Mon, 11 Apr 2022 12:25:42 +0530 Message-Id: <1649660143-22400-7-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com> References: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add TCSR Mutex node to support Qualcomm Hardware Mutex block on SDX65 platform. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 2481769..5c28c94 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -168,6 +168,12 @@ #interrupt-cells = <2>; }; + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x01f40000 0x40000>; + #hwlock-cells = <1>; + }; + sdhc_1: sdhci@8804000 { compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; reg = <0x08804000 0x1000>; From patchwork Mon Apr 11 06:55:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 559656 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17D12C43217 for ; Mon, 11 Apr 2022 06:56:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245151AbiDKG6l (ORCPT ); Mon, 11 Apr 2022 02:58:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37550 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245133AbiDKG6c (ORCPT ); Mon, 11 Apr 2022 02:58:32 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0CA322AE11; Sun, 10 Apr 2022 23:56:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1649660178; x=1681196178; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=nQG1bLVYjKXaO4pl95NzaFxrNoh/8TEGG6qEbyOTkeU=; b=UZ2188xMzVQ3L418NYl8rzAIf9jPqfRFsq6IVNTwNZj3t/g6J0o3oUR7 kJCLyrJPuOGDP2T5hBq11+/M56mhWUhnYkGjJ1feCS9M7Yxii4Z6tSivN wm50G1GdIR0miqdf6R38ALnaldw2aiA/WvvHlZFpwvnTLulBA/Z/sj8vP o=; Received: from ironmsg09-lv.qualcomm.com ([10.47.202.153]) by alexa-out.qualcomm.com with ESMTP; 10 Apr 2022 23:56:17 -0700 X-QCInternal: smtphost Received: from ironmsg01-blr.qualcomm.com ([10.86.208.130]) by ironmsg09-lv.qualcomm.com with ESMTP/TLS/AES256-SHA; 10 Apr 2022 23:56:16 -0700 X-QCInternal: smtphost Received: from hu-rohiagar-hyd.qualcomm.com (HELO hu-sgudaval-hyd.qualcomm.com) ([10.213.106.138]) by ironmsg01-blr.qualcomm.com with ESMTP; 11 Apr 2022 12:25:55 +0530 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id DCADE3A9B; Mon, 11 Apr 2022 12:25:54 +0530 (+0530) From: Rohit Agarwal To: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, robh+dt@kernel.org, krzk+dt@kernel.org, ulf.hansson@linaro.org, agross@kernel.org, bjorn.andersson@linaro.org Cc: linux-arm-kernel@lists.infradead.org, iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org, Rohit Agarwal Subject: [PATCH 7/7] ARM: dts: qcom: sdx65: Add Shared memory manager support Date: Mon, 11 Apr 2022 12:25:43 +0530 Message-Id: <1649660143-22400-8-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com> References: <1649660143-22400-1-git-send-email-quic_rohiagar@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add smem node to support shared memory manager on SDX65 platform. Signed-off-by: Rohit Agarwal --- arch/arm/boot/dts/qcom-sdx65.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 5c28c94..b0eec91 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -174,6 +174,12 @@ #hwlock-cells = <1>; }; + smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + sdhc_1: sdhci@8804000 { compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; reg = <0x08804000 0x1000>;