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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id l18-20020a056a00141200b004f75395b2cesm30481862pfu.150.2022.04.09.22.57.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Apr 2022 22:57:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 1/7] target/arm: Enable FEAT_CSV2 for -cpu max Date: Sat, 9 Apr 2022 22:57:19 -0700 Message-Id: <20220410055725.380246-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220410055725.380246-1-richard.henderson@linaro.org> References: <20220410055725.380246-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This extension concerns branch speculation, which TCG does not implement. Thus we can trivially enable this feature. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index def0f1fdcb..c1006a067c 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -805,6 +805,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ + t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */ cpu->isar.id_aa64pfr0 = t; t = cpu->isar.id_aa64pfr1; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 5cce9116d0..2750cbebec 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -71,6 +71,7 @@ void arm32_max_features(ARMCPU *cpu) cpu->isar.id_mmfr4 = t; t = cpu->isar.id_pfr0; + t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */ t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ cpu->isar.id_pfr0 = t; From patchwork Sun Apr 10 05:57:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 559486 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp1586111map; Sat, 9 Apr 2022 23:03:51 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxNbl8lNpawcDFf3HbCgJkJphO5SYZiY4B4iaLVLzdqOP1zp57KjATGrsjmb/i9SugmvXk9 X-Received: by 2002:a05:6214:4119:b0:441:9eb:d4ba with SMTP id kc25-20020a056214411900b0044109ebd4bamr22488978qvb.54.1649570631787; Sat, 09 Apr 2022 23:03:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649570631; cv=none; d=google.com; s=arc-20160816; b=rL5fqyG9PFx9uBllcNgANAO2j3NXJXt8GdvxLjjWcs4fZVQRrnN+Z6AitK1ciQa6Br h0iyrFOJhWHgS6cGWPfYwW4uibMDUr8/kLRKpSoPoV1Y45Ds/mhxjA+8+ZJxaXrAKpHX xw6H/5xauMXBv5gkD0BTgYRLBXJQyokXqaqMSTDT6PjbtU9BL9I2M6YepI/MXgawbIyU /PsRx5Wo2BELpz7Iz2LxzP0yZNLBOnjKe7o0U5BAeg5jedb1gBm3dMTOM10nu8akjWlh rQ7Bd1lZvcPitzBsU66oo0ckYNYR7nMoGjsNc9sO+qz7VJATs4/8FyQ7Z/H+Ah+Lra50 Wevg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=hRUTijrX/dWDGgF7d1LOxJ77lZwiKODTAAz7SOC7SIQ=; b=0zCglWm9/+NFCcukW9Im6CExureEj8zsQi6y7QSeZvFLmg0RYxMm5oKuO3Lmpe+lVP bb6V5YFq9IXaYtE1t+5LQTMaRUGImlV9t++DpF+K2IwmgiRiL3Y/YIBt68vB0eMHiD23 7QgMYj8B9gG29r+I1Bgsrr/0zXRcYJ1DImHIr47DYMQsVN7nyVEaeN77K2Ar26tc5Zi+ guG14KBZCWUehsL2LNSmtD6+iNKdYb5EaQptmpzu4Rkf626U5XlS8F67HJD3TU6LgOol I/PZNk4etUcoqir0vlo6IsS6siQ5WqXoBEllj4Bnx4UXNiY+ut8qbJuas/SpZ4OqByhk 8iPw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bnU455ss; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id l18-20020a056a00141200b004f75395b2cesm30481862pfu.150.2022.04.09.22.57.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Apr 2022 22:57:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 2/7] target/arm: Update ISAR fields for ARMv8.8 Date: Sat, 9 Apr 2022 22:57:20 -0700 Message-Id: <20220410055725.380246-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220410055725.380246-1-richard.henderson@linaro.org> References: <20220410055725.380246-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Update isar fields per ARM DDI0487 H.a. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index eb8cb738b5..c6c6d89a69 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1941,6 +1941,7 @@ FIELD(ID_MMFR4, CCIDX, 24, 4) FIELD(ID_MMFR4, EVT, 28, 4) FIELD(ID_MMFR5, ETS, 0, 4) +FIELD(ID_MMFR5, NTLBPA, 4, 4) FIELD(ID_PFR0, STATE0, 0, 4) FIELD(ID_PFR0, STATE1, 4, 4) @@ -1993,6 +1994,16 @@ FIELD(ID_AA64ISAR1, SPECRES, 40, 4) FIELD(ID_AA64ISAR1, BF16, 44, 4) FIELD(ID_AA64ISAR1, DGH, 48, 4) FIELD(ID_AA64ISAR1, I8MM, 52, 4) +FIELD(ID_AA64ISAR1, XS, 56, 4) +FIELD(ID_AA64ISAR1, LS64, 60, 4) + +FIELD(ID_AA64ISAR2, WFXT, 0, 4) +FIELD(ID_AA64ISAR2, RPRES, 4, 4) +FIELD(ID_AA64ISAR2, GPA3, 8, 4) +FIELD(ID_AA64ISAR2, APA3, 12, 4) +FIELD(ID_AA64ISAR2, MOPS, 16, 4) +FIELD(ID_AA64ISAR2, BC, 20, 4) +FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) FIELD(ID_AA64PFR0, EL0, 0, 4) FIELD(ID_AA64PFR0, EL1, 4, 4) @@ -2015,6 +2026,10 @@ FIELD(ID_AA64PFR1, SSBS, 4, 4) FIELD(ID_AA64PFR1, MTE, 8, 4) FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) +FIELD(ID_AA64PFR1, SME, 24, 4) +FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) +FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) +FIELD(ID_AA64PFR1, NMI, 36, 4) FIELD(ID_AA64MMFR0, PARANGE, 0, 4) FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) @@ -2041,6 +2056,11 @@ FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) FIELD(ID_AA64MMFR1, XNX, 28, 4) FIELD(ID_AA64MMFR1, TWED, 32, 4) FIELD(ID_AA64MMFR1, ETS, 36, 4) +FIELD(ID_AA64MMFR1, HCX, 40, 4) +FIELD(ID_AA64MMFR1, AFP, 44, 4) +FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) +FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) +FIELD(ID_AA64MMFR1, CMOW, 56, 4) FIELD(ID_AA64MMFR2, CNP, 0, 4) FIELD(ID_AA64MMFR2, UAO, 4, 4) @@ -2067,7 +2087,9 @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) FIELD(ID_AA64DFR0, PMSVER, 32, 4) FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) +FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) FIELD(ID_AA64DFR0, MTPMU, 48, 4) +FIELD(ID_AA64DFR0, BRBE, 52, 4) FIELD(ID_AA64ZFR0, SVEVER, 0, 4) FIELD(ID_AA64ZFR0, AES, 4, 4) @@ -2089,6 +2111,7 @@ FIELD(ID_DFR0, PERFMON, 24, 4) FIELD(ID_DFR0, TRACEFILT, 28, 4) FIELD(ID_DFR1, MTPMU, 0, 4) +FIELD(ID_DFR1, HPMN0, 4, 4) FIELD(DBGDIDR, SE_IMP, 12, 1) FIELD(DBGDIDR, NSUHD_IMP, 14, 1) From patchwork Sun Apr 10 05:57:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 559485 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp1584193map; Sat, 9 Apr 2022 23:00:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxPs7zBUnntcBJ8oQ1+q6rKp9aDrjF3+OSdp2vAf0wDHvidaghQEY5u/sNKYL5zCn8ldsj9 X-Received: by 2002:a05:620a:15f9:b0:69b:e5e6:6011 with SMTP id p25-20020a05620a15f900b0069be5e66011mr6243903qkm.305.1649570404305; Sat, 09 Apr 2022 23:00:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649570404; cv=none; d=google.com; s=arc-20160816; b=b63qkGxbX3F0NnGNRFjRTI4qoDIRXyC9UvPAUtXKW8egkliuoz85ZqB0RZhWsNkw70 vIzc6Y4XNQPtIbSWKTStrFYeeYuYsaMwIpALvIq+fp52AdIEkGwiSbcPEBAbNjMOOTw5 jMrMlX9JxyNRZPAOVyat9b5ivQpD8eNEC9ksAW9e06CmLC2+lpn56hhLcn7KMQ5I4/jM wWVptPoi0bSoBBVo7ISjoGV3EyrXLz3W3uWAwjNDrBcSKk41XpIMbW+cirb+S+rUYV5V EQ1foJEJ4ZW7VvcMCZ+mpcUSGNmSGRG7cBjnlx0W93cWxKgcAKaUXSAzTucnmVP0hDTi G/iQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NpS74LDHWG/S/DkrcIyrDZyCFuZ6BFbDpFALEvPQLBw=; b=nNcHqTuXIYoo09q+ZIyTA4KcbXVuaIQWx7V8CHNQc7pU3eJqxGUKXtkN4+wVtpwB5v v/yqW9VISLglqF4M4OscvQholAbImyLcGUwzDK0FmY4QGjBdBi4+Jr64z9seetL1VU4p BIi1Ltex54d0GhxLIm6x0E4SuD3pmXfeOF1fpMho/5F5EcY4h11DT2P/5rhCCs2rTl6E qV7ToM64df/iRzsAhVf44VkhCpZiOcuNL//xVhKbASG2nPj1C0VaI7rQs+mvn55RM7sZ 09QBje5ok1DRfma6IahGmZ14UVC+QobDKecGRh+kgUqPcJkuCPYbP+RstnHoi3+a9CZG G4mA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="pbpP/sv3"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id l18-20020a056a00141200b004f75395b2cesm30481862pfu.150.2022.04.09.22.57.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Apr 2022 22:57:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 3/7] target/arm: Enable FEAT_CSV2_2 for -cpu max Date: Sat, 9 Apr 2022 22:57:21 -0700 Message-Id: <20220410055725.380246-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220410055725.380246-1-richard.henderson@linaro.org> References: <20220410055725.380246-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There is no branch prediction in TCG, therefore there is no need to actually include the context number into the predictor. Therefore all we need to do is add the state for SCXTNUM_ELx. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 16 +++++++++++ target/arm/cpu64.c | 2 +- target/arm/helper.c | 70 ++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 86 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c6c6d89a69..0b89620662 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -688,6 +688,8 @@ typedef struct CPUArchState { ARMPACKey apdb; ARMPACKey apga; } keys; + + uint64_t scxtnum_el[4]; #endif #if defined(CONFIG_USER_ONLY) @@ -1211,6 +1213,7 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_WXN (1U << 19) #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ +#define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ @@ -4368,6 +4371,19 @@ static inline bool isar_feature_aa64_dit(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0; } +static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) +{ + int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); + if (key >= 2) { + return true; /* FEAT_CSV2_2 */ + } + if (key == 1) { + key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); + return key >= 2; /* FEAT_CSV2_1p2 */ + } + return false; +} + static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c1006a067c..9ff08bd995 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -805,7 +805,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ - t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */ + t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ cpu->isar.id_aa64pfr0 = t; t = cpu->isar.id_aa64pfr1; diff --git a/target/arm/helper.c b/target/arm/helper.c index bd1c8e01cb..66af3397ee 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1780,6 +1780,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_mte, cpu)) { valid_mask |= SCR_ATA; } + if (cpu_isar_feature(aa64_scxtnum, cpu)) { + valid_mask |= SCR_ENSCXT; + } } else { valid_mask &= ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { @@ -5312,6 +5315,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_mask) if (cpu_isar_feature(aa64_mte, cpu)) { valid_mask |= HCR_ATA | HCR_DCT | HCR_TID5; } + if (cpu_isar_feature(aa64_scxtnum, cpu)) { + valid_mask |= HCR_ENSCXT; + } } /* Clear RES0 bits. */ @@ -5965,6 +5971,10 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, + { K(3, 0, 0xd, 0, 7), K(3, 4, 0xd, 0, 7), K(3, 5, 0xd, 0, 7), + "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12", + isar_feature_aa64_scxtnum }, + /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ }; @@ -7434,7 +7444,61 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = { REGINFO_SENTINEL }; -#endif +static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + uint64_t hcr; + + switch (arm_current_el(env)) { + case 0: + hcr = arm_hcr_el2_eff(env); + if ((hcr & (HCR_TGE | HCR_E2H)) != (HCR_TGE | HCR_E2H)) { + if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) { + if (hcr & HCR_TGE) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_TRAP; + } + if (arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) { + return CP_ACCESS_TRAP_EL2; + } + } else { + QEMU_FALLTHROUGH; + case 1: + if (env->cp15.sctlr_el[2] & SCTLR_TSCXT) { + return CP_ACCESS_TRAP_EL2; + } + } + QEMU_FALLTHROUGH; + case 2: + if (arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_ENSCXT)) { + return CP_ACCESS_TRAP_EL3; + } + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo scxtnum_reginfo[] = { + { .name = "SCXTNUM_EL0", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .crn = 0xd, .crm = 0, .opc2 = 7, + .access = PL0_RW, .accessfn = access_scxtnum, + .fieldoffset = offsetof(CPUARMState, scxtnum_el[0]) }, + { .name = "SCXTNUM_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 0xd, .crm = 0, .opc2 = 7, + .access = PL1_RW, .accessfn = access_scxtnum, + .fieldoffset = offsetof(CPUARMState, scxtnum_el[1]) }, + { .name = "SCXTNUM_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 0xd, .crm = 0, .opc2 = 7, + .access = PL2_RW, .accessfn = access_scxtnum, + .fieldoffset = offsetof(CPUARMState, scxtnum_el[2]) }, + { .name = "SCXTNUM_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 0xd, .crm = 0, .opc2 = 7, + .access = PL3_RW, + .fieldoffset = offsetof(CPUARMState, scxtnum_el[3]) }, + REGINFO_SENTINEL +}; +#endif /* TARGET_AARCH64 */ static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -8634,6 +8698,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, mte_tco_ro_reginfo); define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); } + + if (cpu_isar_feature(aa64_scxtnum, cpu)) { + define_arm_cp_regs(cpu, scxtnum_reginfo); + } #endif if (cpu_isar_feature(any_predinv, cpu)) { From patchwork Sun Apr 10 05:57:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 559488 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp1589283map; Sat, 9 Apr 2022 23:10:39 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzqGyVmLXk+jUfT11NJRC68js4o8bZTBIooYW0fM3yYGj1mevBqBzNjQUyqeqtMA4g+uXWc X-Received: by 2002:a05:6214:dcf:b0:444:408e:24d5 with SMTP id 15-20020a0562140dcf00b00444408e24d5mr502829qvt.22.1649571038999; Sat, 09 Apr 2022 23:10:38 -0700 (PDT) ARC-Seal: i=1; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id l18-20020a056a00141200b004f75395b2cesm30481862pfu.150.2022.04.09.22.57.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Apr 2022 22:57:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 4/7] target/arm: Enable FEAT_CSV3 for -cpu max Date: Sat, 9 Apr 2022 22:57:22 -0700 Message-Id: <20220410055725.380246-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220410055725.380246-1-richard.henderson@linaro.org> References: <20220410055725.380246-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This extension concerns cache speculation, which TCG does not implement. Thus we can trivially enable this feature. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 9ff08bd995..a0429538cc 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -806,6 +806,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ + t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ cpu->isar.id_aa64pfr0 = t; t = cpu->isar.id_aa64pfr1; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 2750cbebec..31ea5a90e0 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -77,6 +77,7 @@ void arm32_max_features(ARMCPU *cpu) cpu->isar.id_pfr0 = t; t = cpu->isar.id_pfr2; + t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ cpu->isar.id_pfr2 = t; From patchwork Sun Apr 10 05:57:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 559487 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp1586681map; Sat, 9 Apr 2022 23:04:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzuGD8k9uxf0J+4fgO+0nONl2ct30gEPdmDE1Vrd4YvR+++K86ziivZG+k7HYKI9bMOEcE5 X-Received: by 2002:a05:620a:240e:b0:69c:a35:6640 with SMTP id d14-20020a05620a240e00b0069c0a356640mr2305763qkn.217.1649570692747; Sat, 09 Apr 2022 23:04:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649570692; cv=none; d=google.com; s=arc-20160816; b=A6iF7Vz1OGmHO6DEZ2tdD7mCPsxdogEhOhbr6VJ9xuqZbWcBuR4klwxPIrTIYy/wMJ OhkytX7wutKR2+dYOggGCLFOJuVnffksDW63LvcX1mApyvJZjiNlfll9FZuF/K6IpT0/ nUpP+6b2YflpFCv3J3TUZ32Flg1hDqunsiuldTyc6sIZrcQz8OhIal3vzMJ0mRi+hxtC /OzxP9pRnbRXDCNDgJzHgX3Dehs6nfCmcoCRhQzQgwZQO/y659SeWOeK7EF37lAESXP5 VMXwOBXz1El4Agsfs/FeZdyxsBYw6DAWJU0ttD9/0yjTZSwNKGk/ZdJ4rMfKFYsZyV8d POpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=rAFoHiqfdDsz3JpAFNFs8ScJcRhTKGmndskIyyVL2JU=; b=wFirvYWjXMX98f6ITqYm/Lny8cQkH7FAs2p/PHg14WUAqj22dPJ6JpPjVF/OgGfvvZ yJp4ROi2QBfbgoAOEKKVNoX4z8OHIFBWoZp93rOyB3bDv9zrMI6XAJT8oK+1KD12j+Tf jcY2ovZX1jo+IIdm6rhoJk1AhPS+Oix+0xfrvWPVjLExN0op9lruXv5IeePl2xQYnZp8 vhG6IgG1v6uAsDROPQftaB1OxizpWTmWyHkUMJc0zpaMaGNoFdwJdbx1vJAUQwI/hztV A7UiuEQ00azS6XopsnS+ANSJBrH86QjJ8zFVCQErPlj0fud8ps4vNe0HFERoUVEgHzPo sCZg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lf8zMwjJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id l18-20020a056a00141200b004f75395b2cesm30481862pfu.150.2022.04.09.22.57.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Apr 2022 22:57:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 5/7] target/arm: Enable FEAT_DGH for -cpu max Date: Sat, 9 Apr 2022 22:57:23 -0700 Message-Id: <20220410055725.380246-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220410055725.380246-1-richard.henderson@linaro.org> References: <20220410055725.380246-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This extension concerns not merging memory access, which TCG does not implement. Thus we can trivially enable this feature. Add a comment to handle_hint for the DGH instruction, but no code. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu64.c | 1 + target/arm/translate-a64.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index a0429538cc..199ca437a0 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -795,6 +795,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ + t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ cpu->isar.id_aa64isar1 = t; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index cc54dff83c..c3c1a19dea 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1442,6 +1442,7 @@ static void handle_hint(DisasContext *s, uint32_t insn, break; case 0b00100: /* SEV */ case 0b00101: /* SEVL */ + case 0b00110: /* DGH */ /* we treat all as NOP at least for now */ break; case 0b00111: /* XPACLRI */ From patchwork Sun Apr 10 05:57:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 559489 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp1589396map; Sat, 9 Apr 2022 23:10:52 -0700 (PDT) X-Google-Smtp-Source: ABdhPJx4Z/6XbvGL2rRFVMfadhZySBvZs6lDMqPi1jhSgzhTO7GERbOsfqRKympdMZb5M1UCgHxg X-Received: by 2002:a0c:8d4c:0:b0:443:a990:4eb7 with SMTP id s12-20020a0c8d4c000000b00443a9904eb7mr22288401qvb.85.1649571052638; Sat, 09 Apr 2022 23:10:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1649571052; cv=none; d=google.com; s=arc-20160816; b=hJrnXUf3CzWnAHttkmSCS4W93jtD0bQvIi13ihxYx9STestebIGOGHVnPZICcH0Thf Hp0g3QSu0xNm/VdHUtrOo0X3y4ldCsOCRY+qSSK5ZjVcWCWO7PiMbjwUj7dpG2y70Htt 0QDgG6syG3WGO4qUyEC7B5uoEyjkJ9cjMZSMjB39zoeOC/XTFVjo+L7mHkQe8+pWjZPm gafLAbCnTsl7OQ6Gtcq4FhWgIi1lnq5+6mclvLOKRDjs1azBZubmIyyVc3m1ppAJu7B7 RYXeTHu+M96QOU1SQ8gKRi7fLWL9nlm+L5KnOh79mjImcwUPG+xNtPDgiExx7dM6Zx6H X3lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=5QswmRLp0zJBHFk1pYr5Ngu+gpbMPNOeIbq7m9P+NBQ=; b=Z3JcP8z9cMoJxL7Xj6GiYSOCLKfIZKsCkLlgeGTi+bjoN72Qr0QG8nr9BEQPFJZHy5 P2+bSedm1u1J2klQS/Tc36FAzV/fQzIiBhx+iEYvulLqc8aTCFM7JuIAdjf0sChf0ecX XByx0v/5H4ZO9uFWLkhpZoyoqNcfgzYw6sCKy542gUkdN8w77pbE3mHH5KwXXQ8QRv13 QumxhLU2ege+Bbh0wyU1pEXEv/3kotiX3LJS2ZEfe6Yp3cWgiYEjeBZoKJgisVfZp547 OhHv8TqyjNAvzAuxgQfB0ajTap3hoOT7wKv09VK4G4RsNutaLY7RwkHuNp1PxGwW0eo8 88bg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YN2ysF2a; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id l18-20020a056a00141200b004f75395b2cesm30481862pfu.150.2022.04.09.22.57.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Apr 2022 22:57:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 6/7] target/arm: Define cortex-a76 Date: Sat, 9 Apr 2022 22:57:24 -0700 Message-Id: <20220410055725.380246-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220410055725.380246-1-richard.henderson@linaro.org> References: <20220410055725.380246-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Enable the a76 for virt and sbsa board use. Signed-off-by: Richard Henderson --- hw/arm/sbsa-ref.c | 1 + hw/arm/virt.c | 1 + target/arm/cpu64.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 66 insertions(+) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 2387401963..2ddde88f5e 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -145,6 +145,7 @@ static const int sbsa_ref_irqmap[] = { static const char * const valid_cpus[] = { ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), + ARM_CPU_TYPE_NAME("cortex-a76"), ARM_CPU_TYPE_NAME("max"), }; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d2e5ecd234..ce15c36a7f 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -202,6 +202,7 @@ static const char *valid_cpus[] = { ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), + ARM_CPU_TYPE_NAME("cortex-a76"), ARM_CPU_TYPE_NAME("a64fx"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 199ca437a0..a00c02be2c 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -251,6 +251,69 @@ static void aarch64_a72_initfn(Object *obj) define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); } +static void aarch64_a76_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,cortex-a76"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by B2.4 AArch64 registers by functional group */ + cpu->clidr = 0x82000023; + cpu->ctr = 0x8444C004; + cpu->dcz_blocksize = 4; + cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; + cpu->isar.id_aa64isar0 = 0x0000100010211120ull; + cpu->isar.id_aa64isar1 = 0x0000000000100001ull; + cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; + cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; + cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; + cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; + cpu->isar.id_dfr0 = 0x04010088; + cpu->isar.id_isar0 = 0x02101110; + cpu->isar.id_isar1 = 0x13112111; + cpu->isar.id_isar2 = 0x21232042; + cpu->isar.id_isar3 = 0x01112131; + cpu->isar.id_isar4 = 0x00010142; + cpu->isar.id_isar5 = 0x01011121; + cpu->isar.id_isar6 = 0x00000010; + cpu->isar.id_mmfr0 = 0x10201105; + cpu->isar.id_mmfr1 = 0x40000000; + cpu->isar.id_mmfr2 = 0x01260000; + cpu->isar.id_mmfr3 = 0x02122211; + cpu->isar.id_mmfr4 = 0x00021110; + cpu->isar.id_pfr0 = 0x10010131; + cpu->isar.id_pfr1 = 0x10010000; + cpu->isar.id_pfr2 = 0x00000011; + cpu->midr = 0x413fd0b1; + + /* From B2.18 CCSIDR_EL1 */ + cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ + cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ + cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */ + + /* From B2.93 SCTLR_EL3 */ + cpu->reset_sctlr = 0x30c50838; + + /* From B4.23 ICH_VTR_EL2 */ + cpu->gic_num_lrs = 4; + cpu->gic_vpribits = 5; + cpu->gic_vprebits = 5; + + /* From B5.1 AdvSIMD AArch64 register summary */ + cpu->isar.mvfr0 = 0x10110222; + cpu->isar.mvfr1 = 0x13211111; + cpu->isar.mvfr2 = 0x00000043; +} + void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { /* @@ -935,6 +998,7 @@ static const ARMCPUInfo aarch64_cpus[] = { { .name = "cortex-a57", .initfn = aarch64_a57_initfn }, { .name = "cortex-a53", .initfn = aarch64_a53_initfn }, { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, + { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, { .name = "max", .initfn = aarch64_max_initfn }, #if defined(CONFIG_KVM) || defined(CONFIG_HVF) From patchwork Sun Apr 10 05:57:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 559490 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:6886:0:0:0:0 with SMTP id m6csp1591917map; Sat, 9 Apr 2022 23:17:33 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzBq73no5xedZZW4jIhWHytuQsiHC6WW4qSYktc0+Bn9cLwnvzA3PgL60vWlv3gwWb8xdeE X-Received: by 2002:a05:622a:15ce:b0:2eb:9a95:a422 with SMTP id d14-20020a05622a15ce00b002eb9a95a422mr21652348qty.582.1649571453770; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id l18-20020a056a00141200b004f75395b2cesm30481862pfu.150.2022.04.09.22.57.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 09 Apr 2022 22:57:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 7/7] target/arm: Define neoverse-n1 Date: Sat, 9 Apr 2022 22:57:25 -0700 Message-Id: <20220410055725.380246-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220410055725.380246-1-richard.henderson@linaro.org> References: <20220410055725.380246-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Enable the n1 for virt and sbsa board use. Signed-off-by: Richard Henderson --- hw/arm/sbsa-ref.c | 1 + hw/arm/virt.c | 1 + target/arm/cpu64.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 66 insertions(+) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 2ddde88f5e..dac8860f2d 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -146,6 +146,7 @@ static const char * const valid_cpus[] = { ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("cortex-a76"), + ARM_CPU_TYPE_NAME("neoverse-n1"), ARM_CPU_TYPE_NAME("max"), }; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ce15c36a7f..82dd934de6 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -204,6 +204,7 @@ static const char *valid_cpus[] = { ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("cortex-a76"), ARM_CPU_TYPE_NAME("a64fx"), + ARM_CPU_TYPE_NAME("neoverse-n1"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), }; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index a00c02be2c..6a67b3d840 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -314,6 +314,69 @@ static void aarch64_a76_initfn(Object *obj) cpu->isar.mvfr2 = 0x00000043; } +static void aarch64_neoverse_n1_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,neoverse-n1"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by B2.4 AArch64 registers by functional group */ + cpu->clidr = 0x82000023; + cpu->ctr = 0x8444c004; + cpu->dcz_blocksize = 4; + cpu->isar.id_aa64dfr0 = 0x0000000110305408ull; + cpu->isar.id_aa64isar0 = 0x0000100010211120ull; + cpu->isar.id_aa64isar1 = 0x0000000000100001ull; + cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull; + cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; + cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; + cpu->isar.id_aa64pfr1 = 0x0000000000000020ull; + cpu->isar.id_dfr0 = 0x04010088; + cpu->isar.id_isar0 = 0x02101110; + cpu->isar.id_isar1 = 0x13112111; + cpu->isar.id_isar2 = 0x21232042; + cpu->isar.id_isar3 = 0x01112131; + cpu->isar.id_isar4 = 0x00010142; + cpu->isar.id_isar5 = 0x01011121; + cpu->isar.id_isar6 = 0x00000010; + cpu->isar.id_mmfr0 = 0x10201105; + cpu->isar.id_mmfr1 = 0x40000000; + cpu->isar.id_mmfr2 = 0x01260000; + cpu->isar.id_mmfr3 = 0x02122211; + cpu->isar.id_mmfr4 = 0x00021110; + cpu->isar.id_pfr0 = 0x10010131; + cpu->isar.id_pfr1 = 0x10010000; + cpu->isar.id_pfr2 = 0x00000011; + cpu->midr = 0x414fd0c1; + + /* From B2.23 CCSIDR_EL1 */ + cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ + cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ + cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */ + + /* From B2.98 SCTLR_EL3 */ + cpu->reset_sctlr = 0x30c50838; + + /* From B4.23 ICH_VTR_EL2 */ + cpu->gic_num_lrs = 4; + cpu->gic_vpribits = 5; + cpu->gic_vprebits = 5; + + /* From B5.1 AdvSIMD AArch64 register summary */ + cpu->isar.mvfr0 = 0x10110222; + cpu->isar.mvfr1 = 0x12111111; + cpu->isar.mvfr2 = 0x00000043; +} + void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { /* @@ -1000,6 +1063,7 @@ static const ARMCPUInfo aarch64_cpus[] = { { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, + { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn }, { .name = "max", .initfn = aarch64_max_initfn }, #if defined(CONFIG_KVM) || defined(CONFIG_HVF) { .name = "host", .initfn = aarch64_host_initfn },