From patchwork Tue Dec 11 19:12:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 153502 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp984187ljp; Tue, 11 Dec 2018 11:12:17 -0800 (PST) X-Google-Smtp-Source: AFSGD/V6fuTht5fuVBgaBGeoyjiJ84YBvH/2TjwMZ1kvEnWmWvJg53NOVkewDp6FElPJ9qka2ydN X-Received: by 2002:a63:e84c:: with SMTP id a12mr15501934pgk.241.1544555537562; Tue, 11 Dec 2018 11:12:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544555537; cv=none; d=google.com; s=arc-20160816; b=eBJ6DK/90GyUfJNtqP5w3d/3teQccq9n0WUwPBQXG3TcX8s9Jantk9RfksR4w6TepN 6F8wLGa8ZkT/q2cCuDzU/ll/gpIjhUusaaX9iA1dIzJbvOlhN1ii4IXVUYRo9x+uvSHJ bqpppERl8tU0ksc0MII1RErS+IDQ/jGOHmQObXPTFlVb9VwSvgTBmNuN2jLERGrpWMwK 78s0PwwYGNR6m70wd/5iOHZCrH4lenkkH/8eE0drYyOhlblQA+XWQlWbi/216oTv4Uau tqqjlLZcZIOujWpjrFHYx9Do7VwGn6/fNj6dg8VnLBW64KMP5O+eCFlr5OvR8SaEKnP8 4Otg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:dkim-signature; bh=g1Gu1tvMv1Y9EMPNKEnhoJEhOF9s2cZZX0dAjPhIBK4=; b=Dd0l+oi4u0OuRTGS1OwEDblZPJz/QZii0Gx0w4TOhVhM/qeZqOacdvmrg9Jd04qujj xb1RgYCpzAXJlUd5PdF0GfdS0d/NxVAKzP8zxPr53+567tDaroH1EDMVdD5gnhfEqjIW o16G8k7+4JxEoaX88SX4fewu4jal5tcJA8a7CF3sRZ2fWCga99PSzs3XoQXt93qn8E11 8CDlRAoQTQ+rgeViOtRNCfPgY3GmwebC9Q/Xd42d4aAOH40Qmy+IUy6aZHhgEkF/Iwki Gi8TGavxWBF6zGet5GO5a2E4enT4MdQGlDRE58quMDV0NBNGK7MwScZomTgRSm4evEq+ JshA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=shzvbxIn; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ca19si13815234plb.238.2018.12.11.11.12.17; Tue, 11 Dec 2018 11:12:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=shzvbxIn; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726919AbeLKTMP (ORCPT + 31 others); Tue, 11 Dec 2018 14:12:15 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:44397 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726340AbeLKTMO (ORCPT ); Tue, 11 Dec 2018 14:12:14 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id wBBJCDTf069973; Tue, 11 Dec 2018 13:12:13 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1544555533; bh=g1Gu1tvMv1Y9EMPNKEnhoJEhOF9s2cZZX0dAjPhIBK4=; h=From:To:CC:Subject:Date; b=shzvbxIn9zf1+v7iCuyQYx6Fc87jJB+m1OoklhHfC/kxIHPQgcmc8c70K/6z0QBHk JZYkSzdn7wGRc8xu9YahLYf/7Bju/NoSDqHxxaK7hHLqH2d51LITrHACYSfsOGCJJr BCY3NDfEWi+z4SDZwJqoXpnL8Cq8XnIqMhnIEg7I= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wBBJCCSx127630 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 11 Dec 2018 13:12:13 -0600 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Tue, 11 Dec 2018 13:12:12 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Tue, 11 Dec 2018 13:12:12 -0600 Received: from legion.dal.desgin.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wBBJCCNl008718; Tue, 11 Dec 2018 13:12:12 -0600 Received: from localhost (a0272616local-lt.dhcp.ti.com [172.22.100.89]) by legion.dal.desgin.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id wBBJCCU05298; Tue, 11 Dec 2018 13:12:12 -0600 (CST) From: Dan Murphy To: CC: , , , Dan Murphy Subject: [PATCH v2 1/4] iio: ti-ads124s08: Add DT binding documentation Date: Tue, 11 Dec 2018 13:12:04 -0600 Message-ID: <20181211191207.21900-1-dmurphy@ti.com> X-Mailer: git-send-email 2.12.2 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Adding binding documentation for Texas Instruments ADS124S08 and ADS124S06 ADC. S08 is a 12 channel ADC S06 is a 6 channel ADC Datesheet can be found here: http://www.ti.com/lit/gpn/ads124s08 Signed-off-by: Dan Murphy --- v2 - Fixed incorrect compatible example and removed vref-supply - https://lore.kernel.org/patchwork/patch/1021047/ .../bindings/iio/adc/ti-ads124s08.txt | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/ti-ads124s08.txt -- 2.20.0.rc2.7.g965798d1f2 diff --git a/Documentation/devicetree/bindings/iio/adc/ti-ads124s08.txt b/Documentation/devicetree/bindings/iio/adc/ti-ads124s08.txt new file mode 100644 index 000000000000..6993e76e61c6 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/ti-ads124s08.txt @@ -0,0 +1,23 @@ +* Texas Instruments' ads124s08 and ads124s06 ADC chip + +Required properties: + - compatible: Should be "ti,ads124s08" or "ti,ads124s06" + - reg: spi chip select number for the device + +Recommended properties: + - spi-max-frequency: Definition as per + Documentation/devicetree/bindings/spi/spi-bus.txt + - spi-cpha: Definition as per + Documentation/devicetree/bindings/spi/spi-bus.txt + +Optional properties: + - reset-gpios: GPIO pin used to reset the device. + +Example: +adc@0 { + compatible = "ti,ads124s08"; + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpha; + reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; +}; From patchwork Tue Dec 11 19:12:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 153503 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp984231ljp; Tue, 11 Dec 2018 11:12:19 -0800 (PST) X-Google-Smtp-Source: AFSGD/XH4GcJ5+bFZ3qhXHbw73U2Wb5YJP85ZGVMraWK/uNCsTG2cxJdyM5LeUmH1sI/H/75onrS X-Received: by 2002:a62:178f:: with SMTP id 137mr17238854pfx.226.1544555539376; Tue, 11 Dec 2018 11:12:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544555539; cv=none; d=google.com; s=arc-20160816; b=kCBD3G8R2OxO4jxXaZjwLOdAwcf5nzXBol7CIvNoU0abfAhJEwyYKwcJl2Qc92aNU0 xCwgwTRCM52Vrn/8as/fs35C+dIX90MH4sa58NZzsbDwbs/xNqqk1sqcJxnxqbVPzYnx F4DRg9ErDNNEO5LMAPAoYCqXadW475hwd5pYQMVTM3VMBi6N1upXKHynxj4EY7yAB6ls E36x7Do/WZuUncu1p48CTgcDEWJX6VbUxQoBC2hB8sw4GbyJL3R+XnTTRBJkhu1cgJ7I mM1hVnMjmLIcVmYgltcqXJcwDTEnN5VFOffreW4cYxrN8k4FdpT6Vb6MIuyBJlhpZ6tK i70w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=FCzf8oz9sjscJgUMjt/870u0gx1NZzmkgy01Qyb485E=; b=pIAd8kqLOhTw0pEI3cdQ1qWA5DCcLgleQ0dC/oBH8thlk7ZYmtvZaRJfNSDBs607vD WPK+U5NCf+DFYScf6PmEUx59fZvU2ofHwMW6O3oyhG+/9Li0Mub/o01NwWmwhGHa8na2 DBZyzbhQ3Y1GiATwTCk4UjgOcpGILsxd4iNnCrEb5cMz51BHJZTWHR7+dz4E5En3Xamy Kq2bi0SzFqD9EufIUR8xueI2yHfXxOsDPwTSzBT4rK9i+8/0j8Ui6Xi/t8UM7KGHPOY1 w9vx6TY9GMs7iAh8AX7CKsJhZ5UxOadl5Kt33JaE3grrao/1Pxet7COltgNorrerTTAy qDhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=D+1Y3xv2; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ca19si13815234plb.238.2018.12.11.11.12.19; Tue, 11 Dec 2018 11:12:19 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=D+1Y3xv2; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726959AbeLKTMS (ORCPT + 31 others); Tue, 11 Dec 2018 14:12:18 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:44396 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726402AbeLKTMP (ORCPT ); Tue, 11 Dec 2018 14:12:15 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id wBBJCDGk069979; Tue, 11 Dec 2018 13:12:13 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1544555533; bh=FCzf8oz9sjscJgUMjt/870u0gx1NZzmkgy01Qyb485E=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=D+1Y3xv2pRtEinQZBShddSrP8rAwz9yjH04qFl/P740tpL7Qb+52VZNKmGZN+YeP0 /KWgectL4U8K+PGAHjwk5FfcWZ4DQaJ9KXyGlrFeyfgr25reOWX2S6eSy1B3MYmIiN 3bcT3D+FhtxdHuF741N4F8hlN1TJWA2b9MLopbyU= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wBBJCDVZ010251 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 11 Dec 2018 13:12:13 -0600 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Tue, 11 Dec 2018 13:12:12 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Tue, 11 Dec 2018 13:12:13 -0600 Received: from legion.dal.desgin.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id wBBJCCZq029047; Tue, 11 Dec 2018 13:12:12 -0600 Received: from localhost (a0272616local-lt.dhcp.ti.com [172.22.100.89]) by legion.dal.desgin.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id wBBJCCU05307; Tue, 11 Dec 2018 13:12:12 -0600 (CST) From: Dan Murphy To: CC: , , , Dan Murphy Subject: [PATCH v2 2/4] iio: adc: Add the TI ads124s08 ADC code Date: Tue, 11 Dec 2018 13:12:05 -0600 Message-ID: <20181211191207.21900-2-dmurphy@ti.com> X-Mailer: git-send-email 2.12.2 In-Reply-To: <20181211191207.21900-1-dmurphy@ti.com> References: <20181211191207.21900-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Introduce the TI ADS124S08 and the ADS124S06 ADC devices from TI. The ADS124S08 is the 12 channel ADC and the ADS124S06 is the 6 channel ADC device These devices share a common datasheet: http://www.ti.com/lit/gpn/ads124s08 Signed-off-by: Dan Murphy --- v2 - Removed the fill_noop call, updated probe to use device managed calls, removed regulator support, fixed the buffer to allow 64 bit timestamp, changed all the defines from S0X to S08, added an enum for the IDs and updated copyright header format. I may have missed a few summary changes here but here is the review reference - https://lore.kernel.org/patchwork/patch/1021048/ drivers/iio/adc/Kconfig | 10 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/ti-ads124s08.c | 375 +++++++++++++++++++++++++++++++++ 3 files changed, 386 insertions(+) create mode 100644 drivers/iio/adc/ti-ads124s08.c -- 2.20.0.rc2.7.g965798d1f2 diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index a52fea8749a9..e8c5686e6716 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -887,6 +887,16 @@ config TI_ADS8688 This driver can also be built as a module. If so, the module will be called ti-ads8688. +config TI_ADS124S08 + tristate "Texas Instruments ADS124S08" + depends on SPI && OF + help + If you say yes here you get support for Texas Instruments ADS124S08 + and ADS124S06 ADC chips + + This driver can also be built as a module. If so, the module will be + called ti-ads124s08. + config TI_AM335X_ADC tristate "TI's AM335X ADC driver" depends on MFD_TI_AM335X_TSCADC && HAS_DMA diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index a6e6a0b659e2..d70293abfdba 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -79,6 +79,7 @@ obj-$(CONFIG_TI_ADC161S626) += ti-adc161s626.o obj-$(CONFIG_TI_ADS1015) += ti-ads1015.o obj-$(CONFIG_TI_ADS7950) += ti-ads7950.o obj-$(CONFIG_TI_ADS8688) += ti-ads8688.o +obj-$(CONFIG_TI_ADS124S08) += ti-ads124s08.o obj-$(CONFIG_TI_AM335X_ADC) += ti_am335x_adc.o obj-$(CONFIG_TI_TLC4541) += ti-tlc4541.o obj-$(CONFIG_TWL4030_MADC) += twl4030-madc.o diff --git a/drivers/iio/adc/ti-ads124s08.c b/drivers/iio/adc/ti-ads124s08.c new file mode 100644 index 000000000000..328dfe330088 --- /dev/null +++ b/drivers/iio/adc/ti-ads124s08.c @@ -0,0 +1,375 @@ +// SPDX-License-Identifier: GPL-2.0 +/* TI ADS124S0X chip family driver + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include + +/* Commands */ +#define ADS124S08_CMD_NOP 0x00 +#define ADS124S08_CMD_WAKEUP 0x02 +#define ADS124S08_CMD_PWRDWN 0x04 +#define ADS124S08_CMD_RESET 0x06 +#define ADS124S08_CMD_START 0x08 +#define ADS124S08_CMD_STOP 0x0a +#define ADS124S08_CMD_SYOCAL 0x16 +#define ADS124S08_CMD_SYGCAL 0x17 +#define ADS124S08_CMD_SFOCAL 0x19 +#define ADS124S08_CMD_RDATA 0x12 +#define ADS124S08_CMD_RREG 0x20 +#define ADS124S08_CMD_WREG 0x40 + +/* Registers */ +#define ADS124S08_ID_REG 0x00 +#define ADS124S08_STATUS 0x01 +#define ADS124S08_INPUT_MUX 0x02 +#define ADS124S08_PGA 0x03 +#define ADS124S08_DATA_RATE 0x04 +#define ADS124S08_REF 0x05 +#define ADS124S08_IDACMAG 0x06 +#define ADS124S08_IDACMUX 0x07 +#define ADS124S08_VBIAS 0x08 +#define ADS124S08_SYS 0x09 +#define ADS124S08_OFCAL0 0x0a +#define ADS124S08_OFCAL1 0x0b +#define ADS124S08_OFCAL2 0x0c +#define ADS124S08_FSCAL0 0x0d +#define ADS124S08_FSCAL1 0x0e +#define ADS124S08_FSCAL2 0x0f +#define ADS124S08_GPIODAT 0x10 +#define ADS124S08_GPIOCON 0x11 + +/* ADS124S0x common channels */ +#define ADS124S08_AIN0 0x00 +#define ADS124S08_AIN1 0x01 +#define ADS124S08_AIN2 0x02 +#define ADS124S08_AIN3 0x03 +#define ADS124S08_AIN4 0x04 +#define ADS124S08_AIN5 0x05 +#define ADS124S08_AINCOM 0x0c +/* ADS124S08 only channels */ +#define ADS124S08_AIN6 0x06 +#define ADS124S08_AIN7 0x07 +#define ADS124S08_AIN8 0x08 +#define ADS124S08_AIN9 0x09 +#define ADS124S08_AIN10 0x0a +#define ADS124S08_AIN11 0x0b +#define ADS124S08_MAX_CHANNELS 12 + +#define ADS124S08_POS_MUX_SHIFT 0x04 +#define ADS124S08_INT_REF 0x09 + +#define ADS124S08_START_REG_MASK 0x1f +#define ADS124S08_NUM_BYTES_MASK 0x1f + +#define ADS124S08_START_CONV 0x01 +#define ADS124S08_STOP_CONV 0x00 + +enum ads124s_id { + ADS124S08_ID, + ADS124S06_ID, +}; + +struct ads124s_chip_info { + const struct iio_chan_spec *channels; + unsigned int num_channels; +}; + +struct ads124s_private { + const struct ads124s_chip_info *chip_info; + struct gpio_desc *reset_gpio; + struct spi_device *spi; + struct mutex lock; + u8 data[ADS124S08_MAX_CHANNELS] ____cacheline_aligned; +}; + +#define ADS124S08_CHAN(index) \ +{ \ + .type = IIO_VOLTAGE, \ + .indexed = 1, \ + .channel = index, \ + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ + .scan_index = index, \ + .scan_type = { \ + .sign = 'u', \ + .realbits = 24, \ + .storagebits = 24, \ + .endianness = IIO_BE, \ + }, \ +} + +static const struct iio_chan_spec ads124s06_channels[] = { + ADS124S08_CHAN(0), + ADS124S08_CHAN(1), + ADS124S08_CHAN(2), + ADS124S08_CHAN(3), + ADS124S08_CHAN(4), + ADS124S08_CHAN(5), +}; + +static const struct iio_chan_spec ads124s08_channels[] = { + ADS124S08_CHAN(0), + ADS124S08_CHAN(1), + ADS124S08_CHAN(2), + ADS124S08_CHAN(3), + ADS124S08_CHAN(4), + ADS124S08_CHAN(5), + ADS124S08_CHAN(6), + ADS124S08_CHAN(7), + ADS124S08_CHAN(8), + ADS124S08_CHAN(9), + ADS124S08_CHAN(10), + ADS124S08_CHAN(11), +}; + +static const struct ads124s_chip_info ads124s_chip_info_tbl[] = { + [ADS124S08_ID] = { + .channels = ads124s08_channels, + .num_channels = ARRAY_SIZE(ads124s08_channels), + }, + [ADS124S06_ID] = { + .channels = ads124s06_channels, + .num_channels = ARRAY_SIZE(ads124s06_channels), + }, +}; + +static int ads124s_write_cmd(struct iio_dev *indio_dev, u8 command) +{ + struct ads124s_private *priv = iio_priv(indio_dev); + + priv->data[0] = command; + + return spi_write(priv->spi, &priv->data[0], 1); +} + +static int ads124s_write_reg(struct iio_dev *indio_dev, u8 reg, u8 data) +{ + struct ads124s_private *priv = iio_priv(indio_dev); + + priv->data[0] = ADS124S08_CMD_WREG | reg; + priv->data[1] = 0x0; + priv->data[2] = data; + + return spi_write(priv->spi, &priv->data[0], 3); +} + +static int ads124s_reset(struct iio_dev *indio_dev) +{ + struct ads124s_private *priv = iio_priv(indio_dev); + + if (priv->reset_gpio) { + gpiod_set_value(priv->reset_gpio, 0); + udelay(200); + gpiod_set_value(priv->reset_gpio, 1); + } else { + return ads124s_write_cmd(indio_dev, ADS124S08_CMD_RESET); + } + + return 0; +}; + +static int ads124s_read(struct iio_dev *indio_dev, unsigned int chan) +{ + struct ads124s_private *priv = iio_priv(indio_dev); + int ret; + u32 tmp; + struct spi_transfer t[] = { + { + .tx_buf = &priv->data[0], + .len = 4, + .cs_change = 1, + }, { + .tx_buf = &priv->data[1], + .rx_buf = &priv->data[1], + .len = 4, + }, + }; + + priv->data[0] = ADS124S08_CMD_RDATA; + memset(&priv->data[1], ADS124S08_CMD_NOP, sizeof(priv->data)); + + ret = spi_sync_transfer(priv->spi, t, ARRAY_SIZE(t)); + if (ret < 0) + return ret; + + tmp = priv->data[2] << 16 | priv->data[3] << 8 | priv->data[4]; + + return tmp; +} + +static int ads124s_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long m) +{ + struct ads124s_private *priv = iio_priv(indio_dev); + int ret; + + mutex_lock(&priv->lock); + switch (m) { + case IIO_CHAN_INFO_RAW: + ret = ads124s_write_reg(indio_dev, ADS124S08_INPUT_MUX, + chan->channel); + if (ret) { + dev_err(&priv->spi->dev, "Set ADC CH failed\n"); + goto out; + } + + ret = ads124s_write_cmd(indio_dev, ADS124S08_START_CONV); + if (ret) { + dev_err(&priv->spi->dev, "Start ADC converions failed\n"); + goto out; + } + + ret = ads124s_read(indio_dev, chan->channel); + if (ret < 0) { + dev_err(&priv->spi->dev, "Read ADC failed\n"); + goto out; + } else + *val = ret; + + ret = ads124s_write_cmd(indio_dev, ADS124S08_STOP_CONV); + if (ret) { + dev_err(&priv->spi->dev, "Stop ADC converions failed\n"); + goto out; + } + + ret = IIO_VAL_INT; + break; + default: + ret = -EINVAL; + break; + } +out: + mutex_unlock(&priv->lock); + return ret; +} + +static const struct iio_info ads124s_info = { + .read_raw = &ads124s_read_raw, +}; + +static irqreturn_t ads124s_trigger_handler(int irq, void *p) +{ + struct iio_poll_func *pf = p; + struct iio_dev *indio_dev = pf->indio_dev; + struct ads124s_private *priv = iio_priv(indio_dev); + unsigned short buffer[ADS124S08_MAX_CHANNELS + sizeof(s64)/sizeof(short)]; + int scan_index, j = 0; + int ret; + + for_each_set_bit(scan_index, indio_dev->active_scan_mask, + indio_dev->masklength) { + ret = ads124s_write_reg(indio_dev, ADS124S08_INPUT_MUX, + scan_index); + if (ret) + dev_err(&priv->spi->dev, "Set ADC CH failed\n"); + + ret = ads124s_write_cmd(indio_dev, ADS124S08_START_CONV); + if (ret) + dev_err(&priv->spi->dev, "Start ADC converions failed\n"); + + buffer[j] = ads124s_read(indio_dev, scan_index); + ret = ads124s_write_cmd(indio_dev, ADS124S08_STOP_CONV); + if (ret) + dev_err(&priv->spi->dev, "Stop ADC converions failed\n"); + + j++; + } + + iio_push_to_buffers_with_timestamp(indio_dev, buffer, + pf->timestamp); + + iio_trigger_notify_done(indio_dev->trig); + + return IRQ_HANDLED; +} + +static int ads124s_probe(struct spi_device *spi) +{ + struct ads124s_private *ads124s_priv; + struct iio_dev *indio_dev; + int ret; + + indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*ads124s_priv)); + if (indio_dev == NULL) + return -ENOMEM; + + ads124s_priv = iio_priv(indio_dev); + + ads124s_priv->reset_gpio = devm_gpiod_get_optional(&spi->dev, + "reset", GPIOD_OUT_LOW); + if (IS_ERR(ads124s_priv->reset_gpio)) + dev_info(&spi->dev, "Reset GPIO not defined\n"); + + ads124s_priv->chip_info = &ads124s_chip_info_tbl[spi_get_device_id(spi)->driver_data]; + + spi_set_drvdata(spi, indio_dev); + + ads124s_priv->spi = spi; + + indio_dev->name = spi_get_device_id(spi)->name; + indio_dev->dev.parent = &spi->dev; + indio_dev->dev.of_node = spi->dev.of_node; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->channels = ads124s_priv->chip_info->channels; + indio_dev->num_channels = ads124s_priv->chip_info->num_channels; + indio_dev->info = &ads124s_info; + + mutex_init(&ads124s_priv->lock); + + ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL, + ads124s_trigger_handler, NULL); + if (ret) { + dev_err(&spi->dev, "iio triggered buffer setup failed\n"); + return ret; + } + + ads124s_reset(indio_dev); + + return devm_iio_device_register(&spi->dev, indio_dev); +} + +static const struct spi_device_id ads124s_id[] = { + { "ads124s06", ADS124S06_ID }, + { "ads124s08", ADS124S08_ID }, + { } +}; +MODULE_DEVICE_TABLE(spi, ads124s_id); + +static const struct of_device_id ads124s_of_table[] = { + { .compatible = "ti,ads124s06" }, + { .compatible = "ti,ads124s08" }, + { }, +}; +MODULE_DEVICE_TABLE(of, ads124s_of_table); + +static struct spi_driver ads124s_driver = { + .driver = { + .name = "ads124s08", + .of_match_table = ads124s_of_table, + }, + .probe = ads124s_probe, + .id_table = ads124s_id, +}; +module_spi_driver(ads124s_driver); + +MODULE_AUTHOR("Dan Murphy "); +MODULE_DESCRIPTION("TI TI_ADS12S0X ADC"); +MODULE_LICENSE("GPL v2"); From patchwork Tue Dec 11 19:12:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 153504 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp984317ljp; Tue, 11 Dec 2018 11:12:25 -0800 (PST) X-Google-Smtp-Source: AFSGD/VipLEihJGNY9dJbMBNS6OQaxVLYHpjPS5fo1qSe7AbArLWUP6LeKhE8bzL64dk3Vf/j3uo X-Received: by 2002:a63:9712:: with SMTP id n18mr15408344pge.295.1544555545172; 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[209.132.180.67]) by mx.google.com with ESMTP id 66si12970747plc.125.2018.12.11.11.12.24; Tue, 11 Dec 2018 11:12:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ktpdQXGi; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727027AbeLKTMX (ORCPT + 31 others); Tue, 11 Dec 2018 14:12:23 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:46420 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726340AbeLKTMQ (ORCPT ); Tue, 11 Dec 2018 14:12:16 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id wBBJCE6h068867; Tue, 11 Dec 2018 13:12:14 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1544555534; bh=4GmxVsEkvur/HocmJaaz385vAXn4ukjjWJj68nJCE5w=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ktpdQXGiZdtYYB32VJRL68g95GI7Yhsv7DIhK1ziGwlF2BVvlqMo1leXMxXEPoepq iLrKwXk/M4tSySC5Vez2kMKRfHpTxkiyhynBsXvusiCA4UmwxXR1qZ0/QpGdoh+6X3 RLrl58Z78Wh+3ihT50YDQjbayx6IfdY4SRGtAPUs= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wBBJCEtC010258 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 11 Dec 2018 13:12:14 -0600 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Tue, 11 Dec 2018 13:12:14 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Tue, 11 Dec 2018 13:12:14 -0600 Received: from legion.dal.desgin.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wBBJCEdu012041; Tue, 11 Dec 2018 13:12:14 -0600 Received: from localhost (a0272616local-lt.dhcp.ti.com [172.22.100.89]) by legion.dal.desgin.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id wBBJCDU05313; Tue, 11 Dec 2018 13:12:13 -0600 (CST) From: Dan Murphy To: CC: , , , Dan Murphy Subject: [PATCH v2 3/4] iio: ti-ads8688: Update buffer allocation for timestamps Date: Tue, 11 Dec 2018 13:12:06 -0600 Message-ID: <20181211191207.21900-3-dmurphy@ti.com> X-Mailer: git-send-email 2.12.2 In-Reply-To: <20181211191207.21900-1-dmurphy@ti.com> References: <20181211191207.21900-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Per Jonathan Cameron, the buffer needs to allocate room for a 64 bit timestamp as well as the channels. Change the buffer to allocate this additional space. Signed-off-by: Dan Murphy --- v2 - New patch suggested change by maintainer - https://lore.kernel.org/patchwork/patch/1021048/ drivers/iio/adc/ti-ads8688.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.20.0.rc2.7.g965798d1f2 diff --git a/drivers/iio/adc/ti-ads8688.c b/drivers/iio/adc/ti-ads8688.c index 184d686ebd99..3597bc0697ee 100644 --- a/drivers/iio/adc/ti-ads8688.c +++ b/drivers/iio/adc/ti-ads8688.c @@ -385,7 +385,7 @@ static irqreturn_t ads8688_trigger_handler(int irq, void *p) { struct iio_poll_func *pf = p; struct iio_dev *indio_dev = pf->indio_dev; - u16 buffer[8]; + unsigned short buffer[8 + sizeof(s64)/sizeof(short)]; int i, j = 0; for (i = 0; i < indio_dev->masklength; i++) { From patchwork Tue Dec 11 19:12:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 153505 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp984509ljp; Tue, 11 Dec 2018 11:12:35 -0800 (PST) X-Google-Smtp-Source: AFSGD/UL97yH5GszusnnnyWs33yYPZkRME50AwOsCmp7ZVih7pmSzb/mRw2t7Rr2PDEZgDIrTfQn X-Received: by 2002:a17:902:714c:: with SMTP id u12mr16906324plm.234.1544555555264; Tue, 11 Dec 2018 11:12:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544555555; cv=none; d=google.com; s=arc-20160816; b=vic5lV+oXwynMevKL/HFw2qljIz7ElNnrskIzEpnuDt2JrN6MTdtk7f1l6b0m4qs+6 kc78GKQOAC1OqtaLa1Cy9nKzY37Tn4fRi8qLELFeMOwHM0wOn5yiJPEo3e4MDhHZFvSz eT35+OfyfdoVOecySNelu6vHgUU2tPccB98KRsXEnjQBVEppCn5t/1tNRDqLaMPqkJBF PbmlbNVkVPvb9nfw9ZAXF+xlc07acj6LeOghorxTIB5ELFwHKzDanbriD6r0CEv3RVc0 wiazWuasX4AOufuoUeJwvWS3V2FpV9dhmYaX2DXgOSz9mEsrDHOVoJCpQaPBcf5RjZf7 907A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=ZMupGSZ0KfkZn40zfMtACkB5aYcH5RjAyq86kxZimtU=; b=W9hXGYJbt5akljdkHphVV1UA2bSaNebUxUVfad6zHTBBMc8DelE6TWt9LmmPDG8nDb JSoXFPWGEenXuYHBE7a7f29prKy/JQ6PHAjtPP9Xn/l23h+j8ejaKTJPUqP9PHSRK56e b+wWgXOtyWntaCwlZCnQOUtWlK+J5YQWkJ3lKWEEOtFF+4j46kWVI19pAcC2UA6Ix4WE 286nrJDvf4AEKBVAU3As9e4aklVs8G2rdVxRAlJn1pcM7tn0oGqFexZDDw8oyZK1pZ1J A59gIM9ii/S76fdqQOgR0Qu+MPt3yjMs8+7ufx33eAHiRh+ncud3j+8O4sgh92nNdXQ4 ZI+A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 31si13617994plz.263.2018.12.11.11.12.34; Tue, 11 Dec 2018 11:12:35 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726986AbeLKTMW (ORCPT + 31 others); Tue, 11 Dec 2018 14:12:22 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:57712 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726923AbeLKTMR (ORCPT ); Tue, 11 Dec 2018 14:12:17 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id wBBJCEjk114460; Tue, 11 Dec 2018 13:12:14 -0600 Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wBBJCEiZ101998 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 11 Dec 2018 13:12:14 -0600 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Tue, 11 Dec 2018 13:12:14 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Tue, 11 Dec 2018 13:12:14 -0600 Received: from legion.dal.desgin.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wBBJCEVl008735; Tue, 11 Dec 2018 13:12:14 -0600 Received: from localhost (a0272616local-lt.dhcp.ti.com [172.22.100.89]) by legion.dal.desgin.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id wBBJCEU05336; Tue, 11 Dec 2018 13:12:14 -0600 (CST) From: Dan Murphy To: CC: , , , Dan Murphy Subject: [PATCH v2 4/4] iio: ti-ads8688: Migrate to device managed IIO calls Date: Tue, 11 Dec 2018 13:12:07 -0600 Message-ID: <20181211191207.21900-4-dmurphy@ti.com> X-Mailer: git-send-email 2.12.2 In-Reply-To: <20181211191207.21900-1-dmurphy@ti.com> References: <20181211191207.21900-1-dmurphy@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Migrate the driver to use the devm IIO calls as opposed to the unmanaged calls. Signed-off-by: Dan Murphy --- v2 - New patch drivers/iio/adc/ti-ads8688.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) -- 2.20.0.rc2.7.g965798d1f2 diff --git a/drivers/iio/adc/ti-ads8688.c b/drivers/iio/adc/ti-ads8688.c index 3597bc0697ee..8f42103a1fd9 100644 --- a/drivers/iio/adc/ti-ads8688.c +++ b/drivers/iio/adc/ti-ads8688.c @@ -462,21 +462,21 @@ static int ads8688_probe(struct spi_device *spi) mutex_init(&st->lock); - ret = iio_triggered_buffer_setup(indio_dev, NULL, ads8688_trigger_handler, NULL); + ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL, + ads8688_trigger_handler, NULL); if (ret < 0) { dev_err(&spi->dev, "iio triggered buffer setup failed\n"); goto err_regulator_disable; } - ret = iio_device_register(indio_dev); - if (ret) - goto err_buffer_cleanup; + ret = devm_iio_device_register(&spi->dev, indio_dev); + if (ret < 0) { + dev_err(&spi->dev, "iio device registration failed\n"); + goto err_regulator_disable; + } return 0; -err_buffer_cleanup: - iio_triggered_buffer_cleanup(indio_dev); - err_regulator_disable: if (!IS_ERR(st->reg)) regulator_disable(st->reg); @@ -489,9 +489,6 @@ static int ads8688_remove(struct spi_device *spi) struct iio_dev *indio_dev = spi_get_drvdata(spi); struct ads8688_state *st = iio_priv(indio_dev); - iio_device_unregister(indio_dev); - iio_triggered_buffer_cleanup(indio_dev); - if (!IS_ERR(st->reg)) regulator_disable(st->reg);