From patchwork Tue Apr 5 09:28:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajish Koshy X-Patchwork-Id: 556445 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 738AFC4167B for ; Tue, 5 Apr 2022 11:04:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241173AbiDEK4I (ORCPT ); Tue, 5 Apr 2022 06:56:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345028AbiDEJmz (ORCPT ); Tue, 5 Apr 2022 05:42:55 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 04ACFBF959 for ; Tue, 5 Apr 2022 02:28:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649150901; x=1680686901; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MiDBtTI5DxAu1kXNuWEhbMRyLeEHOB8yGCKvaEoMnnI=; b=zAgyuRTSklxAZfLfy+e33j0hfqwPMjAFNW0FmYXeJbYKGZWFiDZ753WD SIadQB2qh0DuuA54rBIvUJ3qINikUL/jjz19WVdhw9zU0pKsYo1VymH3f zFyBwwUYQeHfsbSaEw9SvB3iWnSFtC4CT5D1s3by4cXJ9bwFi0Kl7PWio yX3zI8xEUcrK8aPuhk/WZEsi4SyNtW1pBbkUvQvce2sCkdsgJsA0wSFmF fHEicCOG+mBV6sJKUhbfGViSr0ddRKakCgInAQTX5p1tjGBRQVpPbeE3e 2/nBodoD8wi+mBDKK3CyvCgXPfHOE1lVIqhiwD8pcceUroKlY8iLCtyuB A==; X-IronPort-AV: E=Sophos;i="5.90,236,1643698800"; d="scan'208";a="154410412" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 05 Apr 2022 02:28:21 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 5 Apr 2022 02:28:21 -0700 Received: from localhost (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 5 Apr 2022 02:28:20 -0700 From: Ajish Koshy To: CC: , , , , Jinpu Wang Subject: [PATCH v2 1/2] scsi: pm80xx: mask and unmask upper interrupt vectors 32-63 Date: Tue, 5 Apr 2022 05:28:32 -0400 Message-ID: <20220405092833.83335-2-Ajish.Koshy@microchip.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220405092833.83335-1-Ajish.Koshy@microchip.com> References: <20220405092833.83335-1-Ajish.Koshy@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org When upper inbound and outbound queues 32-63 are enabled, we see upper vectors 32-63 in interrupt service routine. We need corresponding registers to handle masking and unmasking of these upper interrupts. To achieve this, we use registers MSGU_ODMR_U(0x34) to mask and MSGU_ODMR_CLR_U(0x3C) to unmask the interrupts. In these registers bit 0-31 represents interrupt vectors 32-63. Signed-off-by: Ajish Koshy Signed-off-by: Viswas G Fixes: 05c6c029a44d ("scsi: pm80xx: Increase number of supported queues") --- drivers/scsi/pm8001/pm80xx_hwi.c | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/drivers/scsi/pm8001/pm80xx_hwi.c b/drivers/scsi/pm8001/pm80xx_hwi.c index 9bb31f66db85..3e6413e21bfe 100644 --- a/drivers/scsi/pm8001/pm80xx_hwi.c +++ b/drivers/scsi/pm8001/pm80xx_hwi.c @@ -1728,9 +1728,17 @@ pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec) { #ifdef PM8001_USE_MSIX u32 mask; - mask = (u32)(1 << vec); - pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF)); + if (vec < 32) { + mask = 1U << vec; + /*vectors 0 - 31*/ + pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, mask); + } else { + vec = vec - 32; + mask = 1U << vec; + /*vectors 32 - 63*/ + pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U, mask); + } return; #endif pm80xx_chip_intx_interrupt_enable(pm8001_ha); @@ -1747,11 +1755,22 @@ pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec) { #ifdef PM8001_USE_MSIX u32 mask; - if (vec == 0xFF) + + if (vec == 0xFF) { mask = 0xFFFFFFFF; - else - mask = (u32)(1 << vec); - pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF)); + /* disable all vectors 0-31, 32-63*/ + pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, mask); + pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, mask); + } else if (vec < 32) { + mask = 1U << vec; + /*vectors 0 - 31*/ + pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, mask); + } else { + vec = vec - 32; + mask = 1U << vec; + /*vectors 32 - 63*/ + pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, mask); + } return; #endif pm80xx_chip_intx_interrupt_disable(pm8001_ha); From patchwork Tue Apr 5 09:28:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajish Koshy X-Patchwork-Id: 556447 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01599C433FE for ; Tue, 5 Apr 2022 10:53:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240915AbiDEKz1 (ORCPT ); Tue, 5 Apr 2022 06:55:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345030AbiDEJmz (ORCPT ); Tue, 5 Apr 2022 05:42:55 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B320ABF95F for ; Tue, 5 Apr 2022 02:28:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649150903; x=1680686903; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VD6j8Nu3A7lXR9Uk4FkaKFGK5kcgYsNGW5r9o3Wwkqs=; b=EYVcgFktxXKZ6pSijtWBF+vPWIxcF7o4hXrdJILiNpJvi1UZWzabHrTJ 2W2W1ViO87zrF8qw3LYZ6iahjOJ3BtlBl3iAXKBDTOTqhaK8ALkAPc2pS V+JO4dXnCCW0F0qFV4kyZRuy1X6UAdls8HHVUW9Kznq+FNN5EeZVHr4fK mp3OLVQznER2yo+h/MQWEMmcsQFSFMHXnVSDNhsi2uYS1a+fCAioeYEag vEuHvDrYrHsId2ANgPULFpy64eSzE8RJRNP/y8TkDjojItQpzgRq8PgDS wXw/ozy20zlFRGjTKK38t+pSEa3zTzrUSJmBZSMG8fmo/1CsiiFNOiBoa g==; X-IronPort-AV: E=Sophos;i="5.90,236,1643698800"; d="scan'208";a="159337353" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 05 Apr 2022 02:28:23 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 5 Apr 2022 02:28:22 -0700 Received: from localhost (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Tue, 5 Apr 2022 02:28:22 -0700 From: Ajish Koshy To: CC: , , , , Jinpu Wang Subject: [PATCH v2 2/2] scsi: pm80xx: enable upper inbound, outbound queues Date: Tue, 5 Apr 2022 05:28:33 -0400 Message-ID: <20220405092833.83335-3-Ajish.Koshy@microchip.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220405092833.83335-1-Ajish.Koshy@microchip.com> References: <20220405092833.83335-1-Ajish.Koshy@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-scsi@vger.kernel.org Executing driver on servers with more than 32 CPUs were faced with command timeouts. This is because we were not geting completions for commands submitted on IQ32 - IQ63. Set E64Q bit to enable upper inbound and outbound queues 32 to 63 in the MPI main configuration table. Added 500ms delay after successful MPI initialization as mentioned in controller datasheet. Signed-off-by: Ajish Koshy Signed-off-by: Viswas G Fixes: 05c6c029a44d ("scsi: pm80xx: Increase number of supported queues") Reviewed-by: Damien Le Moal --- drivers/scsi/pm8001/pm80xx_hwi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/scsi/pm8001/pm80xx_hwi.c b/drivers/scsi/pm8001/pm80xx_hwi.c index 3e6413e21bfe..c41c24a4b906 100644 --- a/drivers/scsi/pm8001/pm80xx_hwi.c +++ b/drivers/scsi/pm8001/pm80xx_hwi.c @@ -766,6 +766,10 @@ static void init_default_table_values(struct pm8001_hba_info *pm8001_ha) pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01; pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01; + /* Enable higher IQs and OQs, 32 to 63, bit 16*/ + if (pm8001_ha->max_q_num > 32) + pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |= + 1 << 16; /* Disable end to end CRC checking */ pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16); @@ -1027,6 +1031,8 @@ static int mpi_init_check(struct pm8001_hba_info *pm8001_ha) if (0x0000 != gst_len_mpistate) return -EBUSY; + msleep(500); + return 0; }