From patchwork Tue Apr 5 13:01:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Gupta X-Patchwork-Id: 558691 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB7D5C433F5 for ; Tue, 5 Apr 2022 14:45:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235500AbiDEOq5 (ORCPT ); Tue, 5 Apr 2022 10:46:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36618 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382116AbiDEORO (ORCPT ); Tue, 5 Apr 2022 10:17:14 -0400 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2042.outbound.protection.outlook.com [40.107.223.42]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 830A5160C17; Tue, 5 Apr 2022 06:01:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=i28ISAFOCCx0/+cUsremgSY/kxc8nCtOXYFm6X8bCJefiOpXVEuSPlVqvtFZQEamViFkyah67sfYhhLFiVeyx186T7fKrxn8yZ4c5y22vBNhkNpDmIJYWjFEaowUuDAQSJKbRYj856C3zl6OT89i2j7Sv6Q8udkIMXBAFf2oG79QoKQLuxkTQyfmvl6bH9jW1vAYOS0kfYQNQKJqpdNBzUvt6SxvYOkClL28Dypp+9kt6vS9esLPSVJrPFDielOnIlIESbtkSNU3y9vF8TVgqyAc+K8DRN2lNe8iB2UsE7QnPqqbrYwfBydcd7Wcwy21vB9sTKOdUHvqjs7PYri8EA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=h8i85DJwZtncqEQZ7TEeTjmCCy1RYwOdgyHXoXJi82s=; b=VG9oXDRQCBqK3LE9IC1xiFkuW9rXSQbj8iFd9jJmEzK8qVtaLe695PwLfA8z73VIJfQhKrALEZZRhmwSIVPCBew/Uvhu9XdT2V3XTfbRMSvuzTm6/gk9kOAapCT4YYP4j2TxG4t1PrBWgese4At9WUcYBKbrOVYJ31Ay9kvXdp2+CGM2pULd5yWz+xLjv/c/QVAIu7/sToRsofTQtno+ccmGqWFsOjHgLCMYxfPOkFOHSpA1886DtPhV2iMaOwQR84QiimWNBJq5DladsjmQzuIDB8DwjENqoQfZwNqmIF4yGus4duHMHe0YQZCnY2cU0utbkcpliIvy5aS0Bj2JTg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.236) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=h8i85DJwZtncqEQZ7TEeTjmCCy1RYwOdgyHXoXJi82s=; b=RE+g2f83Tb2ESmhK+Rs7D4bbXOpX2h2XtBh5rUtKYkmLaD8HCvtZoZ2NE9XJkJq9n8AC1CH3lK+sDsDMOiqDpU7BuILz4uZVyM6BaIth+++ZMxC/BEqATLJLT+rKrNjTR5QBd/iGK/r4SuEV94oFGxyy02Btp6b+Di5UC8aFP6elWnWMtcqqbIf1P5gZxXAd4BSMAPWodIwdOIKFNhSTLIVjv/9vq1Mqj73tGc/On/Ab3HA+c/smZ/X4+b8Cf24/nst07Lhe/YlcDdXvQHpK+E4HTsRGpwpduqlJ8PFD6PJoeNdSQA3PBK7weErhsMeHAqjLjsNguruasbPHo+NtWA== Received: from BN0PR04CA0081.namprd04.prod.outlook.com (2603:10b6:408:ea::26) by DM6PR12MB4975.namprd12.prod.outlook.com (2603:10b6:5:1bd::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5123.31; Tue, 5 Apr 2022 13:01:34 +0000 Received: from BN8NAM11FT065.eop-nam11.prod.protection.outlook.com (2603:10b6:408:ea:cafe::46) by BN0PR04CA0081.outlook.office365.com (2603:10b6:408:ea::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5123.31 via Frontend Transport; Tue, 5 Apr 2022 13:01:33 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.236) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.236 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.236; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.236) by BN8NAM11FT065.mail.protection.outlook.com (10.13.177.63) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5123.19 via Frontend Transport; Tue, 5 Apr 2022 13:01:33 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by DRHQMAIL109.nvidia.com (10.27.9.19) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Tue, 5 Apr 2022 13:01:32 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 5 Apr 2022 06:01:32 -0700 Received: from sumitg-l4t.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server id 15.2.986.22 via Frontend Transport; Tue, 5 Apr 2022 06:01:28 -0700 From: Sumit Gupta To: , , , , , , , , , CC: , , , Subject: [Patch v4 1/4] dt-bindings: Document Tegra CCPLEX Cluster Date: Tue, 5 Apr 2022 18:31:16 +0530 Message-ID: <20220405130119.4697-2-sumitg@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220405130119.4697-1-sumitg@nvidia.com> References: <20220405130119.4697-1-sumitg@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1b993c35-5d0e-4316-149b-08da17046932 X-MS-TrafficTypeDiagnostic: DM6PR12MB4975:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zarHcOz+f+dF4Jx70JmICFPCYnnvo2AmENjgPszZoBD0f5ne09e4WXfRfOU+C1cfFJWbERrGFTA6djkkxOXr1n6VEmkaaBhALNwdO71w7hqz/ZnR0NHSWVFaljvG8Xz2nc4ZrJQYLApTwRTVIyoDWqBa8pWGBRhdQ4YCSG7dRfyn/n67VY6gBMu+W/rRJ2uGM1HPDidvR1FuBH+EoJ9J+DEYbi716kKu+eK71hOXSdbljNY7fxY/pyoKzRz2dQayfbmvOfZy9mzazNbhTCCeYmFUkR0tfoVgzJ7OMPI+QhErN2nrZCRF0rUNymxftKWppD1dDNhhsQaaR1o9ntBrL2ebyFPYd3FMIeiCBzc4DQ1v9yMVvGyh0NqAxXGGyySMGweluK1gXzJ+oW3+3W7RCsPBv6Q1HgPyKRMlB+VMwgkC7e+y2/STZnPXS41oJqb9aGmxdkToMBVDQjUTRlcy9v6i1E8dJ3jrXKn0RlNgoVbzYtO/0P3yUKRlHGFiTvj5zRrt3mdZt3AgqutUurX52x8NjPx396dQ7MLntaQF2dphVRz5hemdWmtL4c/dujsyGnjfQrx+N6+TwaMKRIuAjvn1u7zQ3Nk4/nRXEr0wBZDmzwisoyJOLX3OUx3txMBMILR7+rMmw8tcBB2waK7tdn570GsKy/pH/i3G84JGzP79rebVigDyootXpYwYHddQiaH654v6UX7GaxH7xZFUu2tlq4V0i9YFiYds5Rb/lc5awCkU4v0x2HKwnA5MG3droXv8VdOK/th7LFVf8VPjjOTUHgRgXHULB4jye5BzChudPcceR/V2jguzm6e61Uv+e4nRctpGO13uSl8KZ2bV9mi9jBAFm2m8vkKUKNnMLqc= X-Forefront-Antispam-Report: CIP:12.22.5.236; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(4326008)(110136005)(70206006)(70586007)(40460700003)(81166007)(426003)(336012)(82310400005)(8676002)(107886003)(2616005)(356005)(8936002)(86362001)(921005)(2906002)(54906003)(508600001)(36860700001)(316002)(7696005)(5660300002)(1076003)(36756003)(6666004)(47076005)(186003)(26005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Apr 2022 13:01:33.6981 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1b993c35-5d0e-4316-149b-08da17046932 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT065.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4975 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The Tegra CPU COMPLEX CLUSTER area contains memory-mapped registers that initiate CPU frequency/voltage transitions. Signed-off-by: Sumit Gupta --- .../tegra/nvidia,tegra-ccplex-cluster.yaml | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml new file mode 100644 index 000000000000..8c6543b5c0dc --- /dev/null +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra-ccplex-cluster.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: NVIDIA Tegra CPU COMPLEX CLUSTER area device tree bindings + +maintainers: + - Sumit Gupta + - Mikko Perttunen + - Jon Hunter + - Thierry Reding + +description: |+ + The Tegra CPU COMPLEX CLUSTER area contains memory-mapped + registers that initiate CPU frequency/voltage transitions. + +properties: + $nodename: + pattern: "ccplex@([0-9a-f]+)$" + + compatible: + enum: + - nvidia,tegra186-ccplex-cluster + - nvidia,tegra234-ccplex-cluster + + reg: + maxItems: 1 + + nvidia,bpmp: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: | + Specifies the BPMP node that needs to be queried to get + operating point data for all CPUs. + +additionalProperties: false + +required: + - compatible + - reg + - nvidia,bpmp + - status + +examples: + - | + ccplex@e000000 { + compatible = "nvidia,tegra234-ccplex-cluster"; + reg = <0x0e000000 0x5ffff>; + nvidia,bpmp = <&bpmp>; + status = "okay"; + }; From patchwork Tue Apr 5 13:01:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Gupta X-Patchwork-Id: 556412 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA862C433F5 for ; Tue, 5 Apr 2022 14:45:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238187AbiDEOrJ (ORCPT ); Tue, 5 Apr 2022 10:47:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382321AbiDEORP (ORCPT ); Tue, 5 Apr 2022 10:17:15 -0400 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2043.outbound.protection.outlook.com [40.107.220.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 60901160C2F; Tue, 5 Apr 2022 06:01:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=IaVtuKZxcTOU/q4fAtJtao/vXfTPs4HHHAuyXR0XZvutVqh4Q9vlIMw0NpqiRf9YXzgsyZEWQFsWfZDtOaS/ySJBFYy4u9lUnn2cox8hlZE6gwd9MjwNr+pvWp4QQiJauRq2PJQuyWBBpRZMENNfTs/12PiRKsfOLV75PhJVxkYiaZ4dTm2zuwItapE5hZmRn5Vmn6YipocXy4pglUIpmxP/d+wOJADMCSnLiDTJz2EYIuOc352E1dkNEC58SuHvU0LFMwep5wSmcvokrCYmnECwRuL4EoWqHLWFOfXtY5Ed5nrWm9oXBCur1uddDCb7K6Hf9aqAd6gbwVa5RtXaJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=vaSt2YuyCgTMOz8xoVKQnbq/RKA9LOyWJI5LPUGvaFQ=; b=O1hmIz3eguoK4bgRSGuFbBucik5ThYSDoHQtKJrhUYpw+te+5HCB/gzo0cRBOuFcBrkhSf9sWpI6+dUPKSlgXk+WJVeO9mukTrpRz+nzeqjn042lBAbofJG56CkN+wmN9NeX8r+XLtG255SBKbQHy5n6ckh0aEtlGYEv622tZP+NfLskVjY0zdMmLG/UhG9gKI/wvCApLANIeYY0nyzbl5qbpeAX0fB+QiMuNhtqYpNLgHD9obIioMTVu5aRV1q50AwlWQgbcXpEVj2a8bZvmtBLacuNCg2zfPbowoVJ0Nr30hUhwV2g28EBi+SmCMHhJBH64z9XdhSdA4W0Q5p8Og== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.234) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=vaSt2YuyCgTMOz8xoVKQnbq/RKA9LOyWJI5LPUGvaFQ=; b=PsNOuyRejyU0dvlTTStzi034LlyfuoWkUwbgB4yDi3pFTUg0szfPB9fZDPsoYDgzW6mU9xm38KvxPPo1XfwCnCkauzhHdHLkYueQgdLvPDN4RaOukU1voEdH1cvsWBjuOJLrbzM2mNvwyEyTX9D8B2HptngRqQQYspCE6MKOyugly+fd8b/arMSHcdd+2CfEuBToIZo6fwYCFpAorE/Ds3hL9rTjQ+NJlmqFwhnSvJDjz0HgWypvKdYUird2iH7kd+CcJpBoXeE0bDUoDytuHMoIIZWxDvhe0sALb/PPbIbFeWEh6kJrUdzDDP/5emaZsVVkH1vCQ4+jqyjvWfOcnw== Received: from DS7PR03CA0310.namprd03.prod.outlook.com (2603:10b6:8:2b::9) by CY4PR1201MB0216.namprd12.prod.outlook.com (2603:10b6:910:18::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5123.31; Tue, 5 Apr 2022 13:01:38 +0000 Received: from DM6NAM11FT004.eop-nam11.prod.protection.outlook.com (2603:10b6:8:2b:cafe::6) by DS7PR03CA0310.outlook.office365.com (2603:10b6:8:2b::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5123.31 via Frontend Transport; Tue, 5 Apr 2022 13:01:38 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.234) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.234) by DM6NAM11FT004.mail.protection.outlook.com (10.13.172.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5123.19 via Frontend Transport; Tue, 5 Apr 2022 13:01:38 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Tue, 5 Apr 2022 13:01:37 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 5 Apr 2022 06:01:37 -0700 Received: from sumitg-l4t.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server id 15.2.986.22 via Frontend Transport; Tue, 5 Apr 2022 06:01:33 -0700 From: Sumit Gupta To: , , , , , , , , , CC: , , , Subject: [Patch v4 2/4] cpufreq: tegra194: add soc data to support multiple soc Date: Tue, 5 Apr 2022 18:31:17 +0530 Message-ID: <20220405130119.4697-3-sumitg@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220405130119.4697-1-sumitg@nvidia.com> References: <20220405130119.4697-1-sumitg@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c317fe48-f2bc-4447-8f1e-08da17046c0e X-MS-TrafficTypeDiagnostic: CY4PR1201MB0216:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: kvyt1DvwzapVVZ0pWasgYYgpq3pCbxfeJ0qIm8IX/3zj1hhMub6Wil0aaivGkSyvPMW404v7Jfg7nOpt3ZvfvAWTuU+RTBPIV5GPEWi6Av8sTvB8ymYvoG2IxqUZCPEQKlGqRKtpKbhv/HMvUxdeKKz8K6jJIR5Q2EqWMDXYelkZzFj10YGbfCCpiRlnaZPTo8T9JKQnfldNAy/+kiXKf1kMDDSZxWr9AJ4hCIJaIRFDl5LycIQaoMwNVrIFPBBIaxuVA3N6tJkvrehYSeVQXlpY/LqEolSrXRpiK9Za7LiihY/Xv2VjUanUW4VTqht07S8toVhNV5sXAuKo0H1YN2IumiaobSwJ+IdAMhEdy6jRJJfEU9PhGe52qkq+aIhrS8KwFgBfOuOhTgqe1fX9OEwJwUT/+Cfd1NoMjAfk17oX6qyJPkDUbF9DXUiLlThoUTKewAfkKHDQYCvlmsCueQoF8SnZcDx0Urcpocj9x5l25wM724Olu/lhocO6zmcoLNg9jWCVsFsb3hlI9IBmSzIbmocvdewqW4FsI7YN/f8b08IcBGtm81zIVwnJlasc8isv4IWVmJOg9Ju0S8Fk5/ittjqgBdrOdp0XgTh9KNb5um4HesuMRMW2negEBbKrZUJcO2Jo1j5TNxM8LoBN3u7zHWQTmZEWOKcp1MbDjTjPTAjrB1Oq94vFWsrC6sv6D0qRybmWIIJG/Wa46w8KnAr0nT7idU4n8jf4qnlx3Kc= X-Forefront-Antispam-Report: CIP:12.22.5.234; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(36840700001)(46966006)(40470700004)(26005)(186003)(82310400005)(356005)(47076005)(83380400001)(81166007)(86362001)(40460700003)(426003)(336012)(921005)(36860700001)(36756003)(1076003)(8936002)(107886003)(508600001)(2616005)(70586007)(4326008)(8676002)(54906003)(110136005)(316002)(5660300002)(70206006)(2906002)(6666004)(7696005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Apr 2022 13:01:38.4672 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c317fe48-f2bc-4447-8f1e-08da17046c0e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT004.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR1201MB0216 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Adding SoC data and ops to support multiple SoC's in same driver. Signed-off-by: Sumit Gupta --- drivers/cpufreq/tegra194-cpufreq.c | 142 +++++++++++++++++++++-------- 1 file changed, 105 insertions(+), 37 deletions(-) diff --git a/drivers/cpufreq/tegra194-cpufreq.c b/drivers/cpufreq/tegra194-cpufreq.c index ac381db25dbe..2d59b2bd0e1d 100644 --- a/drivers/cpufreq/tegra194-cpufreq.c +++ b/drivers/cpufreq/tegra194-cpufreq.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved + * Copyright (c) 2020 - 2022, NVIDIA CORPORATION. All rights reserved */ #include @@ -35,12 +35,6 @@ enum cluster { MAX_CLUSTERS, }; -struct tegra194_cpufreq_data { - void __iomem *regs; - size_t num_clusters; - struct cpufreq_frequency_table **tables; -}; - struct tegra_cpu_ctr { u32 cpu; u32 coreclk_cnt, last_coreclk_cnt; @@ -52,13 +46,42 @@ struct read_counters_work { struct tegra_cpu_ctr c; }; +struct tegra_cpufreq_ops { + void (*read_counters)(struct tegra_cpu_ctr *c); + void (*set_cpu_ndiv)(struct cpufreq_policy *policy, u64 ndiv); + void (*get_cpu_cluster_id)(u32 cpu, u32 *cpuid, u32 *clusterid); + int (*get_cpu_ndiv)(u32 cpu, u32 cpuid, u32 clusterid, u64 *ndiv); +}; + +struct tegra_cpufreq_soc { + struct tegra_cpufreq_ops *ops; + int maxcpus_per_cluster; +}; + +struct tegra194_cpufreq_data { + void __iomem *regs; + size_t num_clusters; + struct cpufreq_frequency_table **tables; + const struct tegra_cpufreq_soc *soc; +}; + static struct workqueue_struct *read_counters_wq; -static void get_cpu_cluster(void *cluster) +static void tegra_get_cpu_mpidr(void *mpidr) { - u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; + *((u64 *)mpidr) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; +} + +static void tegra194_get_cpu_cluster_id(u32 cpu, u32 *cpuid, u32 *clusterid) +{ + u64 mpidr; + + smp_call_function_single(cpu, tegra_get_cpu_mpidr, &mpidr, true); - *((uint32_t *)cluster) = MPIDR_AFFINITY_LEVEL(mpidr, 1); + if (cpuid) + *cpuid = MPIDR_AFFINITY_LEVEL(mpidr, 0); + if (clusterid) + *clusterid = MPIDR_AFFINITY_LEVEL(mpidr, 1); } /* @@ -85,11 +108,24 @@ static inline u32 map_ndiv_to_freq(struct mrq_cpu_ndiv_limits_response return nltbl->ref_clk_hz / KHZ * ndiv / (nltbl->pdiv * nltbl->mdiv); } +static void tegra194_read_counters(struct tegra_cpu_ctr *c) +{ + u64 val; + + val = read_freq_feedback(); + c->last_refclk_cnt = lower_32_bits(val); + c->last_coreclk_cnt = upper_32_bits(val); + udelay(US_DELAY); + val = read_freq_feedback(); + c->refclk_cnt = lower_32_bits(val); + c->coreclk_cnt = upper_32_bits(val); +} + static void tegra_read_counters(struct work_struct *work) { + struct tegra194_cpufreq_data *data = cpufreq_get_driver_data(); struct read_counters_work *read_counters_work; struct tegra_cpu_ctr *c; - u64 val; /* * ref_clk_counter(32 bit counter) runs on constant clk, @@ -107,13 +143,7 @@ static void tegra_read_counters(struct work_struct *work) work); c = &read_counters_work->c; - val = read_freq_feedback(); - c->last_refclk_cnt = lower_32_bits(val); - c->last_coreclk_cnt = upper_32_bits(val); - udelay(US_DELAY); - val = read_freq_feedback(); - c->refclk_cnt = lower_32_bits(val); - c->coreclk_cnt = upper_32_bits(val); + data->soc->ops->read_counters(c); } /* @@ -177,7 +207,7 @@ static unsigned int tegra194_calculate_speed(u32 cpu) return (rate_mhz * KHZ); /* in KHz */ } -static void get_cpu_ndiv(void *ndiv) +static void tegra194_get_cpu_ndiv_sysreg(void *ndiv) { u64 ndiv_val; @@ -186,30 +216,43 @@ static void get_cpu_ndiv(void *ndiv) *(u64 *)ndiv = ndiv_val; } -static void set_cpu_ndiv(void *data) +static int tegra194_get_cpu_ndiv(u32 cpu, u32 cpuid, u32 clusterid, u64 *ndiv) +{ + int ret; + + ret = smp_call_function_single(cpu, tegra194_get_cpu_ndiv_sysreg, &ndiv, true); + + return ret; +} + +static void tegra194_set_cpu_ndiv_sysreg(void *data) { - struct cpufreq_frequency_table *tbl = data; - u64 ndiv_val = (u64)tbl->driver_data; + u64 ndiv_val = *(u64 *)data; asm volatile("msr s3_0_c15_c0_4, %0" : : "r" (ndiv_val)); } +static void tegra194_set_cpu_ndiv(struct cpufreq_policy *policy, u64 ndiv) +{ + on_each_cpu_mask(policy->cpus, tegra194_set_cpu_ndiv_sysreg, &ndiv, true); +} + static unsigned int tegra194_get_speed(u32 cpu) { struct tegra194_cpufreq_data *data = cpufreq_get_driver_data(); struct cpufreq_frequency_table *pos; + u32 cpuid, clusterid; unsigned int rate; u64 ndiv; int ret; - u32 cl; - smp_call_function_single(cpu, get_cpu_cluster, &cl, true); + data->soc->ops->get_cpu_cluster_id(cpu, &cpuid, &clusterid); /* reconstruct actual cpu freq using counters */ rate = tegra194_calculate_speed(cpu); /* get last written ndiv value */ - ret = smp_call_function_single(cpu, get_cpu_ndiv, &ndiv, true); + ret = data->soc->ops->get_cpu_ndiv(cpu, cpuid, clusterid, &ndiv); if (WARN_ON_ONCE(ret)) return rate; @@ -219,7 +262,7 @@ static unsigned int tegra194_get_speed(u32 cpu) * to the last written ndiv value from freq_table. This is * done to return consistent value. */ - cpufreq_for_each_valid_entry(pos, data->tables[cl]) { + cpufreq_for_each_valid_entry(pos, data->tables[clusterid]) { if (pos->driver_data != ndiv) continue; @@ -237,19 +280,22 @@ static unsigned int tegra194_get_speed(u32 cpu) static int tegra194_cpufreq_init(struct cpufreq_policy *policy) { struct tegra194_cpufreq_data *data = cpufreq_get_driver_data(); - u32 cpu; - u32 cl; + int maxcpus_per_cluster = data->soc->maxcpus_per_cluster; + u32 start_cpu, cpu; + u32 clusterid; - smp_call_function_single(policy->cpu, get_cpu_cluster, &cl, true); + data->soc->ops->get_cpu_cluster_id(policy->cpu, NULL, &clusterid); - if (cl >= data->num_clusters || !data->tables[cl]) + if (clusterid >= data->num_clusters || !data->tables[clusterid]) return -EINVAL; + start_cpu = rounddown(policy->cpu, maxcpus_per_cluster); /* set same policy for all cpus in a cluster */ - for (cpu = (cl * 2); cpu < ((cl + 1) * 2); cpu++) - cpumask_set_cpu(cpu, policy->cpus); - - policy->freq_table = data->tables[cl]; + for (cpu = start_cpu; cpu < (start_cpu + maxcpus_per_cluster); cpu++) { + if (cpu_possible(cpu)) + cpumask_set_cpu(cpu, policy->cpus); + } + policy->freq_table = data->tables[clusterid]; policy->cpuinfo.transition_latency = TEGRA_CPUFREQ_TRANSITION_LATENCY; return 0; @@ -259,13 +305,14 @@ static int tegra194_cpufreq_set_target(struct cpufreq_policy *policy, unsigned int index) { struct cpufreq_frequency_table *tbl = policy->freq_table + index; + struct tegra194_cpufreq_data *data = cpufreq_get_driver_data(); /* * Each core writes frequency in per core register. Then both cores * in a cluster run at same frequency which is the maximum frequency * request out of the values requested by both cores in that cluster. */ - on_each_cpu_mask(policy->cpus, set_cpu_ndiv, tbl, true); + data->soc->ops->set_cpu_ndiv(policy, (u64)tbl->driver_data); return 0; } @@ -280,6 +327,18 @@ static struct cpufreq_driver tegra194_cpufreq_driver = { .attr = cpufreq_generic_attr, }; +static struct tegra_cpufreq_ops tegra194_cpufreq_ops = { + .read_counters = tegra194_read_counters, + .get_cpu_cluster_id = tegra194_get_cpu_cluster_id, + .get_cpu_ndiv = tegra194_get_cpu_ndiv, + .set_cpu_ndiv = tegra194_set_cpu_ndiv, +}; + +const struct tegra_cpufreq_soc tegra194_cpufreq_soc = { + .ops = &tegra194_cpufreq_ops, + .maxcpus_per_cluster = 2, +}; + static void tegra194_cpufreq_free_resources(void) { destroy_workqueue(read_counters_wq); @@ -359,6 +418,7 @@ init_freq_table(struct platform_device *pdev, struct tegra_bpmp *bpmp, static int tegra194_cpufreq_probe(struct platform_device *pdev) { + const struct tegra_cpufreq_soc *soc; struct tegra194_cpufreq_data *data; struct tegra_bpmp *bpmp; int err, i; @@ -367,6 +427,15 @@ static int tegra194_cpufreq_probe(struct platform_device *pdev) if (!data) return -ENOMEM; + soc = of_device_get_match_data(&pdev->dev); + + if (soc->ops && soc->maxcpus_per_cluster) { + data->soc = soc; + } else { + dev_err(&pdev->dev, "soc data missing\n"); + return -EINVAL; + } + data->num_clusters = MAX_CLUSTERS; data->tables = devm_kcalloc(&pdev->dev, data->num_clusters, sizeof(*data->tables), GFP_KERNEL); @@ -416,10 +485,9 @@ static int tegra194_cpufreq_remove(struct platform_device *pdev) } static const struct of_device_id tegra194_cpufreq_of_match[] = { - { .compatible = "nvidia,tegra194-ccplex", }, + { .compatible = "nvidia,tegra194-ccplex", .data = &tegra194_cpufreq_soc }, { /* sentinel */ } }; -MODULE_DEVICE_TABLE(of, tegra194_cpufreq_of_match); static struct platform_driver tegra194_ccplex_driver = { .driver = { From patchwork Tue Apr 5 13:01:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Gupta X-Patchwork-Id: 558689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AF374C433EF for ; Tue, 5 Apr 2022 14:46:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234135AbiDEOsB (ORCPT ); Tue, 5 Apr 2022 10:48:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382327AbiDEORP (ORCPT ); Tue, 5 Apr 2022 10:17:15 -0400 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2045.outbound.protection.outlook.com [40.107.220.45]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 944FC160C3A; Tue, 5 Apr 2022 06:01:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=h55KPj0vTAC0+uQSP4ltWzU5kq6GmPD6U3rPzmQntlBMXCpRuJmh4bPyxs2xdk245rGp0vZ8QcIASqJct0E39h3BCPqR0MiRfIExuIZ6m+tWQOZo6AeP6hLLC+WoxyS5XOrRWK96DG5GmYPs6Un2T6lL0Dvyh3n7XA3OQ5bXzzwVmSM8ShLgVh0SRB+NdNUG/f55kknsEoK/n/AmH/z2LXXDvYmvyEGKEtbx/LDwkb0weF2k3ex2RbiLtgLT6EZCogNSStg2bWCnbLizXCEDjcXeopOstik2EnY6O6hPICwADVT7HnnBBvMykZwqDzJLbDrwY5DnLgEWgMQQXBdxuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Qc4iAL8TXxvbp7/DyB/nsLSUrz912sWCvcI8+//F0VU=; b=gQBGTKt+dlQlaafUzVSHVdonG0V68fRhYdg8bTa+xpMC83oOww7A3JqIsFA4tsMAAcx/i57+XSvwQyVIOdEseVJL5GRaPnHTT2LbBr6cG75lX74N8K98WOaavy4uBRf6bpRkUK/k2A4UT0Gj1qOkZA37+K2X/9uOrIA3fy5bryPuES3g/SHjkrIndNvM5+14OsaM83M93+uWWdaIIz5WrI/DFX/8uBjfjvfXwmaoaz0cSDCJC8ke624LItjit2lU8k+N65AMkaX5V9nNH4XFh8LXYidXxZ6UGANFRvBdqqFYa72mQ+MLpXfEvGCkf4GIqCaA+3bUjzuuUG8IJ7axOw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.235) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Qc4iAL8TXxvbp7/DyB/nsLSUrz912sWCvcI8+//F0VU=; b=ZgZasr3W7WOjwcnpSRzxK4BDXnlIchOTDpbi60p/SLyMzP+fe/wjaX05LhVTzS73Mv6IQ3bmlCGmfdWUOXTHybnX+3sisCI/NPbOEAf3GSkBHIzMwUdlfGzK9Oyta87mWATW0oXi2aRFmq5sSP5m6ArqgK6MQqg9QeJDTF2V/e1wo7q+oESCFA7r4F9h3fEDh1nk0QWUM9QvCyjBn+QOsii8fiwrzVsArnJJotBDVZ2Ei01TtfZVnO76ZwqVP3I2zi+5mWDD9vmsJnFZ/jZPbL/BESI9lmLi6QyvpUOrOi/DDu2goMegbEg1FHbu8WuZwRASmI1XqXgVCVzhElkbNw== Received: from MW4PR03CA0095.namprd03.prod.outlook.com (2603:10b6:303:b7::10) by DS7PR12MB5862.namprd12.prod.outlook.com (2603:10b6:8:79::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5123.31; Tue, 5 Apr 2022 13:01:43 +0000 Received: from CO1NAM11FT029.eop-nam11.prod.protection.outlook.com (2603:10b6:303:b7:cafe::62) by MW4PR03CA0095.outlook.office365.com (2603:10b6:303:b7::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5123.31 via Frontend Transport; Tue, 5 Apr 2022 13:01:43 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.235) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.235 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.235; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.235) by CO1NAM11FT029.mail.protection.outlook.com (10.13.174.214) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5123.19 via Frontend Transport; Tue, 5 Apr 2022 13:01:42 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Tue, 5 Apr 2022 13:01:42 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 5 Apr 2022 06:01:41 -0700 Received: from sumitg-l4t.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server id 15.2.986.22 via Frontend Transport; Tue, 5 Apr 2022 06:01:38 -0700 From: Sumit Gupta To: , , , , , , , , , CC: , , , Subject: [Patch v4 3/4] cpufreq: tegra194: Add support for Tegra234 Date: Tue, 5 Apr 2022 18:31:18 +0530 Message-ID: <20220405130119.4697-4-sumitg@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220405130119.4697-1-sumitg@nvidia.com> References: <20220405130119.4697-1-sumitg@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 06afbc8c-f5c3-4d6a-2f9b-08da17046eab X-MS-TrafficTypeDiagnostic: DS7PR12MB5862:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: x5yl9kNog7rKLeApaZenLoj4KsWfYkg0xctt22QsFw8obbr7t1s/V/HFkcgb+6lvkfS6wSFc3Mapn8IaMw42G+9H4PyxjI6dOhIgqdKf2KY3jj6eGdcpl0YfT0Bxch8q1qydYU8NqtmRrLAG7brgo88ukEg9WP5JbYgPO8pgqIVhzE5R6yqd9W+8hYsNxUU8NynZT16dqf4AdaLYwL154ac6kXU0oA/RRze/iOofzlBWBFpwT39YsNX4kOY+CBVVvLSuSZTlkDvFXNLAmo4uza3YfsAL0z01Hf/HtktTteQpKC1sbN6TbzRvgUo0H/6hNA9hIvmgsj0fIqRzsBdmiZV1UP/FPxXCsAMZ+W6NyJxWr3QM2/sjmeDKlY4whJGm8LMemZZ1BdY9FYronTLih1eZJCoYMjzjYNaGFQNi6pXPIFKibNgRrce8VYEJay/zKb3RCLWpilaL7RHF9PsXI9p+iL3idMFhyTikpFO17CLeicTfKzGa507YP7ctAzcyLuBaCJSQNwKWw1mCkD9WpTwU0e4ivkgpcVUHnuyV6hHVRY4gAv/DDZ+dqQnwB+llG3ccOHmap3uf3iJoNsrk5ZjQEiMdK1078hMGSc2nxrW55VUumrylX3k2IiuNxyr7FrTKCePA9gy39VzyFtVnAAkV1rIUWt874Umd6Tn9oIWx7GcpKCZB0bz8XVO9hCLybOwx0ZnZjLVRDNZjhyyTE9EXxT11jxSuITgQMleZRs4= X-Forefront-Antispam-Report: CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(46966006)(36840700001)(40470700004)(36756003)(47076005)(426003)(336012)(82310400005)(70206006)(70586007)(36860700001)(110136005)(54906003)(8936002)(6666004)(83380400001)(26005)(186003)(4326008)(1076003)(2906002)(5660300002)(86362001)(81166007)(40460700003)(8676002)(316002)(2616005)(107886003)(921005)(508600001)(356005)(7696005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Apr 2022 13:01:42.9273 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 06afbc8c-f5c3-4d6a-2f9b-08da17046eab X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT029.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5862 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org This patch adds driver support for Tegra234 cpufreq. Tegra234 has per core MMIO registers instead of system registers for cpu frequency requests and to read the counters for re-constructing the cpu frequency. Also, MPIDR affinity info in Tegra234 is different from Tegra194. Added ops hooks and soc data for Tegra234. This will help to easily add variants of Tegra234 and future SoC's which use similar logic to {get|set} the cpu frequency. Signed-off-by: Sumit Gupta --- drivers/cpufreq/tegra194-cpufreq.c | 104 +++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) diff --git a/drivers/cpufreq/tegra194-cpufreq.c b/drivers/cpufreq/tegra194-cpufreq.c index 2d59b2bd0e1d..2a6a98764a8c 100644 --- a/drivers/cpufreq/tegra194-cpufreq.c +++ b/drivers/cpufreq/tegra194-cpufreq.c @@ -24,6 +24,17 @@ #define CPUFREQ_TBL_STEP_HZ (50 * KHZ * KHZ) #define MAX_CNT ~0U +#define NDIV_MASK 0x1FF + +#define CORE_OFFSET(cpu) (cpu * 8) +#define CMU_CLKS_BASE 0x2000 +#define SCRATCH_FREQ_CORE_REG(data, cpu) (data->regs + CMU_CLKS_BASE + CORE_OFFSET(cpu)) + +#define MMCRAB_CLUSTER_BASE(cl) (0x30000 + (cl * 0x10000)) +#define CLUSTER_ACTMON_BASE(data, cl) \ + (data->regs + (MMCRAB_CLUSTER_BASE(cl) + data->soc->actmon_cntr_base)) +#define CORE_ACTMON_CNTR_REG(data, cl, cpu) (CLUSTER_ACTMON_BASE(data, cl) + CORE_OFFSET(cpu)) + /* cpufreq transisition latency */ #define TEGRA_CPUFREQ_TRANSITION_LATENCY (300 * 1000) /* unit in nanoseconds */ @@ -56,6 +67,7 @@ struct tegra_cpufreq_ops { struct tegra_cpufreq_soc { struct tegra_cpufreq_ops *ops; int maxcpus_per_cluster; + phys_addr_t actmon_cntr_base; }; struct tegra194_cpufreq_data { @@ -72,6 +84,90 @@ static void tegra_get_cpu_mpidr(void *mpidr) *((u64 *)mpidr) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK; } +static void tegra234_get_cpu_cluster_id(u32 cpu, u32 *cpuid, u32 *clusterid) +{ + u64 mpidr; + + smp_call_function_single(cpu, tegra_get_cpu_mpidr, &mpidr, true); + + if (cpuid) + *cpuid = MPIDR_AFFINITY_LEVEL(mpidr, 1); + if (clusterid) + *clusterid = MPIDR_AFFINITY_LEVEL(mpidr, 2); +} + +static int tegra234_get_cpu_ndiv(u32 cpu, u32 cpuid, u32 clusterid, u64 *ndiv) +{ + struct tegra194_cpufreq_data *data = cpufreq_get_driver_data(); + void __iomem *freq_core_reg; + u64 mpidr_id; + + /* use physical id to get address of per core frequency register */ + mpidr_id = (clusterid * data->soc->maxcpus_per_cluster) + cpuid; + freq_core_reg = SCRATCH_FREQ_CORE_REG(data, mpidr_id); + + *ndiv = readl(freq_core_reg) & NDIV_MASK; + + return 0; +} + +static void tegra234_set_cpu_ndiv(struct cpufreq_policy *policy, u64 ndiv) +{ + struct tegra194_cpufreq_data *data = cpufreq_get_driver_data(); + void __iomem *freq_core_reg; + u32 cpu, cpuid, clusterid; + u64 mpidr_id; + + for_each_cpu_and(cpu, policy->cpus, cpu_online_mask) { + data->soc->ops->get_cpu_cluster_id(cpu, &cpuid, &clusterid); + + /* use physical id to get address of per core frequency register */ + mpidr_id = (clusterid * data->soc->maxcpus_per_cluster) + cpuid; + freq_core_reg = SCRATCH_FREQ_CORE_REG(data, mpidr_id); + + writel(ndiv, freq_core_reg); + } +} + +/* + * This register provides access to two counter values with a single + * 64-bit read. The counter values are used to determine the average + * actual frequency a core has run at over a period of time. + * [63:32] PLLP counter: Counts at fixed frequency (408 MHz) + * [31:0] Core clock counter: Counts on every core clock cycle + */ +static void tegra234_read_counters(struct tegra_cpu_ctr *c) +{ + struct tegra194_cpufreq_data *data = cpufreq_get_driver_data(); + void __iomem *actmon_reg; + u32 cpuid, clusterid; + u64 val; + + data->soc->ops->get_cpu_cluster_id(c->cpu, &cpuid, &clusterid); + actmon_reg = CORE_ACTMON_CNTR_REG(data, clusterid, cpuid); + + val = readq(actmon_reg); + c->last_refclk_cnt = upper_32_bits(val); + c->last_coreclk_cnt = lower_32_bits(val); + udelay(US_DELAY); + val = readq(actmon_reg); + c->refclk_cnt = upper_32_bits(val); + c->coreclk_cnt = lower_32_bits(val); +} + +static struct tegra_cpufreq_ops tegra234_cpufreq_ops = { + .read_counters = tegra234_read_counters, + .get_cpu_cluster_id = tegra234_get_cpu_cluster_id, + .get_cpu_ndiv = tegra234_get_cpu_ndiv, + .set_cpu_ndiv = tegra234_set_cpu_ndiv, +}; + +const struct tegra_cpufreq_soc tegra234_cpufreq_soc = { + .ops = &tegra234_cpufreq_ops, + .actmon_cntr_base = 0x9000, + .maxcpus_per_cluster = 4, +}; + static void tegra194_get_cpu_cluster_id(u32 cpu, u32 *cpuid, u32 *clusterid) { u64 mpidr; @@ -442,6 +538,13 @@ static int tegra194_cpufreq_probe(struct platform_device *pdev) if (!data->tables) return -ENOMEM; + if (soc->actmon_cntr_base) { + /* mmio registers are used for frequency request and re-construction */ + data->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(data->regs)) + return PTR_ERR(data->regs); + } + platform_set_drvdata(pdev, data); bpmp = tegra_bpmp_get(&pdev->dev); @@ -486,6 +589,7 @@ static int tegra194_cpufreq_remove(struct platform_device *pdev) static const struct of_device_id tegra194_cpufreq_of_match[] = { { .compatible = "nvidia,tegra194-ccplex", .data = &tegra194_cpufreq_soc }, + { .compatible = "nvidia,tegra234-ccplex-cluster", .data = &tegra234_cpufreq_soc }, { /* sentinel */ } }; From patchwork Tue Apr 5 13:01:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sumit Gupta X-Patchwork-Id: 558690 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34CAEC433FE for ; Tue, 5 Apr 2022 14:46:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238842AbiDEOrr (ORCPT ); Tue, 5 Apr 2022 10:47:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1382375AbiDEORR (ORCPT ); Tue, 5 Apr 2022 10:17:17 -0400 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2057.outbound.protection.outlook.com [40.107.220.57]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF51511BCF9; Tue, 5 Apr 2022 06:01:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Mv+UgOlWnHKuY8eIzzJH+Dkbio0qMDcVxRFPILH7tHzXNXexipOk+FEDg0H5F3XfjwcVrWp/v4scquDwdpw6n0dw9h5fuLaq5b7tLtvYY6+hKVeUJceEr2YCh1hB0si70ZEaHRx3ciQKSvEYoU2F/WJ0uFsds8jr0FoqxFcwFvBD+07UKPSWxdA83gRgTcFYvR7L1TCc4ukIuZTgnlkJDTU3Vp53sZLwEopj5RmYBKhvwV0U22PJb2Y3z2BZx9fF3hFxeWpLo414ka/cviJIuA9lKbtaHwSUCu8S/ps6kq3OWDDxTgUXglb4+Vs4F6AkbiYRy6YYoXRT7uk55ih0eQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=0jiZqiuA4bL/Xl4sXyXV/fFxhFrzn1JlNSbgW6WB1YI=; b=bxVexal4p09bNddM+nieVgV3IPeYlyvokKeUjCnBKtBvDQBXwTetPuVx6XkXu0Oj63wBYWYRB8fzydAZSe8JIhw1XEVW77KFDVHn7EHJs1V0YCYSHJXjrPZgb6+hBTSqyru+x9hWAqWvUSUF9nLHXtLukn3YwtiCXeBVAZjRnABVgfuUoLCeuwVSuPSDPjC5e2sRElFbzAnFJb6jVgIPNtdkUCIZLL4jgYaQsvEh26c4YP/YZjmwRIWOFp+BZSaPrSIRj4JPZRgyuRKlj8Xmie3gltsCbipuHVvHprjhEft/5fZ262+1QalcqzON3KBdlT3LVkUttqFhOm/Yl9JT2A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 12.22.5.235) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=0jiZqiuA4bL/Xl4sXyXV/fFxhFrzn1JlNSbgW6WB1YI=; b=VnoZZwyYL1GXk65Cch0NN3n49Zo8Pkqr9nG0LzKWwW+6ZLCsS570JgDkoU8cgrG462sm6bwF3d7t3i7n0AklWJPKrGL/PsABxlsAW9LZUFtowujQgnrAft6wKn4MucjfxbkP83Zc7n1O//5uuxGxb8vqej0mCFHorWZ1WRFzz4k7BjkWxJd94CYnlSK+P50ivLTeqfeGz6dPerHdE/LIHR2Z78j0IVO8JhaiEMFhvWVsZYv38+vK8E33rPsgUyxnBfYQXh7rOt8P1BMHdJgmeM35Hq3Vy5Aux4XG9xvFTb+JKwjOnLxMV9Z7XQSoEGMpwXZtNKSkzqRwAirSQMcBAw== Received: from DS7P222CA0005.NAMP222.PROD.OUTLOOK.COM (2603:10b6:8:2e::17) by MWHPR12MB1806.namprd12.prod.outlook.com (2603:10b6:300:10d::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5123.31; Tue, 5 Apr 2022 13:01:48 +0000 Received: from DM6NAM11FT032.eop-nam11.prod.protection.outlook.com (2603:10b6:8:2e:cafe::76) by DS7P222CA0005.outlook.office365.com (2603:10b6:8:2e::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5123.13 via Frontend Transport; Tue, 5 Apr 2022 13:01:48 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 12.22.5.235) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.235 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.235; helo=mail.nvidia.com; Received: from mail.nvidia.com (12.22.5.235) by DM6NAM11FT032.mail.protection.outlook.com (10.13.173.93) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5123.19 via Frontend Transport; Tue, 5 Apr 2022 13:01:47 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Tue, 5 Apr 2022 13:01:47 +0000 Received: from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Tue, 5 Apr 2022 06:01:46 -0700 Received: from sumitg-l4t.nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server id 15.2.986.22 via Frontend Transport; Tue, 5 Apr 2022 06:01:43 -0700 From: Sumit Gupta To: , , , , , , , , , CC: , , , Subject: [Patch v4 4/4] arm64: tegra: add node for tegra234 cpufreq Date: Tue, 5 Apr 2022 18:31:19 +0530 Message-ID: <20220405130119.4697-5-sumitg@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220405130119.4697-1-sumitg@nvidia.com> References: <20220405130119.4697-1-sumitg@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5a0d1af0-1579-4906-61da-08da170471a0 X-MS-TrafficTypeDiagnostic: MWHPR12MB1806:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Zw321ry2odIqITdbSssDdazv89WR6VAk7H4lecQsmHTIzGQ+PMKEtXilrCcNE4dhK0+bWrwJHgGchpJKDI5UIGmB3nZ2A0Cvobfif/adjeTvh8Es/3DPD1wykxYxSiIeF+SSYsYjx3LTpByO80OIzpQHHURvi1xhxYTAISKqO62x0yz+QIyFSEWPlrQ1cj4UzaCdAefddhNijxzwXRPTTvfO3Nf/zgWqhP3CprM6fldqPfOB8psJw9vklyPABZviSuyXQCQwrz2Y521KQbthQFvmnTBMfnpGdduNZ0pt7VLZPRN0uU+Ti3x/MjxllapJJG/kMrWE2yWlEk9/MZDf2efNM2VAAVkhIU8mrLXKACm5cXGtyepyM/GsZbjmujKvHlVhHLLkCqGqQexu1w1ZE4QCLtGoJ4YIQYZptymKOhhcwH9bqtHIz0GN8Cv91rxmOXISKsVWSg3iti1wI3bvnb1dGqb6AnZCBY5v6hHf4k1vE7VzyiNCQQ6I9IozXX2U3UW/jEPJBm4nezTxPJ0L1jrZjLW+fkdp931v+vTCqO9+Gk3v2KLiFscyyPoae7wJ95vz7CoKAzdpp/0aq5g2H1a+ZXduVKx/+Q1Krb8eE8Wk6jO0fZYMq7nT+YdUec3udUQoSBcLRM2YhMI4lNBBbOZaF4FKuYFN6Iv+HotqUB9vl99ITzHgseoy6f2fyDzS4eHfYdieRzkZ80PD12Wfy7ZX8wGNZ9WanzAvjy/62SY= X-Forefront-Antispam-Report: CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(36840700001)(40470700004)(46966006)(2616005)(5660300002)(1076003)(107886003)(2906002)(36860700001)(82310400005)(8936002)(921005)(7696005)(4744005)(356005)(47076005)(36756003)(86362001)(316002)(4326008)(70586007)(70206006)(83380400001)(40460700003)(6666004)(81166007)(8676002)(186003)(26005)(426003)(54906003)(336012)(508600001)(110136005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Apr 2022 13:01:47.8740 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5a0d1af0-1579-4906-61da-08da170471a0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT032.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1806 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Adding cclpex node to represent Tegra234 cpufreq. Tegra234 uses some of the CRAB (Control Register Access Bus) registers for cpu frequency requests. These registers are memory mapped to CCPLEX_MMCRAB_ARM region. In this node, mapping the range of MMCRAB registers required only for cpu frequency info. Signed-off-by: Sumit Gupta --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index aaace605bdaa..610207f3f967 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -1258,6 +1258,13 @@ }; }; + ccplex@e000000 { + compatible = "nvidia,tegra234-ccplex-cluster"; + reg = <0x0 0x0e000000 0x0 0x5ffff>; + nvidia,bpmp = <&bpmp>; + status = "okay"; + }; + sram@40000000 { compatible = "nvidia,tegra234-sysram", "mmio-sram"; reg = <0x0 0x40000000 0x0 0x80000>;