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Tsirkin" , Nelson Escobar , netdev@vger.kernel.org, Rob Clark , Robin Murphy , Suravee Suthikulpanit , virtualization@lists.linux-foundation.org, Will Deacon Cc: Christoph Hellwig , "Tian, Kevin" Subject: [PATCH 2/5] vfio: Require that devices support DMA cache coherence Date: Tue, 5 Apr 2022 13:16:01 -0300 Message-Id: <2-v1-ef02c60ddb76+12ca2-intel_no_snoop_jgg@nvidia.com> In-Reply-To: <0-v1-ef02c60ddb76+12ca2-intel_no_snoop_jgg@nvidia.com> References: X-ClientProxiedBy: BLAPR03CA0132.namprd03.prod.outlook.com (2603:10b6:208:32e::17) To MN2PR12MB4192.namprd12.prod.outlook.com (2603:10b6:208:1d5::15) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e7d9c9f2-6da3-4d58-f19b-08da171f961a X-MS-TrafficTypeDiagnostic: BN6PR12MB1153:EE_|DM6PR12MB4299:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FjwQmjlOmfHCsEM4bLx9JOuZ58gvnWJE4vQiqz1hVqOLAd/inUXi1+L/o97OkajDdSuxwuFHKSucD7F83TamEsuBj0ZeCIJ52VmRRUC/8iNd3s16jLTgBSYPudq6u7+ysm2p92Ta1UrN+DkT004wWHJ7+yYxYocMYWxI201JtdL0NUmQ1B9lwOshvLYhXgkdmbU4Gj3UX2nUojgVeeBzUeU8vPNoR/x5REbzb11Kcu5TdTHn1X2ehKt9esVWZuOEUx5o4woKGTfK0dO9LZQx/YjimD+3N3J8RBAU+1qO578V/5/qULx5xgIlqWEo3ZS+UPRrG6xM7hEJCIo2xceXf0GIDgpTojwG2JP6cuDJlkHgP46ynyB5xbQnefQukIa8inTNyV7IO+vxnLje6Tw6I5bnJSKmizMgTKzVEHn1Xk1FB23Q5yjcl8XTI1UnVy5Rif1XBTMhEh2PfYso86NJNXIsCDeaEXZ3+OOrSOSKUR5TuJKyEiUPe+A0Opc5InphWLt7D5M7VbQJnnzTog2sx7TEDRX1lBvlLB+OvQLaZSe28Fj2pIqz3So+hxLzow/GK1JSoopMCWa0No7Gz72IuJaT7i8CqE1KK7/B3KPzEfXLV768xlMjxDcfDHB0duqb8Z3BqL+d3DNkF43EantczHSVVQ4jojarr6Q15jr1DoHs4km6MwQwH/r6BXiNEpsrr70ckOUoi16F8PaliNHKDw== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:BN6PR12MB1153.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230001)(4636009)(366004)(86362001)(83380400001)(316002)(4326008)(6506007)(8676002)(6486002)(38100700002)(66946007)(186003)(54906003)(508600001)(6666004)(110136005)(66556008)(66476007)(26005)(2906002)(921005)(5660300002)(2616005)(6512007)(36756003)(8936002)(7416002)(4216001); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 08VJmu319hGyDiqOLsMxzAiQdwQyUlrB9i/dRXjY4upczr2I8wMpI7mM2TcTbcGCvxoSjIIgrKN9odU1h4UZbuQY2e7NZguhmDzMk/fkFGoUQ91HOHbFEgh+CtXzckjF5TwreUE4ugz+euXCJzBySAsCaHfdNQjVhuarY2xNmuL9pwvX0mVtO/psTSsmLwfHEPba1ZI03ol6YMe+NwX8SHC7Nxzo8TGpnI2q4H3+LvZjK7lsQOE06+7zCfGULzTFwRVXdLGe8tr9R4I6cjf3npSV91pqiKehXW3scNSl5NO+eiZbUanESBpfQfZHM9cY6Mb0GIIiddt59bJRtuk6ufM8sn468g9AgdzJORmiGL25AkM2fQqTlefoy2mU0FFBS4xygx0r2UTQGiTcufuMCcZ2RQDroHtqaOiDo5gD8bmCznImq+kR3quNedVS1LW3XqheAG0GBY+wLHGZDHA4JTunXks7HfmWCB6exDfcYKC9SOxkfl5jZVcr4OEhR1TKbImoH/so+xAxRkU0dSMBIJKyfOuZKDTPcCU6vpdYw0e9EmLakIYX6IhZAwEE5nzyWsSTnWFJt2eWTknIqvxj3Ur5Z/KtvHac3UVzrlWId7UE+EM+Vt/UkLVZZJgQRAsyW730lRNLvd50vhvjhLDzltIBkHrX99hZBDA78KakgoqPlD9Mo6yv3kJNFIo4G6DcAfUPgLCj4oeDEu30Ouzf6CyojFO7xrFUs1glcn5VOc7cHQpX7t4n59PEZHwLIE2hCMSFrKJHqc67vsd+FOpbZS4ua5Z0agagcG60ERjmaFTQUw3dpHyzcMlPownnwineBpMZ9hbBa5vfuGou6aTkvsUH+UgCpustNawATUYGQ/qobYCCMt5XTrMtxlQixbZjmRzI2dZCCgryC2mNenZJEDF2yUlGazv9nxm7YCAJF690WQKJzPgufVikMWNibQ8VKnLp+thIGKYwNl4u+4h/RmiySn6qvpMHxtg5ZaScKcWc/vxLTISYwwdHxoT7M+RJQc/R4FZAytM5nzbrIBAbmIsTEUD5D7HFw+apg9zzQLHfphfLAoPjzQOzkjpq4bbC6usZxqI9C1xFBlNmLgaHaChNDuoQqCvJDzzX6SOZqr0IV1Nn4ssb2CbEWA5AqWlxBtyBEh3YDY4D3tGs9uaFGE3utZ8mVdnjBXYfSm5ze2xP0S4hxzkOeljIaM8EF0jYKsd91noGht7aWzphgLxCGftV+aM6IWbTAyptJ5jEIOnJSVWviTHgj2JGLJmt2lAj3InVdZhlnOoZTfU0NrAMRlXBlG725bdKCLquaybThSkqHSrAB7YLPnGM0e/gtqZ4cUt5KxIqzz5gGMA2sQWeixN6xo3i/b1Rxsy2TKj6W+DVbMVrqvTkVtHKZMc7C7EnDeidXdmvchLeOzO6U9weNa2Bgv/Xn1Gelpdu+K7qUGGx52938zx4uxpq1xtRMlDkiWPUC0HB4z09PGvdyUMKoYSadfaDaWiXTXdOoXFIXHymYcGW3IIeKYClavvPPBkb6RIs2i9IE9eX1EhlnP7SnVso5NbgeFmhNgMLWI7qJ1gm03pcB8OiowWA64Eku/TQ5zD1M2MSfqQpPoCMN/jhuHErBIQftsKtHFTM+wtXBnH3tdLXj0f6BeTQN0XKL2LuCKjr7wbJyijRLW1q3lfP9W8FB2QKrEMzQ3osPLGeBtBiae2hq23ouZGxFlH9kz7XRJHwFFbs0VIuvAzADF1cuA== X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: e7d9c9f2-6da3-4d58-f19b-08da171f961a X-MS-Exchange-CrossTenant-AuthSource: MN2PR12MB4192.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Apr 2022 16:16:06.0037 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: rddkv4Z2JH8AOMnvNH5drmyDeecvvoIMqRchnNMRWub/IZvyy0eso1eUnxmEhhBm X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4299 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org dev_is_dma_coherent() is the control to determine if IOMMU_CACHE can be supported. IOMMU_CACHE means that normal DMAs do not require any additional coherency mechanism and is the basic uAPI that VFIO exposes to userspace. For instance VFIO applications like DPDK will not work if additional coherency operations are required. Therefore check dev_is_dma_coherent() before allowing a device to join a domain. This will block device/platform/iommu combinations from using VFIO that do not support cache coherent DMA. Signed-off-by: Jason Gunthorpe --- drivers/vfio/vfio.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/vfio/vfio.c b/drivers/vfio/vfio.c index a4555014bd1e72..2a3aa3e742d943 100644 --- a/drivers/vfio/vfio.c +++ b/drivers/vfio/vfio.c @@ -32,6 +32,7 @@ #include #include #include +#include #include "vfio.h" #define DRIVER_VERSION "0.3" @@ -1348,6 +1349,11 @@ static int vfio_group_get_device_fd(struct vfio_group *group, char *buf) if (IS_ERR(device)) return PTR_ERR(device); + if (group->type == VFIO_IOMMU && !dev_is_dma_coherent(device->dev)) { + ret = -ENODEV; + goto err_device_put; + } + if (!try_module_get(device->dev->driver->owner)) { ret = -ENODEV; goto err_device_put; From patchwork Tue Apr 5 16:16:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 556302 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57A5EC433EF for ; Tue, 5 Apr 2022 23:26:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231773AbiDEXD6 (ORCPT ); Tue, 5 Apr 2022 19:03:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1457618AbiDEQSK (ORCPT ); Tue, 5 Apr 2022 12:18:10 -0400 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2067.outbound.protection.outlook.com [40.107.93.67]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE05119C2B; Tue, 5 Apr 2022 09:16:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jsgQSR/6/4R1rUCJcVM/8aIXWPJEpVGRU/H5HB1VJTNc+8uyO6yCARBF3KOEQ2vif2yZvxsuTMhYnbJFFyM6/hA4G4qIprRk4QxblrQskhfg+PPnaZFnO9vkExIA1cialWUSuaY+DfSav7po/KHKfpNepUdlF2Yboa0I19r5/upwQ11AWCLOfTSlzzjHVpEscpybeo7gmumyFMdP5otheFmgeCqz7PYKerzUwr7DSu7boZDlD+rMP7ayXVPiI4yqliCAeDg7ZNdve6XwVZ1bajneReuCmE0KFvcJTme80AQZdFA8WfX4+DWOy3EuxlvyxOvURv7S+PhLy2eGNiYsoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=2cXS8aEB142780tos2+ZV5bahKx5euq/IyIr1ripIAU=; b=Td0IWkW+ue5ppRzJn37yS51hwr0+UuiPfNDH1qHOXSMTAiHn4udF1XOI7XV6GfoubTVGIdxRLMFCY/xTMeOERsF0pNpqdip9kMRvKmcQmqYxFptIxtvryJnrXJC5RAwfPs+x1nZxveYLg7HhijCZpjl1wqNji1Y/zy75+ltmgtRm9TjFK8B6KtksNkyQ4k+1H5tNNpGI+TeSoecAfXFA4XN/zwi0bHhv7xwrJkR3XB/a8YX6cMpoqFibQGjqXzhoX1Olm3MuS302QOCbV3Mwc2V1RpxdP5JNi9KgB0Y0g6v6kmW8vsASDuQPnGgF2/0shRW8Z4PDnRpCZiGMTeGdSw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=2cXS8aEB142780tos2+ZV5bahKx5euq/IyIr1ripIAU=; b=DaQrdIeGrKOkWrJbB3bGVcfO0Ad5+eD5xLAJ/a0jQAgYLopbQ7210tFV3mTtW7NvwyWXk77S91OryH16gtV9R+YKXPM3beQlwVH5WN3CmxJ3ks0Z7s0nD9AASskjtonXYhFfjxfkFccAhHYYH1oW0J3d31shAdkbwZldBZhDlOUJevkEnPZZaNo0H5C2MKLqYKApxh/EVM07whGV8M3VPAQ6t5asHd7Jd3x075osgHt9DIkpSa618ast25MoMt2wwcl+gjPYFdVrrj22b32V3ndqsq9QNKj3UfObA2l+e25Iqr+NFLtLS7DL9atXi4m1JgXC+ub9ZUTSYhopgy7taQ== Received: from BN6PR12MB1153.namprd12.prod.outlook.com (2603:10b6:404:19::17) by MWHPR12MB1488.namprd12.prod.outlook.com (2603:10b6:301:f::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5123.31; Tue, 5 Apr 2022 16:16:09 +0000 Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from MN2PR12MB4192.namprd12.prod.outlook.com (2603:10b6:208:1d5::15) by BN6PR12MB1153.namprd12.prod.outlook.com (2603:10b6:404:19::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5123.31; Tue, 5 Apr 2022 16:16:08 +0000 Received: from MN2PR12MB4192.namprd12.prod.outlook.com ([fe80::cdfb:f88e:410b:9374]) by MN2PR12MB4192.namprd12.prod.outlook.com ([fe80::cdfb:f88e:410b:9374%5]) with mapi id 15.20.5123.031; Tue, 5 Apr 2022 16:16:08 +0000 From: Jason Gunthorpe To: Alex Williamson , Lu Baolu , Christian Benvenuti , Cornelia Huck , David Woodhouse , Gerald Schaefer , iommu@lists.linux-foundation.org, Jason Wang , Joerg Roedel , kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-rdma@vger.kernel.org, linux-s390@vger.kernel.org, Matthew Rosato , "Michael S. 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Currently only Intel and AMD IOMMUs are known to support this feature. They both implement it as an IOPTE bit, that when set, will cause PCIe TLPs to that IOVA with the no-snoop bit set to be treated as though the no-snoop bit was clear. The new API is triggered by calling enforce_cache_coherency() before mapping any IOVA to the domain which globally switches on no-snoop blocking. This allows other implementations that might block no-snoop globally and outside the IOPTE - AMD also documents such an HW capability. Leave AMD out of sync with Intel and have it block no-snoop even for in-kernel users. This can be trivially resolved in a follow up patch. Only VFIO will call this new API. Signed-off-by: Jason Gunthorpe --- drivers/iommu/amd/iommu.c | 7 +++++++ drivers/iommu/intel/iommu.c | 14 +++++++++++++- include/linux/intel-iommu.h | 1 + include/linux/iommu.h | 4 ++++ 4 files changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index a1ada7bff44e61..e500b487eb3429 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2271,6 +2271,12 @@ static int amd_iommu_def_domain_type(struct device *dev) return 0; } +static bool amd_iommu_enforce_cache_coherency(struct iommu_domain *domain) +{ + /* IOMMU_PTE_FC is always set */ + return true; +} + const struct iommu_ops amd_iommu_ops = { .capable = amd_iommu_capable, .domain_alloc = amd_iommu_domain_alloc, @@ -2293,6 +2299,7 @@ const struct iommu_ops amd_iommu_ops = { .flush_iotlb_all = amd_iommu_flush_iotlb_all, .iotlb_sync = amd_iommu_iotlb_sync, .free = amd_iommu_domain_free, + .enforce_cache_coherency = amd_iommu_enforce_cache_coherency, } }; diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index df5c62ecf942b8..f08611a6cc4799 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -4422,7 +4422,8 @@ static int intel_iommu_map(struct iommu_domain *domain, prot |= DMA_PTE_READ; if (iommu_prot & IOMMU_WRITE) prot |= DMA_PTE_WRITE; - if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping) + if (((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping) || + dmar_domain->enforce_no_snoop) prot |= DMA_PTE_SNP; max_addr = iova + size; @@ -4545,6 +4546,16 @@ static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain, return phys; } +static bool intel_iommu_enforce_cache_coherency(struct iommu_domain *domain) +{ + struct dmar_domain *dmar_domain = to_dmar_domain(domain); + + if (!dmar_domain->iommu_snooping) + return false; + dmar_domain->enforce_no_snoop = true; + return true; +} + static bool intel_iommu_capable(enum iommu_cap cap) { if (cap == IOMMU_CAP_CACHE_COHERENCY) @@ -4898,6 +4909,7 @@ const struct iommu_ops intel_iommu_ops = { .iotlb_sync = intel_iommu_tlb_sync, .iova_to_phys = intel_iommu_iova_to_phys, .free = intel_iommu_domain_free, + .enforce_cache_coherency = intel_iommu_enforce_cache_coherency, } }; diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h index 2f9891cb3d0014..1f930c0c225d94 100644 --- a/include/linux/intel-iommu.h +++ b/include/linux/intel-iommu.h @@ -540,6 +540,7 @@ struct dmar_domain { u8 has_iotlb_device: 1; u8 iommu_coherency: 1; /* indicate coherency of iommu access */ u8 iommu_snooping: 1; /* indicate snooping control feature */ + u8 enforce_no_snoop : 1; /* Create IOPTEs with snoop control */ struct list_head devices; /* all devices' list */ struct iova_domain iovad; /* iova's that belong to this domain */ diff --git a/include/linux/iommu.h b/include/linux/iommu.h index 9208eca4b0d1ac..fe4f24c469c373 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -272,6 +272,9 @@ struct iommu_ops { * @iotlb_sync: Flush all queued ranges from the hardware TLBs and empty flush * queue * @iova_to_phys: translate iova to physical address + * @enforce_cache_coherency: Prevent any kind of DMA from bypassing IOMMU_CACHE, + * including no-snoop TLPs on PCIe or other platform + * specific mechanisms. * @enable_nesting: Enable nesting * @set_pgtable_quirks: Set io page table quirks (IO_PGTABLE_QUIRK_*) * @free: Release the domain after use. @@ -300,6 +303,7 @@ struct iommu_domain_ops { phys_addr_t (*iova_to_phys)(struct iommu_domain *domain, dma_addr_t iova); + bool (*enforce_cache_coherency)(struct iommu_domain *domain); int (*enable_nesting)(struct iommu_domain *domain); int (*set_pgtable_quirks)(struct iommu_domain *domain, unsigned long quirks); From patchwork Tue Apr 5 16:16:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 556276 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E80BDC433F5 for ; Tue, 5 Apr 2022 23:34:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1575562AbiDEXIQ (ORCPT ); Tue, 5 Apr 2022 19:08:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1457616AbiDEQSK (ORCPT ); Tue, 5 Apr 2022 12:18:10 -0400 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2082.outbound.protection.outlook.com [40.107.223.82]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88FFF19C16; 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The definition allows for special non-coherent DMA to exist - ie processing of the no-snoop flag in PCIe TLPs - so long as this behavior is opt-in by the device driver. The flag is used by the DMA API and is always available if dev_is_dma_coherent() is set. For Intel IOMMU IOMMU_CACHE was redefined to mean 'force all DMA to be cache coherent' which has the practical effect of causing the IOMMU to ignore the no-snoop bit in a PCIe TLP. x86 platforms are always IOMMU_CACHE, so Intel should ignore this flag. Instead use the new domain op enforce_cache_coherency() which causes every IOPTE created in the domain to have the no-snoop blocking behavior. Reconfigure VFIO to always use IOMMU_CACHE and call enforce_cache_coherency() to operate the special Intel behavior. Remove the IOMMU_CACHE test from Intel IOMMU. Ultimately VFIO plumbs the result of enforce_cache_coherency() back into the x86 platform code through kvm_arch_register_noncoherent_dma() which controls if the WBINVD instruction is available in the guest. No other arch implements kvm_arch_register_noncoherent_dma(). Signed-off-by: Jason Gunthorpe --- drivers/iommu/intel/iommu.c | 3 +-- drivers/vfio/vfio_iommu_type1.c | 30 +++++++++++++++++++----------- 2 files changed, 20 insertions(+), 13 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index f08611a6cc4799..0ca43671d934e9 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -4422,8 +4422,7 @@ static int intel_iommu_map(struct iommu_domain *domain, prot |= DMA_PTE_READ; if (iommu_prot & IOMMU_WRITE) prot |= DMA_PTE_WRITE; - if (((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping) || - dmar_domain->enforce_no_snoop) + if (dmar_domain->enforce_no_snoop) prot |= DMA_PTE_SNP; max_addr = iova + size; diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type1.c index 9394aa9444c10c..c13b9290e35759 100644 --- a/drivers/vfio/vfio_iommu_type1.c +++ b/drivers/vfio/vfio_iommu_type1.c @@ -84,8 +84,8 @@ struct vfio_domain { struct iommu_domain *domain; struct list_head next; struct list_head group_list; - int prot; /* IOMMU_CACHE */ - bool fgsp; /* Fine-grained super pages */ + bool fgsp : 1; /* Fine-grained super pages */ + bool enforce_cache_coherency : 1; }; struct vfio_dma { @@ -1461,7 +1461,7 @@ static int vfio_iommu_map(struct vfio_iommu *iommu, dma_addr_t iova, list_for_each_entry(d, &iommu->domain_list, next) { ret = iommu_map(d->domain, iova, (phys_addr_t)pfn << PAGE_SHIFT, - npage << PAGE_SHIFT, prot | d->prot); + npage << PAGE_SHIFT, prot | IOMMU_CACHE); if (ret) goto unwind; @@ -1771,7 +1771,7 @@ static int vfio_iommu_replay(struct vfio_iommu *iommu, } ret = iommu_map(domain->domain, iova, phys, - size, dma->prot | domain->prot); + size, dma->prot | IOMMU_CACHE); if (ret) { if (!dma->iommu_mapped) { vfio_unpin_pages_remote(dma, iova, @@ -1859,7 +1859,7 @@ static void vfio_test_domain_fgsp(struct vfio_domain *domain) return; ret = iommu_map(domain->domain, 0, page_to_phys(pages), PAGE_SIZE * 2, - IOMMU_READ | IOMMU_WRITE | domain->prot); + IOMMU_READ | IOMMU_WRITE | IOMMU_CACHE); if (!ret) { size_t unmapped = iommu_unmap(domain->domain, 0, PAGE_SIZE); @@ -2267,8 +2267,15 @@ static int vfio_iommu_type1_attach_group(void *iommu_data, goto out_detach; } - if (iommu_capable(bus, IOMMU_CAP_CACHE_COHERENCY)) - domain->prot |= IOMMU_CACHE; + /* + * If the IOMMU can block non-coherent operations (ie PCIe TLPs with + * no-snoop set) then VFIO always turns this feature on because on Intel + * platforms it optimizes KVM to disable wbinvd emulation. + */ + if (domain->domain->ops->enforce_cache_coherency) + domain->enforce_cache_coherency = + domain->domain->ops->enforce_cache_coherency( + domain->domain); /* * Try to match an existing compatible domain. We don't want to @@ -2279,7 +2286,8 @@ static int vfio_iommu_type1_attach_group(void *iommu_data, */ list_for_each_entry(d, &iommu->domain_list, next) { if (d->domain->ops == domain->domain->ops && - d->prot == domain->prot) { + d->enforce_cache_coherency == + domain->enforce_cache_coherency) { iommu_detach_group(domain->domain, group->iommu_group); if (!iommu_attach_group(d->domain, group->iommu_group)) { @@ -2611,14 +2619,14 @@ static void vfio_iommu_type1_release(void *iommu_data) kfree(iommu); } -static int vfio_domains_have_iommu_cache(struct vfio_iommu *iommu) +static int vfio_domains_have_enforce_cache_coherency(struct vfio_iommu *iommu) { struct vfio_domain *domain; int ret = 1; mutex_lock(&iommu->lock); list_for_each_entry(domain, &iommu->domain_list, next) { - if (!(domain->prot & IOMMU_CACHE)) { + if (!(domain->enforce_cache_coherency)) { ret = 0; break; } @@ -2641,7 +2649,7 @@ static int vfio_iommu_type1_check_extension(struct vfio_iommu *iommu, case VFIO_DMA_CC_IOMMU: if (!iommu) return 0; - return vfio_domains_have_iommu_cache(iommu); + return vfio_domains_have_enforce_cache_coherency(iommu); default: return 0; } From patchwork Tue Apr 5 16:16:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jason Gunthorpe X-Patchwork-Id: 556299 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 218E2C433FE for ; Tue, 5 Apr 2022 23:26:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245342AbiDEXE4 (ORCPT ); Tue, 5 Apr 2022 19:04:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1457617AbiDEQSK (ORCPT ); Tue, 5 Apr 2022 12:18:10 -0400 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2087.outbound.protection.outlook.com [40.107.93.87]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B443919C18; 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Signed-off-by: Jason Gunthorpe --- drivers/iommu/amd/iommu.c | 2 -- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 2 -- drivers/iommu/arm/arm-smmu/arm-smmu.c | 6 ------ drivers/iommu/arm/arm-smmu/qcom_iommu.c | 6 ------ drivers/iommu/fsl_pamu_domain.c | 6 ------ drivers/iommu/intel/iommu.c | 2 -- drivers/iommu/s390-iommu.c | 2 -- include/linux/iommu.h | 2 -- 8 files changed, 28 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index e500b487eb3429..f144eb9fea8e31 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2156,8 +2156,6 @@ static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom, static bool amd_iommu_capable(enum iommu_cap cap) { switch (cap) { - case IOMMU_CAP_CACHE_COHERENCY: - return true; case IOMMU_CAP_INTR_REMAP: return (irq_remapping_enabled == 1); case IOMMU_CAP_NOEXEC: diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 627a3ed5ee8fd1..c4115015a633a7 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1986,8 +1986,6 @@ static const struct iommu_flush_ops arm_smmu_flush_ops = { static bool arm_smmu_capable(enum iommu_cap cap) { switch (cap) { - case IOMMU_CAP_CACHE_COHERENCY: - return true; case IOMMU_CAP_NOEXEC: return true; default: diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 568cce590ccc13..166bf45ac3d444 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1333,12 +1333,6 @@ static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain, static bool arm_smmu_capable(enum iommu_cap cap) { switch (cap) { - case IOMMU_CAP_CACHE_COHERENCY: - /* - * Return true here as the SMMU can always send out coherent - * requests. - */ - return true; case IOMMU_CAP_NOEXEC: return true; default: diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c index 4c077c38fbd64f..fc72465fc63d50 100644 --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c @@ -496,12 +496,6 @@ static phys_addr_t qcom_iommu_iova_to_phys(struct iommu_domain *domain, static bool qcom_iommu_capable(enum iommu_cap cap) { switch (cap) { - case IOMMU_CAP_CACHE_COHERENCY: - /* - * Return true here as the SMMU can always send out coherent - * requests. - */ - return true; case IOMMU_CAP_NOEXEC: return true; default: diff --git a/drivers/iommu/fsl_pamu_domain.c b/drivers/iommu/fsl_pamu_domain.c index 69a4a62dc3b9c7..9f80285dab2951 100644 --- a/drivers/iommu/fsl_pamu_domain.c +++ b/drivers/iommu/fsl_pamu_domain.c @@ -177,11 +177,6 @@ static phys_addr_t fsl_pamu_iova_to_phys(struct iommu_domain *domain, return iova; } -static bool fsl_pamu_capable(enum iommu_cap cap) -{ - return cap == IOMMU_CAP_CACHE_COHERENCY; -} - static void fsl_pamu_domain_free(struct iommu_domain *domain) { struct fsl_dma_domain *dma_domain = to_fsl_dma_domain(domain); @@ -451,7 +446,6 @@ static void fsl_pamu_release_device(struct device *dev) } static const struct iommu_ops fsl_pamu_ops = { - .capable = fsl_pamu_capable, .domain_alloc = fsl_pamu_domain_alloc, .probe_device = fsl_pamu_probe_device, .release_device = fsl_pamu_release_device, diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 0ca43671d934e9..e5062461ab0640 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -4557,8 +4557,6 @@ static bool intel_iommu_enforce_cache_coherency(struct iommu_domain *domain) static bool intel_iommu_capable(enum iommu_cap cap) { - if (cap == IOMMU_CAP_CACHE_COHERENCY) - return domain_update_iommu_snooping(NULL); if (cap == IOMMU_CAP_INTR_REMAP) return irq_remapping_enabled == 1; diff --git a/drivers/iommu/s390-iommu.c b/drivers/iommu/s390-iommu.c index 3833e86c6e7b8a..3dbf9663246552 100644 --- a/drivers/iommu/s390-iommu.c +++ b/drivers/iommu/s390-iommu.c @@ -42,8 +42,6 @@ static struct s390_domain *to_s390_domain(struct iommu_domain *dom) static bool s390_iommu_capable(enum iommu_cap cap) { switch (cap) { - case IOMMU_CAP_CACHE_COHERENCY: - return true; case IOMMU_CAP_INTR_REMAP: return true; default: diff --git a/include/linux/iommu.h b/include/linux/iommu.h index fe4f24c469c373..aebb73bda19797 100644 --- a/include/linux/iommu.h +++ b/include/linux/iommu.h @@ -103,8 +103,6 @@ static inline bool iommu_is_dma_domain(struct iommu_domain *domain) } enum iommu_cap { - IOMMU_CAP_CACHE_COHERENCY, /* IOMMU can enforce cache coherent DMA - transactions */ IOMMU_CAP_INTR_REMAP, /* IOMMU supports interrupt isolation */ IOMMU_CAP_NOEXEC, /* IOMMU_NOEXEC flag */ };