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Mon, 28 Mar 2022 20:55:23 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT009.mail.protection.outlook.com (10.13.176.65) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5102.17 via Frontend Transport; Mon, 28 Mar 2022 20:55:23 +0000 Received: from AUS-LX-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Mon, 28 Mar 2022 15:55:22 -0500 From: Mario Limonciello To: Bjorn Helgaas , "open list:PCI SUBSYSTEM" CC: , , Mario Limonciello Subject: [PATCH v5 1/2] PCI / ACPI: Assume `HotPlugSupportInD3` only if device can wake from D3 Date: Mon, 28 Mar 2022 15:55:18 -0500 Message-ID: <20220328205519.250-1-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4c17aaad-c5d4-4ee0-448c-08da10fd474c X-MS-TrafficTypeDiagnostic: DM6PR12MB4187:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230001)(6029001)(4636009)(40470700004)(36840700001)(46966006)(356005)(81166007)(36756003)(45080400002)(316002)(2616005)(16526019)(26005)(44832011)(186003)(426003)(336012)(2906002)(1076003)(7696005)(47076005)(6666004)(8936002)(83380400001)(82310400004)(110136005)(5660300002)(36860700001)(54906003)(70586007)(4326008)(8676002)(70206006)(40460700003)(966005)(86362001)(508600001)(81973001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Mar 2022 20:55:23.4672 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4c17aaad-c5d4-4ee0-448c-08da10fd474c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4187 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org According to the Microsoft spec the _DSD `HotPlugSupportInD3` is indicates the ability for a bridge to be able to wakeup from D3: This ACPI object [HotPlugSupportInD3] enables the operating system to identify and power manage PCIe Root Ports that are capable of handling hot plug events while in D3 state. This however is static information in the ACPI table at BIOS compilation time and on some platforms it's possible to configure the firmware at boot up such that _S0W returns "0" indicating the inability to wake up the device from D3 as explained in the ACPI specification: 7.3.20 _S0W (S0 Device Wake State) This object evaluates to an integer that conveys to OSPM the deepest D-state supported by this device in the S0 system sleeping state where the device can wake itself. This mismatch may lead to being unable to enumerate devices behind the hotplug bridge when a device is plugged in. To remedy these situations that `HotPlugSupportInD3` is specified by _S0W returns 0, explicitly check that the ACPI companion has returned _S0W greater than or equal to 3 and the device has a GPE allowing the device to generate wakeup signals handled by the platform in `acpi_pci_bridge_d3`. Windows 10 and Windows 11 both will prevent the bridge from going in D3 when the firmware is configured this way and this changes aligns the handling of the situation to be the same. Link: https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/07_Power_and_Performance_Mgmt/device-power-management-objects.html?highlight=s0w#s0w-s0-device-wake-state Link: https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports#identifying-pcie-root-ports-supporting-hot-plug-in-d3 Fixes: 26ad34d510a87 ("PCI / ACPI: Whitelist D3 for more PCIe hotplug ports") Signed-off-by: Mario Limonciello --- v4-v5: * Don't fail if _S0W is missing drivers/pci/pci-acpi.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 1f15ab7eabf8..91c165ea4346 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -977,6 +977,7 @@ bool acpi_pci_bridge_d3(struct pci_dev *dev) const union acpi_object *obj; struct acpi_device *adev; struct pci_dev *rpdev; + unsigned long long ret; if (acpi_pci_disabled || !dev->is_hotplug_bridge) return false; @@ -1003,7 +1004,21 @@ bool acpi_pci_bridge_d3(struct pci_dev *dev) ACPI_TYPE_INTEGER, &obj) < 0) return false; - return obj->integer.value == 1; + if (!obj->integer.value) + return false; + + /* + * If 'HotPlugSupportInD3' is set, but wakeup is not actually supported, + * the former cannot be trusted anyway, so validate it by verifying the + * latter. + */ + if (!adev->wakeup.flags.valid) + return false; + + if (ACPI_SUCCESS(acpi_evaluate_integer(adev->handle, "_S0W", NULL, &ret))) + return ret >= ACPI_STATE_D3_HOT; + + return true; } int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state) From patchwork Mon Mar 28 20:55:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mario Limonciello X-Patchwork-Id: 555480 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9637BC4332F for ; Mon, 28 Mar 2022 20:55:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230362AbiC1U5J (ORCPT ); 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Mon, 28 Mar 2022 15:55:22 -0500 From: Mario Limonciello To: Bjorn Helgaas , "open list:PCI SUBSYSTEM" CC: , , Mario Limonciello , Bjorn Helgaas Subject: [PATCH v5 2/2] PCI / ACPI: Adjust comment about `HotPlugSupportInD3` Date: Mon, 28 Mar 2022 15:55:19 -0500 Message-ID: <20220328205519.250-2-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220328205519.250-1-mario.limonciello@amd.com> References: <20220328205519.250-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 47698720-300f-4789-29d8-08da10fd47b5 X-MS-TrafficTypeDiagnostic: MN0PR12MB5908:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: SdB2cdvVBSxq5SdXaxQGS0eq/cSGg/Rvoxgo0lAdCBXMnGrTInJMk1l0qNFDTC2GSOKU5Pm1U2aD/we03TDzGvDAytIVqxu+/UNPiRhLfs2pDqchjtToEQ3v1CX0NgFGRbNGCT8AhZIUsmejnxDgA14Yp2U9uCIQEbz8xqHcWNgNOIsdwKur85qA6WQ4TO2jEED6R9XNbUu09NfmoZZbIWlIo/XGkCS3QDt+zHy9OiNU3I0j5Sn9QIqt0VNHi8+aPLDyJem1iTWJFwcdF+mMpSo8OzIUf1aUKcFD2aL6OXyc/lbYn2/RLDDjnAHwGjQtEqJG3DzbWZUOd/aQhZ83PuFHnOvD27QZm6gRO/7QNioeN1rvZuoqPq/KPA8vaJcMJrfqVSWiQ98gVNlXEZ/f0CJB0zISF7cpmC32w5uPnQhTciYB0IJntwdNsowPRvwnP558KQYwjvcG1SfIXaxDSyFsJcvHz/y9L8twdKLetvBdWCmc64g906i6t/Mv7MXGrHNArS6POrm0+zQo360OVTuRYnBRCJTiyA9bP9TJX7DcaYQWqE2Y80gPVD0HVu6CEo59s+9XBbaxf85c1D05OlyXHfwoohpCuY1hk+G2eTH/IwkasZnWkqZHwjE06tjykHN0/OxGc5ViHlurVEqu6V5/sr0VltMy64KroYVYU7tmAyL0swBfXcfWHrGyWJA1aa/N60/YoqSXdTzxF6flfsz1O4OE5wznKl14bs7GnR8= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230001)(6029001)(4636009)(46966006)(36840700001)(40470700004)(47076005)(83380400001)(1076003)(81166007)(186003)(54906003)(26005)(316002)(110136005)(44832011)(336012)(82310400004)(426003)(2616005)(16526019)(5660300002)(6666004)(70206006)(70586007)(7696005)(4326008)(2906002)(8676002)(36756003)(36860700001)(508600001)(356005)(86362001)(40460700003)(8936002)(81973001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Mar 2022 20:55:24.1546 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 47698720-300f-4789-29d8-08da10fd47b5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5908 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The comments in `acpi_pci_bridge_d3` make an assertion that all devices behind a PCIe root port that supports D3 also support D3. This was pointed out however that it's no guarantee but rather a reasonable assumption for the ecosystem used for Thunderbolt and USB4. Update the comment to use weaker language and clarifying this is an assumption. Suggested-by: Bjorn Helgaas Signed-off-by: Mario Limonciello --- v4->v5: * New patch drivers/pci/pci-acpi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 91c165ea4346..4f12d4fca808 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -989,8 +989,8 @@ bool acpi_pci_bridge_d3(struct pci_dev *dev) /* * The ACPI firmware will provide the device-specific properties through * _DSD configuration object. Look for the 'HotPlugSupportInD3' property - * for the root port and if it is set we know the hierarchy behind it - * supports D3 just fine. + * for the root port and if it is set we make an assumption that the + * hierarchy behind it supports D3 as well. */ rpdev = pcie_find_root_port(dev); if (!rpdev)