From patchwork Fri Mar 25 20:03:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 554144 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38C7AC4332F for ; Fri, 25 Mar 2022 20:07:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232348AbiCYUId (ORCPT ); Fri, 25 Mar 2022 16:08:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232338AbiCYUH5 (ORCPT ); Fri, 25 Mar 2022 16:07:57 -0400 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4D942B18D; Fri, 25 Mar 2022 13:04:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648238654; x=1679774654; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=s157fb9lA4a8XOSEq9n0q0pdUa5Gw9sK4n7L6BfC7jE=; b=MrfDQR4SBZpLVpd9l0jHg0K3ahLikmX6eJvB2DUlbkEINw81nqp+Q414 2yUclt0hO4LN/WpcJ1TTe9cvCHXGSDJyeOQnt9poPvC6qNSNNCzRegFnn hTdgKhIHW0o8dkT8uXKL6Cx3R2f/omlJfVy2N4ZDmQ2spX6WuveAuk1Lr k/T+mcCHsMkzb5aGp0UP8NuC2Gc7fRAJ2PStf7OKd+9JRK5K6gFC5HiFQ eJ234Vu2Jg3c9UnvPE685VVxbaP2QpDPQ/faXJXM6mFGvbTXFHrFVqkmA JltaEOhW0I7ClVxX8YyR6M++1lG4AKVQ9iwtL0uEy4HeP1LeEEValWtWW w==; X-IronPort-AV: E=McAfee;i="6200,9189,10297"; a="257537296" X-IronPort-AV: E=Sophos;i="5.90,211,1643702400"; d="scan'208";a="257537296" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2022 13:04:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,211,1643702400"; d="scan'208";a="638321942" Received: from black.fi.intel.com ([10.237.72.28]) by FMSMGA003.fm.intel.com with ESMTP; 25 Mar 2022 13:04:09 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 8C8E61C8; Fri, 25 Mar 2022 22:04:30 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , Gregory CLEMENT , Geert Uytterhoeven , Fabien Dessenne , Linus Walleij , linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Cc: Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Andrew Lunn , Sebastian Hesselbarth , Maxime Coquelin , Alexandre Torgue , Bartosz Golaszewski Subject: [PATCH v1 3/5] pinctrl: renesas: Replace custom code by gpiochip_count() call Date: Fri, 25 Mar 2022 22:03:36 +0200 Message-Id: <20220325200338.54270-3-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220325200338.54270-1-andriy.shevchenko@linux.intel.com> References: <20220325200338.54270-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Since we have generic function to count GPIO controller nodes under given device, there is no need to open code it. Replace custom code by gpiochip_count() call. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/renesas/pinctrl-rza1.c | 17 +---------------- 1 file changed, 1 insertion(+), 16 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rza1.c b/drivers/pinctrl/renesas/pinctrl-rza1.c index c1d6e9512c7a..c66e72e7dd71 100644 --- a/drivers/pinctrl/renesas/pinctrl-rza1.c +++ b/drivers/pinctrl/renesas/pinctrl-rza1.c @@ -1154,21 +1154,6 @@ static const struct pinmux_ops rza1_pinmux_ops = { * RZ/A1 pin controller driver operations */ -static unsigned int rza1_count_gpio_chips(struct device_node *np) -{ - struct device_node *child; - unsigned int count = 0; - - for_each_child_of_node(np, child) { - if (!of_property_read_bool(child, "gpio-controller")) - continue; - - count++; - } - - return count; -} - /** * rza1_parse_gpiochip() - parse and register a gpio chip and pin range * @@ -1255,7 +1240,7 @@ static int rza1_gpio_register(struct rza1_pinctrl *rza1_pctl) unsigned int i; int ret; - ngpiochips = rza1_count_gpio_chips(np); + ngpiochips = gpiochip_count(rza1_pctl->dev); if (ngpiochips == 0) { dev_dbg(rza1_pctl->dev, "No gpiochip registered\n"); return 0; From patchwork Fri Mar 25 20:03:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 554145 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B496C433FE for ; Fri, 25 Mar 2022 20:06:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231922AbiCYUIc (ORCPT ); Fri, 25 Mar 2022 16:08:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232339AbiCYUH5 (ORCPT ); Fri, 25 Mar 2022 16:07:57 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24CE02BB19; Fri, 25 Mar 2022 13:04:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648238655; x=1679774655; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+3cMN1f1lEcXuRBrNDyNybfnJAqjD8jUdUQVryZwyuU=; b=VGbWWgqKbqXccXQql6hhvf8UAJkQJ6ZRaxfzgmH2DkLmuc1H//obZUyN Ev4MPix2rKWPgIqduFRM5sAoC4/6XGJ2ORuIFWU2C2XmNTl19WkzH9dgE GcExgFY7xAwFwf8Qsy/W6tvD8xXwY0bEqBSBLIGse1JkapXVlm/eRjP3L fOaYRBr3i65Sg/Mdy/gsrIFBo1alTeWdzlal6E5JCX29dM8Veao4sxs1n JPkts368v6zLr1YmsOteitgqyf7QkmmQKwrL7hjKzyKx1VABcxI/8m/Bw U7F0r+JPdsdnWdRK8eYn88BEplqn++SzIT60y8mwVH9CgAPORtXl7uzMp g==; X-IronPort-AV: E=McAfee;i="6200,9189,10297"; a="258427150" X-IronPort-AV: E=Sophos;i="5.90,211,1643702400"; d="scan'208";a="258427150" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2022 13:04:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,211,1643702400"; d="scan'208";a="561956350" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga008.jf.intel.com with ESMTP; 25 Mar 2022 13:04:10 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id A508B314; Fri, 25 Mar 2022 22:04:30 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , Gregory CLEMENT , Geert Uytterhoeven , Fabien Dessenne , Linus Walleij , linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Cc: Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Andrew Lunn , Sebastian Hesselbarth , Maxime Coquelin , Alexandre Torgue , Bartosz Golaszewski Subject: [PATCH v1 5/5] pinctrl: armada-37xx: Replace custom code by gpiochip_count() call Date: Fri, 25 Mar 2022 22:03:38 +0200 Message-Id: <20220325200338.54270-5-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220325200338.54270-1-andriy.shevchenko@linux.intel.com> References: <20220325200338.54270-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Since we have generic function to count GPIO controller nodes under given device, there is no need to open code it. Replace custom code by gpiochip_count() call. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 24 +++++++++------------ 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 08cad14042e2..ba94125f6566 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -728,22 +728,18 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, struct gpio_irq_chip *girq = &gc->irq; struct device *dev = &pdev->dev; struct device_node *np; - int ret = -ENODEV, i, nr_irq_parent; + unsigned int nr_child_nodes, i; + int ret; /* Check if we have at least one gpio-controller child node */ - for_each_child_of_node(dev->of_node, np) { - if (of_property_read_bool(np, "gpio-controller")) { - ret = 0; - break; - } - } - if (ret) - return dev_err_probe(dev, ret, "no gpio-controller child node\n"); + nr_child_nodes = gpiochip_count(dev); + if (!nr_child_nodes) + return dev_err_probe(dev, -ENODEV, "no gpio-controller child node\n"); - nr_irq_parent = of_irq_count(np); spin_lock_init(&info->irq_lock); - if (!nr_irq_parent) { + nr_child_nodes = of_irq_count(np); + if (!nr_child_nodes) { dev_err(dev, "invalid or no IRQ\n"); return 0; } @@ -766,11 +762,11 @@ static int armada_37xx_irqchip_register(struct platform_device *pdev, * controller. But we do not take advantage of this and use * the chained irq with all of them. */ - girq->num_parents = nr_irq_parent; - girq->parents = devm_kcalloc(dev, nr_irq_parent, sizeof(*girq->parents), GFP_KERNEL); + girq->num_parents = nr_child_nodes; + girq->parents = devm_kcalloc(dev, nr_child_nodes, sizeof(*girq->parents), GFP_KERNEL); if (!girq->parents) return -ENOMEM; - for (i = 0; i < nr_irq_parent; i++) { + for (i = 0; i < nr_child_nodes; i++) { int irq = irq_of_parse_and_map(np, i); if (irq < 0)