From patchwork Fri Mar 25 15:40:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jae Hyun Yoo X-Patchwork-Id: 554130 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11C3AC433EF for ; Fri, 25 Mar 2022 15:44:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348903AbiCYPpc (ORCPT ); Fri, 25 Mar 2022 11:45:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377906AbiCYPoJ (ORCPT ); Fri, 25 Mar 2022 11:44:09 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5DFD349699 for ; Fri, 25 Mar 2022 08:41:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1648222895; x=1679758895; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CucjsfBkAdH0gqXdIIFD6ukDX3MkdK2lqPYfJFXfEXc=; b=L8kWTOnFlkmRNzr78Im/MJWbsaGgCyCfRHY9KBYVpOxqquZ3x34rPbij Pm7GPGih0mte7MiufBa1H4wQ6ZfMM7X63i0ya0BTm10mMG0mLREVFngwH djBeRw0le+hEMvBT/PKPvnvCUE8ZL//S3oI/CQ2FqvgHVOVVUBdS7prim A=; Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 25 Mar 2022 08:41:34 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg08-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2022 08:41:34 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 25 Mar 2022 08:41:33 -0700 Received: from maru.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 25 Mar 2022 08:41:32 -0700 From: Jae Hyun Yoo To: Rob Herring , Joel Stanley , "Andrew Jeffery" , Andrew Lunn CC: Jamie Iles , Graeme Gregory , , , , Johnny Huang , Jae Hyun Yoo Subject: [PATCH v2 4/5] ARM: dts: aspeed-g6: add FWQSPI group in pinctrl dtsi Date: Fri, 25 Mar 2022 08:40:47 -0700 Message-ID: <20220325154048.467245-5-quic_jaehyoo@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220325154048.467245-1-quic_jaehyoo@quicinc.com> References: <20220325154048.467245-1-quic_jaehyoo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Johnny Huang Add FWSPIDQ2 and FWSPIDQ3 group to support AST2600 FW SPI quad mode. These pins can be used with dedicated FW SPI pins - FWSPICS0#, FWSPICK, FWSPIMOSI and FWSPIMISO. Signed-off-by: Johnny Huang Signed-off-by: Jae Hyun Yoo --- Changes in v2: * None. arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi index 06d60a8540e9..47c3fb137cbc 100644 --- a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi +++ b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi @@ -117,6 +117,11 @@ pinctrl_fwspid_default: fwspid_default { groups = "FWSPID"; }; + pinctrl_fwqspi_default: fwqspi_default { + function = "FWQSPI"; + groups = "FWQSPI"; + }; + pinctrl_fwspiwp_default: fwspiwp_default { function = "FWSPIWP"; groups = "FWSPIWP"; From patchwork Fri Mar 25 15:40:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jae Hyun Yoo X-Patchwork-Id: 554129 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AA2AC43217 for ; Fri, 25 Mar 2022 15:44:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1354918AbiCYPpf (ORCPT ); Fri, 25 Mar 2022 11:45:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377905AbiCYPoJ (ORCPT ); Fri, 25 Mar 2022 11:44:09 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C816649900 for ; Fri, 25 Mar 2022 08:41:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1648222895; x=1679758895; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IFcwkw0ChYMrKdMzLxdkJFRH7VV3hwdHok6sJeSzKZc=; b=RmIhZiE+je4nAxlVWCcQ7EIq9AcCjf9VvuUPZgI4uKHaWZdF0c2C8Pk5 GdVtERmZxYe+fhhHksyaRmLlzsCd3IUTJZk1/LOyrkK1n4ypN/6te47+7 AJpOnZmAnvroGnzBlsPfcNiZbhNys8AVINdw/hgPn3/R6spTyOYOVWUuz 0=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-01.qualcomm.com with ESMTP; 25 Mar 2022 08:41:35 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg02-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2022 08:41:35 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 25 Mar 2022 08:41:34 -0700 Received: from maru.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Fri, 25 Mar 2022 08:41:33 -0700 From: Jae Hyun Yoo To: Rob Herring , Joel Stanley , "Andrew Jeffery" , Andrew Lunn CC: Jamie Iles , Graeme Gregory , , , , "Jae Hyun Yoo" Subject: [PATCH v2 5/5] ARM: dts: aspeed-g6: fix SPI1/SPI2 quad pin group Date: Fri, 25 Mar 2022 08:40:48 -0700 Message-ID: <20220325154048.467245-6-quic_jaehyoo@quicinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220325154048.467245-1-quic_jaehyoo@quicinc.com> References: <20220325154048.467245-1-quic_jaehyoo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Fix incorrect function mappings in pinctrl_qspi1_default and pinctrl_qspi2_default since there function should be SPI1 and SPI2 respectively. Signed-off-by: Jae Hyun Yoo Fixes: f510f04c8c83 ("ARM: dts: aspeed: Add AST2600 pinmux nodes") --- Changes in v2: * None. arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi index 47c3fb137cbc..7cd4f075e325 100644 --- a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi +++ b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi @@ -653,12 +653,12 @@ pinctrl_pwm9g1_default: pwm9g1_default { }; pinctrl_qspi1_default: qspi1_default { - function = "QSPI1"; + function = "SPI1"; groups = "QSPI1"; }; pinctrl_qspi2_default: qspi2_default { - function = "QSPI2"; + function = "SPI2"; groups = "QSPI2"; };