From patchwork Fri Mar 18 20:13:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 553064 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5725AC433F5 for ; Fri, 18 Mar 2022 20:13:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240525AbiCRUO6 (ORCPT ); Fri, 18 Mar 2022 16:14:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239791AbiCRUO5 (ORCPT ); Fri, 18 Mar 2022 16:14:57 -0400 Received: from ssl.serverraum.org (ssl.serverraum.org [IPv6:2a01:4f8:151:8464::1:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B8A20196121; Fri, 18 Mar 2022 13:13:37 -0700 (PDT) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 13D44223EA; Fri, 18 Mar 2022 21:13:35 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1647634415; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qWHNfVem7DZQ9oD5nMVySWgz28W4v66+TQrxd7Lt7Z8=; b=JuFSQTwDVWbz7sIcbfUAdfS2Km6tULGL5wmzoGO87bt1s0fM3zkczwM/zMOxX32cL6mg43 H3G0xhgaEbp5Jvgc9723wR0RI3sUPZt71eIB32Zb1aG8GlKJABbQgR8y87VG5e6FH8VWvV X9XoXqDBCPXRz3mUriPgAs3juX56K2k= From: Michael Walle To: "David S . Miller" , Jakub Kicinski , Rob Herring , Krzysztof Kozlowski , Andrew Lunn , Heiner Kallweit , Russell King Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Horatiu Vultur , Michael Walle Subject: [PATCH net-next v3 1/3] dt-bindings: net: mscc-miim: add lan966x compatible Date: Fri, 18 Mar 2022 21:13:22 +0100 Message-Id: <20220318201324.1647416-2-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220318201324.1647416-1-michael@walle.cc> References: <20220318201324.1647416-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The MDIO controller has support to release the internal PHYs from reset by specifying a second memory resource. This is different between the currently supported SparX-5 and the LAN966x. Add a new compatible to distinguish between these two. Signed-off-by: Michael Walle Acked-by: Horatiu Vultur --- Documentation/devicetree/bindings/net/mscc-miim.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/mscc-miim.txt b/Documentation/devicetree/bindings/net/mscc-miim.txt index 7104679cf59d..70e0cb1ee485 100644 --- a/Documentation/devicetree/bindings/net/mscc-miim.txt +++ b/Documentation/devicetree/bindings/net/mscc-miim.txt @@ -2,7 +2,7 @@ Microsemi MII Management Controller (MIIM) / MDIO ================================================= Properties: -- compatible: must be "mscc,ocelot-miim" +- compatible: must be "mscc,ocelot-miim" or "microchip,lan966x-miim" - reg: The base address of the MDIO bus controller register bank. Optionally, a second register bank can be defined if there is an associated reset register for internal PHYs From patchwork Fri Mar 18 20:13:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 553065 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB36DC433EF for ; Fri, 18 Mar 2022 20:13:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240512AbiCRUO6 (ORCPT ); Fri, 18 Mar 2022 16:14:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39122 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235797AbiCRUO5 (ORCPT ); Fri, 18 Mar 2022 16:14:57 -0400 Received: from ssl.serverraum.org (ssl.serverraum.org [IPv6:2a01:4f8:151:8464::1:2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B5BF218A7A9; Fri, 18 Mar 2022 13:13:37 -0700 (PDT) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id D61AA223EF; Fri, 18 Mar 2022 21:13:35 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1647634416; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8eeLDjh6XapUMf/oGuY0biPxASPRa2wiMP2QiDHhD0Y=; b=ju1TVEchIP157lqBA6dKazAzpJnVAQhCe/+uNB34ljJO3oGHPkyg7xtyX/yyYBKuu6h0zT P/vVglkrxbkPmBk6gphjR1Tb91YqeiA1YPhr0hxufciym2wqJQmhAbpnXkyUGko85z2cWX llnDWpF7LCkqv5fM+EsiQaEyFQj7zVw= From: Michael Walle To: "David S . Miller" , Jakub Kicinski , Rob Herring , Krzysztof Kozlowski , Andrew Lunn , Heiner Kallweit , Russell King Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Horatiu Vultur , Michael Walle Subject: [PATCH net-next v3 2/3] net: mdio: mscc-miim: replace magic numbers for the bus reset Date: Fri, 18 Mar 2022 21:13:23 +0100 Message-Id: <20220318201324.1647416-3-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220318201324.1647416-1-michael@walle.cc> References: <20220318201324.1647416-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Replace the magic numbers by macros which are already defined. It seems the original commit missed to use them. Signed-off-by: Michael Walle --- drivers/net/mdio/mdio-mscc-miim.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/mdio/mdio-mscc-miim.c b/drivers/net/mdio/mdio-mscc-miim.c index 64fb76c1e395..2f77bf75288d 100644 --- a/drivers/net/mdio/mdio-mscc-miim.c +++ b/drivers/net/mdio/mdio-mscc-miim.c @@ -158,18 +158,18 @@ static int mscc_miim_reset(struct mii_bus *bus) { struct mscc_miim_dev *miim = bus->priv; int offset = miim->phy_reset_offset; + int reset_bits = PHY_CFG_PHY_ENA | PHY_CFG_PHY_COMMON_RESET | + PHY_CFG_PHY_RESET; int ret; if (miim->phy_regs) { - ret = regmap_write(miim->phy_regs, - MSCC_PHY_REG_PHY_CFG + offset, 0); + ret = regmap_write(miim->phy_regs, offset, 0); if (ret < 0) { WARN_ONCE(1, "mscc reset set error %d\n", ret); return ret; } - ret = regmap_write(miim->phy_regs, - MSCC_PHY_REG_PHY_CFG + offset, 0x1ff); + ret = regmap_write(miim->phy_regs, offset, reset_bits); if (ret < 0) { WARN_ONCE(1, "mscc reset clear error %d\n", ret); return ret; @@ -272,7 +272,7 @@ static int mscc_miim_probe(struct platform_device *pdev) miim = bus->priv; miim->phy_regs = phy_regmap; - miim->phy_reset_offset = 0; + miim->phy_reset_offset = MSCC_PHY_REG_PHY_CFG; ret = of_mdiobus_register(bus, pdev->dev.of_node); if (ret < 0) { From patchwork Fri Mar 18 20:13:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 552677 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25049C433EF for ; Fri, 18 Mar 2022 20:13:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240532AbiCRUO7 (ORCPT ); Fri, 18 Mar 2022 16:14:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39198 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239948AbiCRUO6 (ORCPT ); Fri, 18 Mar 2022 16:14:58 -0400 Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE1DE19C5BF; Fri, 18 Mar 2022 13:13:37 -0700 (PDT) Received: from mwalle01.kontron.local. (unknown [213.135.10.150]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 29670223F0; Fri, 18 Mar 2022 21:13:36 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1647634416; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/DLo4n9LcEDq3m+ys72xRNV4+0sMmookIoTiaSxWb4Y=; b=HzaHDuVAE8+iwwhaowp63U1TPFyre7RwmpUi4gQjsQp30EUulJxZ0AooOJhxb2BVQKzPYR rs6vJYVvu1aZWwJgm06g8yTg21Efc+zq1kNhnuO3/PvHfc7C5JUkNsbi1uYS/P4jwc5loz RE2dUUCqtB2dXk0DUW/h/QqXDa0dPJQ= From: Michael Walle To: "David S . Miller" , Jakub Kicinski , Rob Herring , Krzysztof Kozlowski , Andrew Lunn , Heiner Kallweit , Russell King Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Horatiu Vultur , Michael Walle Subject: [PATCH net-next v3 3/3] net: mdio: mscc-miim: add lan966x internal phy reset support Date: Fri, 18 Mar 2022 21:13:24 +0100 Message-Id: <20220318201324.1647416-4-michael@walle.cc> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220318201324.1647416-1-michael@walle.cc> References: <20220318201324.1647416-1-michael@walle.cc> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The LAN966x has two internal PHYs which are in reset by default. The driver already supported the internal PHYs of the SparX-5. Now add support for the LAN966x, too. Add a new compatible to distinguish them. The LAN966x has additional control bits in this register, thus convert the regmap_write() to regmap_update_bits() to leave the remaining bits untouched. This doesn't change anything for the SparX-5 SoC, because there, the register consists only of reset bits. Signed-off-by: Michael Walle --- drivers/net/mdio/mdio-mscc-miim.c | 67 ++++++++++++++++++++++--------- 1 file changed, 49 insertions(+), 18 deletions(-) diff --git a/drivers/net/mdio/mdio-mscc-miim.c b/drivers/net/mdio/mdio-mscc-miim.c index 2f77bf75288d..c483ba67c21f 100644 --- a/drivers/net/mdio/mdio-mscc-miim.c +++ b/drivers/net/mdio/mdio-mscc-miim.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #define MSCC_MIIM_REG_STATUS 0x0 @@ -36,11 +37,19 @@ #define PHY_CFG_PHY_RESET (BIT(5) | BIT(6) | BIT(7) | BIT(8)) #define MSCC_PHY_REG_PHY_STATUS 0x4 +#define LAN966X_CUPHY_COMMON_CFG 0x0 +#define CUPHY_COMMON_CFG_RESET_N BIT(0) + +struct mscc_miim_info { + unsigned int phy_reset_offset; + unsigned int phy_reset_bits; +}; + struct mscc_miim_dev { struct regmap *regs; int mii_status_offset; struct regmap *phy_regs; - int phy_reset_offset; + const struct mscc_miim_info *info; }; /* When high resolution timers aren't built-in: we can't use usleep_range() as @@ -157,27 +166,29 @@ static int mscc_miim_write(struct mii_bus *bus, int mii_id, static int mscc_miim_reset(struct mii_bus *bus) { struct mscc_miim_dev *miim = bus->priv; - int offset = miim->phy_reset_offset; - int reset_bits = PHY_CFG_PHY_ENA | PHY_CFG_PHY_COMMON_RESET | - PHY_CFG_PHY_RESET; + unsigned int offset, bits; int ret; - if (miim->phy_regs) { - ret = regmap_write(miim->phy_regs, offset, 0); - if (ret < 0) { - WARN_ONCE(1, "mscc reset set error %d\n", ret); - return ret; - } + if (!miim->phy_regs) + return 0; - ret = regmap_write(miim->phy_regs, offset, reset_bits); - if (ret < 0) { - WARN_ONCE(1, "mscc reset clear error %d\n", ret); - return ret; - } + offset = miim->info->phy_reset_offset; + bits = miim->info->phy_reset_bits; + + ret = regmap_update_bits(miim->phy_regs, offset, bits, 0); + if (ret < 0) { + WARN_ONCE(1, "mscc reset set error %d\n", ret); + return ret; + } - mdelay(500); + ret = regmap_update_bits(miim->phy_regs, offset, bits, bits); + if (ret < 0) { + WARN_ONCE(1, "mscc reset clear error %d\n", ret); + return ret; } + mdelay(500); + return 0; } @@ -272,7 +283,10 @@ static int mscc_miim_probe(struct platform_device *pdev) miim = bus->priv; miim->phy_regs = phy_regmap; - miim->phy_reset_offset = MSCC_PHY_REG_PHY_CFG; + + miim->info = device_get_match_data(&pdev->dev); + if (!miim->info) + return -EINVAL; ret = of_mdiobus_register(bus, pdev->dev.of_node); if (ret < 0) { @@ -294,8 +308,25 @@ static int mscc_miim_remove(struct platform_device *pdev) return 0; } +static const struct mscc_miim_info mscc_ocelot_miim_info = { + .phy_reset_offset = MSCC_PHY_REG_PHY_CFG, + .phy_reset_bits = PHY_CFG_PHY_ENA | PHY_CFG_PHY_COMMON_RESET | + PHY_CFG_PHY_RESET, +}; + +static const struct mscc_miim_info microchip_lan966x_miim_info = { + .phy_reset_offset = LAN966X_CUPHY_COMMON_CFG, + .phy_reset_bits = CUPHY_COMMON_CFG_RESET_N, +}; + static const struct of_device_id mscc_miim_match[] = { - { .compatible = "mscc,ocelot-miim" }, + { + .compatible = "mscc,ocelot-miim", + .data = &mscc_ocelot_miim_info + }, { + .compatible = "microchip,lan966x-miim", + .data = µchip_lan966x_miim_info + }, { } }; MODULE_DEVICE_TABLE(of, mscc_miim_match);